[gcc(refs/users/aoliva/heads/testme)] testsuite: vect: ppc: add vect_no_int_remainder

[Alexandre Oliva]

https://gcc.gnu.org/g:6eef4c6345e13d31e984b40d9b61af69bd4b4e2c

commit 6eef4c6345e13d31e984b40d9b61af69bd4b4e2c
Author: Alexandre Oliva <oliva@adacore.com>
Date:   Tue Mar 10 04:20:29 2026 -0300

    testsuite: vect: ppc: add vect_no_int_remainder
    
    vect-tsvc-s315.c fails on powerpc with altivec only because it doesn't
    support vectorized remainder on type int.
    
    Introduce vect_no_int_remainder and require it.
    
    
    for  gcc/ChangeLog
    
            * sourcebuild.texi (vect_no_int_remainder): Document.
    
    for  gcc/testsuite/ChangeLog
    
            * lib/target-supports.exp
            (check_effective_target_vect_no_int_remainder): New.
            * gcc.dg/vect/tsvc/vect-tsvc-s315.c: Don't expect
            vectorization without support for that.

Diff:
---
 gcc/doc/sourcebuild.texi                        |  3 +++
 gcc/testsuite/gcc.dg/vect/tsvc/vect-tsvc-s315.c |  2 +-
 gcc/testsuite/lib/target-supports.exp           | 11 +++++++++++
 3 files changed, 15 insertions(+), 1 deletion(-)

diff --git a/gcc/doc/sourcebuild.texi b/gcc/doc/sourcebuild.texi
index 46ebd435fb19..4b77bbc2c146 100644
--- a/gcc/doc/sourcebuild.texi
+++ b/gcc/doc/sourcebuild.texi
@@ -1738,6 +1738,9 @@ Target does not support a vector min and max instruction on @code{int}.
 @item vect_no_int_add
 Target does not support a vector add instruction on @code{int}.
 
+@item vect_no_int_remainder
+Target does not support a vector remainder instruction on @code{int}.
+
 @item vect_no_bitwise
 Target does not support vector bitwise instructions.
 
diff --git a/gcc/testsuite/gcc.dg/vect/tsvc/vect-tsvc-s315.c b/gcc/testsuite/gcc.dg/vect/tsvc/vect-tsvc-s315.c
index 8d734a0f7b65..b1b36e77fd7b 100644
--- a/gcc/testsuite/gcc.dg/vect/tsvc/vect-tsvc-s315.c
+++ b/gcc/testsuite/gcc.dg/vect/tsvc/vect-tsvc-s315.c
@@ -47,4 +47,4 @@ int main (int argc, char **argv)
   return 0;
 }
 
-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" } } */
\ No newline at end of file
+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { ! { vect_no_int_remainder } } } } } */
diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp
index 3254bdc2e9f2..e9a5f66fdbdf 100644
--- a/gcc/testsuite/lib/target-supports.exp
+++ b/gcc/testsuite/lib/target-supports.exp
@@ -8546,6 +8546,17 @@ proc check_effective_target_vect_no_int_add { } {
       expr { [istarget alpha*-*-*] }}]
 }
 
+# Return 1 if the target plus current options does not support a vector
+# remainder instruction on "int", 0 otherwise.
+#
+# This won't change for different subtargets so cache the result.
+
+proc check_effective_target_vect_no_int_remainder { } {
+    # Alpha only supports vector add on V8QI and V4HI.
+    return [check_cached_effective_target vect_no_int_remainder {
+      expr { [istarget powerpc*-*-*] && ![check_p8vector_hw_available]}}]
+}
+
 # Return 1 if the target plus current options does not support vector
 # bitwise instructions, 0 otherwise.
 #