[gcc(refs/vendors/ibm/heads/gcc-17-future)] PR target/117251: Improve vector fusion #3
Michael Meissner
meissner@gcc.gnu.org
Thu Jun 25 19:38:13 GMT 2026
https://gcc.gnu.org/g:371bade478c97fddc1e2b6c591a63bc3f0a27cd3
commit 371bade478c97fddc1e2b6c591a63bc3f0a27cd3
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Thu Jun 25 15:35:03 2026 -0400
PR target/117251: Improve vector fusion #3
See the following post for a complete explanation of what the patches
for PR target/117251:
* https://gcc.gnu.org/pipermail/gcc-patches/2025-June/686474.html
This is patch #2 of 45 to generate the 'XXEVAL' instruction on power10
and power11 instead of using the Altivec 'VANDC' instruction feeding
into 'VAND'. The 'XXEVAL' instruction can use all 64 vector registers,
instead of the 32 registers that traditional Altivec vector
instructions use. By allowing all of the vector registers to be used,
it reduces the amount of spilling that a large benchmark generated.
For vectors such as:
vector int a, b, c, d;
This patch will generate a call to xxeval if any of the registers are allocated
to traditional floating point registers:
Code: Old: New:
===== ==== ====
a = ~ ((~ (c & d)) | b); vnan xxeval a,b,c,d,16d t,c,d
vnor a,t,b
a = (c & d) ^ b; vand t,c,d xxeval a,b,c,d,30
vxor a,t,b
a = (c & d) | b; vand t,c,d xxeval a,b,c,d,31
vor a,t,b
a = (c & ~ d) ^ b; vandc t,c,d xxeval a,b,c,d,45
vxor a,t,b
a = (c & ~ d) | b; vandc t,c,d xxeval a,b,c,d,47
vor a,t,b
a = ~ ((c | ~ d) | b); vorc t,c,d xxeval a,b,c,d,64
vnor a,t,b
a = ~ ((c | ~ d) ^ b); vorc t,c,d xxeval a,b,c,d,75
veqv a,t,b
a = (c | ~ d) | ~ b; vorc t,c,d xxeval a,b,c,d,79
vorc a,t,b
Since fusion using 2 Altivec instructions is slightly faster than using
the 'XXEVAL' instruction we prefer to generate the Altivec instructions
if we can. In addition, because 'XXEVAL' is a prefixed instruction, it
possibly might generate an extra NOP instruction to align the 'XXEVAL'
instruction.
I have tested these patches on both big endian and little endian
PowerPC servers, with no regressions. Can I check these patchs into
the trunk?
2026-06-25 Michael Meissner <meissner@linux.ibm.com>
gcc/
PR target/117251
* config/rs6000/fusion.md: Regenerate.
* config/rs6000/genfusion.pl (gen_logical_addsubf): Add support
to generate vector/vector fusion if XXEVAL is supported.
Diff:
---
gcc/config/rs6000/fusion.md | 120 ++++++++++++++++++++++++-----------------
gcc/config/rs6000/genfusion.pl | 8 +++
2 files changed, 80 insertions(+), 48 deletions(-)
diff --git a/gcc/config/rs6000/fusion.md b/gcc/config/rs6000/fusion.md
index 7e404893aca5..79bfc9e238ad 100644
--- a/gcc/config/rs6000/fusion.md
+++ b/gcc/config/rs6000/fusion.md
@@ -2294,20 +2294,23 @@
;; logical-logical fusion pattern generated by gen_logical_addsubf
;; vector vorc -> veqv
(define_insn "*fuse_vorc_veqv"
- [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v")
- (not:VM (xor:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v"))
- (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))
- (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))))
- (clobber (match_scratch:VM 4 "=X,X,X,&v"))]
+ [(set (match_operand:VM 3 "vector_fusion_operand" "=&0,&1,&v,wa,v")
+ (not:VM (xor:VM (ior:VM (not:VM (match_operand:VM 0 "vector_fusion_operand" "v,v,v,wa,v"))
+ (match_operand:VM 1 "vector_fusion_operand" "v,v,v,wa,v"))
+ (match_operand:VM 2 "vector_fusion_operand" "v,v,v,wa,v"))))
+ (clobber (match_scratch:VM 4 "=X,X,X,X,&v"))]
"(TARGET_P10_FUSION)"
"@
vorc %3,%1,%0\;veqv %3,%3,%2
vorc %3,%1,%0\;veqv %3,%3,%2
vorc %3,%1,%0\;veqv %3,%3,%2
+ xxeval %x3,%x2,%x1,%x0,75
vorc %4,%1,%0\;veqv %3,%4,%2"
[(set_attr "type" "fused_vector")
(set_attr "cost" "6")
- (set_attr "length" "8")])
+ (set_attr "length" "8")
+ (set_attr "prefixed" "*,*,*,yes,*")
+ (set_attr "isa" "*,*,*,p10p,*")])
;; logical-logical fusion pattern generated by gen_logical_addsubf
;; vector vxor -> veqv
@@ -2528,20 +2531,23 @@
;; logical-logical fusion pattern generated by gen_logical_addsubf
;; vector vnand -> vnor
(define_insn "*fuse_vnand_vnor"
- [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v")
- (and:VM (not:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v"))
- (not:VM (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))))
- (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))))
- (clobber (match_scratch:VM 4 "=X,X,X,&v"))]
+ [(set (match_operand:VM 3 "vector_fusion_operand" "=&0,&1,&v,wa,v")
+ (and:VM (not:VM (ior:VM (not:VM (match_operand:VM 0 "vector_fusion_operand" "v,v,v,wa,v"))
+ (not:VM (match_operand:VM 1 "vector_fusion_operand" "v,v,v,wa,v"))))
+ (not:VM (match_operand:VM 2 "vector_fusion_operand" "v,v,v,wa,v"))))
+ (clobber (match_scratch:VM 4 "=X,X,X,X,&v"))]
"(TARGET_P10_FUSION)"
"@
vnand %3,%1,%0\;vnor %3,%3,%2
vnand %3,%1,%0\;vnor %3,%3,%2
vnand %3,%1,%0\;vnor %3,%3,%2
+ xxeval %x3,%x2,%x1,%x0,16
vnand %4,%1,%0\;vnor %3,%4,%2"
[(set_attr "type" "fused_vector")
(set_attr "cost" "6")
- (set_attr "length" "8")])
+ (set_attr "length" "8")
+ (set_attr "prefixed" "*,*,*,yes,*")
+ (set_attr "isa" "*,*,*,p10p,*")])
;; logical-logical fusion pattern generated by gen_logical_addsubf
;; vector vnor -> vnor
@@ -2582,20 +2588,23 @@
;; logical-logical fusion pattern generated by gen_logical_addsubf
;; vector vorc -> vnor
(define_insn "*fuse_vorc_vnor"
- [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v")
- (and:VM (not:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v"))
- (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")))
- (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))))
- (clobber (match_scratch:VM 4 "=X,X,X,&v"))]
+ [(set (match_operand:VM 3 "vector_fusion_operand" "=&0,&1,&v,wa,v")
+ (and:VM (not:VM (ior:VM (not:VM (match_operand:VM 0 "vector_fusion_operand" "v,v,v,wa,v"))
+ (match_operand:VM 1 "vector_fusion_operand" "v,v,v,wa,v")))
+ (not:VM (match_operand:VM 2 "vector_fusion_operand" "v,v,v,wa,v"))))
+ (clobber (match_scratch:VM 4 "=X,X,X,X,&v"))]
"(TARGET_P10_FUSION)"
"@
vorc %3,%1,%0\;vnor %3,%3,%2
vorc %3,%1,%0\;vnor %3,%3,%2
vorc %3,%1,%0\;vnor %3,%3,%2
+ xxeval %x3,%x2,%x1,%x0,64
vorc %4,%1,%0\;vnor %3,%4,%2"
[(set_attr "type" "fused_vector")
(set_attr "cost" "6")
- (set_attr "length" "8")])
+ (set_attr "length" "8")
+ (set_attr "prefixed" "*,*,*,yes,*")
+ (set_attr "isa" "*,*,*,p10p,*")])
;; logical-logical fusion pattern generated by gen_logical_addsubf
;; vector vxor -> vnor
@@ -2618,38 +2627,44 @@
;; logical-logical fusion pattern generated by gen_logical_addsubf
;; vector vand -> vor
(define_insn "*fuse_vand_vor"
- [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v")
- (ior:VM (and:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")
- (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))
- (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))
- (clobber (match_scratch:VM 4 "=X,X,X,&v"))]
+ [(set (match_operand:VM 3 "vector_fusion_operand" "=&0,&1,&v,wa,v")
+ (ior:VM (and:VM (match_operand:VM 0 "vector_fusion_operand" "v,v,v,wa,v")
+ (match_operand:VM 1 "vector_fusion_operand" "v,v,v,wa,v"))
+ (match_operand:VM 2 "vector_fusion_operand" "v,v,v,wa,v")))
+ (clobber (match_scratch:VM 4 "=X,X,X,X,&v"))]
"(TARGET_P10_FUSION)"
"@
vand %3,%1,%0\;vor %3,%3,%2
vand %3,%1,%0\;vor %3,%3,%2
vand %3,%1,%0\;vor %3,%3,%2
+ xxeval %x3,%x2,%x1,%x0,31
vand %4,%1,%0\;vor %3,%4,%2"
[(set_attr "type" "fused_vector")
(set_attr "cost" "6")
- (set_attr "length" "8")])
+ (set_attr "length" "8")
+ (set_attr "prefixed" "*,*,*,yes,*")
+ (set_attr "isa" "*,*,*,p10p,*")])
;; logical-logical fusion pattern generated by gen_logical_addsubf
;; vector vandc -> vor
(define_insn "*fuse_vandc_vor"
- [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v")
- (ior:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v"))
- (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))
- (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))
- (clobber (match_scratch:VM 4 "=X,X,X,&v"))]
+ [(set (match_operand:VM 3 "vector_fusion_operand" "=&0,&1,&v,wa,v")
+ (ior:VM (and:VM (not:VM (match_operand:VM 0 "vector_fusion_operand" "v,v,v,wa,v"))
+ (match_operand:VM 1 "vector_fusion_operand" "v,v,v,wa,v"))
+ (match_operand:VM 2 "vector_fusion_operand" "v,v,v,wa,v")))
+ (clobber (match_scratch:VM 4 "=X,X,X,X,&v"))]
"(TARGET_P10_FUSION)"
"@
vandc %3,%1,%0\;vor %3,%3,%2
vandc %3,%1,%0\;vor %3,%3,%2
vandc %3,%1,%0\;vor %3,%3,%2
+ xxeval %x3,%x2,%x1,%x0,47
vandc %4,%1,%0\;vor %3,%4,%2"
[(set_attr "type" "fused_vector")
(set_attr "cost" "6")
- (set_attr "length" "8")])
+ (set_attr "length" "8")
+ (set_attr "prefixed" "*,*,*,yes,*")
+ (set_attr "isa" "*,*,*,p10p,*")])
;; logical-logical fusion pattern generated by gen_logical_addsubf
;; vector veqv -> vor
@@ -2870,20 +2885,23 @@
;; logical-logical fusion pattern generated by gen_logical_addsubf
;; vector vorc -> vorc
(define_insn "*fuse_vorc_vorc"
- [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v")
- (ior:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v"))
- (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))
- (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))))
- (clobber (match_scratch:VM 4 "=X,X,X,&v"))]
+ [(set (match_operand:VM 3 "vector_fusion_operand" "=&0,&1,&v,wa,v")
+ (ior:VM (ior:VM (not:VM (match_operand:VM 0 "vector_fusion_operand" "v,v,v,wa,v"))
+ (match_operand:VM 1 "vector_fusion_operand" "v,v,v,wa,v"))
+ (not:VM (match_operand:VM 2 "vector_fusion_operand" "v,v,v,wa,v"))))
+ (clobber (match_scratch:VM 4 "=X,X,X,X,&v"))]
"(TARGET_P10_FUSION)"
"@
vorc %3,%1,%0\;vorc %3,%3,%2
vorc %3,%1,%0\;vorc %3,%3,%2
vorc %3,%1,%0\;vorc %3,%3,%2
+ xxeval %x3,%x2,%x1,%x0,79
vorc %4,%1,%0\;vorc %3,%4,%2"
[(set_attr "type" "fused_vector")
(set_attr "cost" "6")
- (set_attr "length" "8")])
+ (set_attr "length" "8")
+ (set_attr "prefixed" "*,*,*,yes,*")
+ (set_attr "isa" "*,*,*,p10p,*")])
;; logical-logical fusion pattern generated by gen_logical_addsubf
;; vector vxor -> vorc
@@ -2906,38 +2924,44 @@
;; logical-logical fusion pattern generated by gen_logical_addsubf
;; vector vand -> vxor
(define_insn "*fuse_vand_vxor"
- [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v")
- (xor:VM (and:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")
- (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))
- (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))
- (clobber (match_scratch:VM 4 "=X,X,X,&v"))]
+ [(set (match_operand:VM 3 "vector_fusion_operand" "=&0,&1,&v,wa,v")
+ (xor:VM (and:VM (match_operand:VM 0 "vector_fusion_operand" "v,v,v,wa,v")
+ (match_operand:VM 1 "vector_fusion_operand" "v,v,v,wa,v"))
+ (match_operand:VM 2 "vector_fusion_operand" "v,v,v,wa,v")))
+ (clobber (match_scratch:VM 4 "=X,X,X,X,&v"))]
"(TARGET_P10_FUSION)"
"@
vand %3,%1,%0\;vxor %3,%3,%2
vand %3,%1,%0\;vxor %3,%3,%2
vand %3,%1,%0\;vxor %3,%3,%2
+ xxeval %x3,%x2,%x1,%x0,30
vand %4,%1,%0\;vxor %3,%4,%2"
[(set_attr "type" "fused_vector")
(set_attr "cost" "6")
- (set_attr "length" "8")])
+ (set_attr "length" "8")
+ (set_attr "prefixed" "*,*,*,yes,*")
+ (set_attr "isa" "*,*,*,p10p,*")])
;; logical-logical fusion pattern generated by gen_logical_addsubf
;; vector vandc -> vxor
(define_insn "*fuse_vandc_vxor"
- [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v")
- (xor:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v"))
- (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))
- (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))
- (clobber (match_scratch:VM 4 "=X,X,X,&v"))]
+ [(set (match_operand:VM 3 "vector_fusion_operand" "=&0,&1,&v,wa,v")
+ (xor:VM (and:VM (not:VM (match_operand:VM 0 "vector_fusion_operand" "v,v,v,wa,v"))
+ (match_operand:VM 1 "vector_fusion_operand" "v,v,v,wa,v"))
+ (match_operand:VM 2 "vector_fusion_operand" "v,v,v,wa,v")))
+ (clobber (match_scratch:VM 4 "=X,X,X,X,&v"))]
"(TARGET_P10_FUSION)"
"@
vandc %3,%1,%0\;vxor %3,%3,%2
vandc %3,%1,%0\;vxor %3,%3,%2
vandc %3,%1,%0\;vxor %3,%3,%2
+ xxeval %x3,%x2,%x1,%x0,45
vandc %4,%1,%0\;vxor %3,%4,%2"
[(set_attr "type" "fused_vector")
(set_attr "cost" "6")
- (set_attr "length" "8")])
+ (set_attr "length" "8")
+ (set_attr "prefixed" "*,*,*,yes,*")
+ (set_attr "isa" "*,*,*,p10p,*")])
;; logical-logical fusion pattern generated by gen_logical_addsubf
;; vector veqv -> vxor
diff --git a/gcc/config/rs6000/genfusion.pl b/gcc/config/rs6000/genfusion.pl
index eb299133d1b9..d983144b0843 100755
--- a/gcc/config/rs6000/genfusion.pl
+++ b/gcc/config/rs6000/genfusion.pl
@@ -224,6 +224,14 @@ sub gen_logical_addsubf
"vorc_vand" => 11,
"vandc_vandc" => 13,
"vnand_vand" => 14,
+ "vnand_vnor" => 16,
+ "vand_vxor" => 30,
+ "vand_vor" => 31,
+ "vandc_vxor" => 45,
+ "vandc_vor" => 47,
+ "vorc_vnor" => 64,
+ "vorc_veqv" => 75,
+ "vorc_vorc" => 79,
);
KIND: foreach $kind ('scalar','vector') {
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