[gcc r16-7223] testsuite: riscv: disable scheduling for rvv/autovec/bug-3.c

[Alexandre Oliva]

https://gcc.gnu.org/g:d7a7ac3c83eecbac6555e8820905899d7f0b84c7

commit r16-7223-gd7a7ac3c83eecbac6555e8820905899d7f0b84c7
Author: Alexandre Oliva <oliva@adacore.com>
Date:   Sun Feb 1 04:35:23 2026 -0300

    testsuite: riscv: disable scheduling for rvv/autovec/bug-3.c
    
    Combine was prevented for some time from combining two ashifts when
    the substituted insn couldn't be removed, and r15-7801 changed the
    expectations to match.
    
    Combine was later allowed to combine such insns, and the scheduler
    reorders the insns so that the expected function body doesn't match.
    
    I've added options to disable scheduling, and I've restored the
    combine expectation.
    
    
    for  gcc/testsuite/ChangeLog
    
            * gcc.target/riscv/rvv/autovec/bug-3.c: Disable scheduling,
            and restore expectation of slli combine.

Diff:
---
 gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-3.c | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-3.c
index 2d5f4c2e0de0..6075d689cc4c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-3.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvl512b -mabi=lp64d -mrvv-max-lmul=m8 -mrvv-vector-bits=scalable -fno-vect-cost-model -O2 -ffast-math" } */
+/* { dg-options "-march=rv64gcv_zvl512b -mabi=lp64d -mrvv-max-lmul=m8 -mrvv-vector-bits=scalable -fno-vect-cost-model -O2 -ffast-math -fno-schedule-insns -fno-schedule-insns2" } */
 /* { dg-final { check-function-bodies "**" "" } } */
 
 #define N 16
@@ -31,8 +31,7 @@ _Complex float res[N] =
 ** ...
 ** csrr\s+[atx][0-9]+,\s*vlenb
 ** slli\s+[atx][0-9]+,\s*[atx][0-9],\s*1
-** ...
-** slli\s+[atx][0-9]+,\s*[atx][0-9],\s*32
+** slli\s+[atx][0-9]+,\s*[atx][0-9],\s*33
 ** ...
 */
 void