[gcc(refs/users/meissner/heads/work240-sha)] PR target/117251: Improve vector nand to vector xor fusion

[Michael Meissner]

https://gcc.gnu.org/g:c4732dc62af2e00b18ce6c24c069aceafd94c6ae

commit c4732dc62af2e00b18ce6c24c069aceafd94c6ae
Author: Michael Meissner <meissner@linux.ibm.com>
Date:   Fri Apr 17 00:12:26 2026 -0400

    PR target/117251: Improve vector nand to vector xor fusion
    
    See the following post for a complete explanation of what the patches
    for PR target/117251:
    
     * https://gcc.gnu.org/pipermail/gcc-patches/2025-June/686474.html
    
    This is patch #35 of 45 to generate the 'XXEVAL' instruction on power10
    and power11 instead of using the Altivec 'VNAND' instruction feeding
    into 'VXOR'.  The 'XXEVAL' instruction can use all 64 vector registers,
    instead of the 32 registers that traditional Altivec vector
    instructions use.  By allowing all of the vector registers to be used,
    it reduces the amount of spilling that a large benchmark generated.
    
    Currently the following code:
    
            vector int a, b, c, d;
            a = (~ (c & d)) ^ b;
    
    Generates:
    
            vnand  t,c,d
            vxor   a,t,b
    
    Now in addition with this patch, if the arguments or result is
    allocated to a traditional FPR register, the GCC compiler will now
    generate the following code instead of adding vector move instructions:
    
            xxeval a,b,c,225
    
    Since fusion using 2 Altivec instructions is slightly faster than using
    the 'XXEVAL' instruction we prefer to generate the Altivec instructions
    if we can.  In addition, because 'XXEVAL' is a prefixed instruction, it
    possibly might generate an extra NOP instruction to align the 'XXEVAL'
    instruction.
    
    I have tested these patches on both big endian and little endian
    PowerPC servers, with no regressions.  Can I check these patchs into
    the trunk?
    
    2026-04-16  Michael Meissner  <meissner@linux.ibm.com>
    
    gcc/
    
            PR target/117251
            * config/rs6000/fusion.md: Regenerate.
            * config/rs6000/genfusion.pl (gen_logical_addsubf): Add support
            to generate vector nand => xor fusion if XXEVAL is supported.

Diff:
---
 gcc/config/rs6000/fusion.md    | 15 +++++++++------
 gcc/config/rs6000/genfusion.pl |  1 +
 2 files changed, 10 insertions(+), 6 deletions(-)

diff --git a/gcc/config/rs6000/fusion.md b/gcc/config/rs6000/fusion.md
index 55e372f6b687..3f8e8f174109 100644
--- a/gcc/config/rs6000/fusion.md
+++ b/gcc/config/rs6000/fusion.md
@@ -3023,20 +3023,23 @@
 ;; logical-logical fusion pattern generated by gen_logical_addsubf
 ;; vector vnand -> vxor
 (define_insn "*fuse_vnand_vxor"
-  [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v")
-        (xor:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v"))
-                          (not:VM (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")))
-                 (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))
-   (clobber (match_scratch:VM 4 "=X,X,X,&v"))]
+  [(set (match_operand:VM 3 "vector_fusion_operand" "=&0,&1,&v,wa,v")
+        (xor:VM (ior:VM (not:VM (match_operand:VM 0 "vector_fusion_operand" "v,v,v,wa,v"))
+                          (not:VM (match_operand:VM 1 "vector_fusion_operand" "v,v,v,wa,v")))
+                 (match_operand:VM 2 "vector_fusion_operand" "v,v,v,wa,v")))
+   (clobber (match_scratch:VM 4 "=X,X,X,X,&v"))]
   "(TARGET_P10_FUSION)"
   "@
    vnand %3,%1,%0\;vxor %3,%3,%2
    vnand %3,%1,%0\;vxor %3,%3,%2
    vnand %3,%1,%0\;vxor %3,%3,%2
+   xxeval %x3,%x2,%x1,%x0,225
    vnand %4,%1,%0\;vxor %3,%4,%2"
   [(set_attr "type" "fused_vector")
    (set_attr "cost" "6")
-   (set_attr "length" "8")])
+   (set_attr "length" "8")
+   (set_attr "prefixed" "*,*,*,yes,*")
+   (set_attr "isa" "*,*,*,xxeval,*")])
 
 ;; logical-logical fusion pattern generated by gen_logical_addsubf
 ;; vector vnor -> vxor
diff --git a/gcc/config/rs6000/genfusion.pl b/gcc/config/rs6000/genfusion.pl
index 1da52bc8d8d3..33b083f9d6f2 100755
--- a/gcc/config/rs6000/genfusion.pl
+++ b/gcc/config/rs6000/genfusion.pl
@@ -249,6 +249,7 @@ sub gen_logical_addsubf
       "vandc_vnor"  => 208,
       "vandc_veqv"  => 210,
       "vand_vnor"   => 224,
+      "vnand_vxor"  => 225,
     );
 
     KIND: foreach $kind ('scalar','vector') {