[gcc(refs/users/meissner/heads/work222-float)] Change -mieee16 to -mfloat16; Allow use on power8.
Michael Meissner
meissner@gcc.gnu.org
Sat Sep 27 01:15:28 GMT 2025
https://gcc.gnu.org/g:310f960703989f298e37e428e45bde066a3ca9e5
commit 310f960703989f298e37e428e45bde066a3ca9e5
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Fri Sep 26 21:15:07 2025 -0400
Change -mieee16 to -mfloat16; Allow use on power8.
2025-09-25 Michael Meissner <meissner@linux.ibm.com>
gcc/
* config/rs6000/rs6000-c.cc (rs6000_target_modify_macros): Define
__FLOAT16__, __FLOAT16_HW__, __BFLOAT16__, and __BFLOAT16_HW__ based on
the options.
* config/rs6000/rs6000-call.cc (USE_FP_FOR_ARG_P): Change -mieee16 to
-mfloat16.
* config/rs6000/rs6000-cpus.def (ISA_3_0_MASKS_SERVER): Likewise.
(POWERPC_MASKS): Likewise.
* config/rs6000/rs6000.cc (rs6000_init_hard_regno_mode_ok): Likewise.
(rs6000_option_override_internal): Allow -mfloat16 and -mbfloat16 on
older systems.
(rs6000_function_value): Change -mieee16 to -mfloat16.
(rs6000_floatn_mode): Likewise.
(rs6000_opt_masks): Likewise.
* config/rs6000/rs6000.h (FP16_SCALAR_MODE_P): Likewise.
* config/rs6000/rs6000.md (FP16): Likewise.
(FP16_HW): New mode iterator.
(extendhf<mode>2): Require power9 support.
(trunc<mode>hf2): Likewise.
(extendbf<mode>2): Require power10 support.
(trunc<mode>bf2): Likewise.
(extend<FP16_HW:mode><FP16_CONVERT:mode>): Change FP16 mode iterator
FP16_HW.
(extend<FP16_HW:mode><FP16_CONVERT:mode>2): Likewise.
(trunc<FP16_CONVERT:mode><FP16_HW:mode>2): Likewise.
(float<GPR:mode><FP16_HW:mode>2): Likewise.
(floatuns<GPR:mode><FP16_HW:mode>2): Likewise.
(fix_trunc<FP16_HW:mode><GPR:mode>2): Likewise.
(fixuns_trunc<FP16_HW:mode><GPR:mode>2): Likewise.
* config/rs6000/rs6000.opt (-mfloat16): Change -mieee16 to -mfloat16.
Remove Undocumented flag.
(-mfloat16-gpr-args): Change -mieee16-gpr-args to -mfloat16-gpr-args.
* config/rs6000/vector.md (vec_pack_trunc_v4sf): Change -mieee16 to
-mfloat16.
(-mbfloat16): Remove Undocumented flag.
(vec_unpacku_float_lo_v4sf): Likewise.
* config/rs6000/vsx.md (VECTOR_16BIT): Likewise.
(VSX_L): Likewise.
(VSX_M): Likewise.
* doc/invoke.texi (PowerPC options): Document -mfloat16 and -mbfloat16.
Diff:
---
gcc/config/rs6000/rs6000-c.cc | 15 +++++++++++
gcc/config/rs6000/rs6000-call.cc | 2 +-
gcc/config/rs6000/rs6000-cpus.def | 4 +--
gcc/config/rs6000/rs6000.cc | 29 ++++++++++----------
gcc/config/rs6000/rs6000.h | 2 +-
gcc/config/rs6000/rs6000.md | 57 +++++++++++++++++++++------------------
gcc/config/rs6000/rs6000.opt | 12 ++++-----
gcc/config/rs6000/vector.md | 4 +--
gcc/config/rs6000/vsx.md | 6 ++---
gcc/doc/invoke.texi | 15 ++++++++++-
10 files changed, 89 insertions(+), 57 deletions(-)
diff --git a/gcc/config/rs6000/rs6000-c.cc b/gcc/config/rs6000/rs6000-c.cc
index 70e6d4b1e6db..3b4d4c4a09ab 100644
--- a/gcc/config/rs6000/rs6000-c.cc
+++ b/gcc/config/rs6000/rs6000-c.cc
@@ -586,6 +586,21 @@ rs6000_target_modify_macros (bool define_p,
if ((flags & OPTION_MASK_FLOAT128_HW) != 0)
rs6000_define_or_undefine_macro (define_p, "__FLOAT128_HARDWARE__");
+ /* 16-bit floating point support. */
+ if ((flags & OPTION_MASK_FLOAT16) != 0)
+ {
+ rs6000_define_or_undefine_macro (define_p, "__FLOAT16__");
+ if ((cpu_option & CPU_OPTION_POWER9_MASK) != 0)
+ rs6000_define_or_undefine_macro (define_p, "__FLOAT16_HW__");
+ }
+
+ if ((flags & OPTION_MASK_BFLOAT16) != 0)
+ {
+ rs6000_define_or_undefine_macro (define_p, "__BFLOAT16__");
+ if ((cpu_option & CPU_OPTION_POWER10_MASK) != 0)
+ rs6000_define_or_undefine_macro (define_p, "__BFLOAT16_HW__");
+ }
+
/* Tell the user if we are targeting CELL. */
if (rs6000_cpu == PROCESSOR_CELL)
rs6000_define_or_undefine_macro (define_p, "__PPU__");
diff --git a/gcc/config/rs6000/rs6000-call.cc b/gcc/config/rs6000/rs6000-call.cc
index a446897f842b..169bcee07778 100644
--- a/gcc/config/rs6000/rs6000-call.cc
+++ b/gcc/config/rs6000/rs6000-call.cc
@@ -86,7 +86,7 @@
(SCALAR_FLOAT_MODE_NOT_VECTOR_P (MODE) \
&& (CUM)->fregno <= FP_ARG_MAX_REG \
&& TARGET_HARD_FLOAT \
- && (!FP16_SCALAR_MODE_P (MODE) || !TARGET_IEEE16_GPR_ARGS))
+ && (!FP16_SCALAR_MODE_P (MODE) || !TARGET_FLOAT16_GPR_ARGS))
/* Nonzero if we can use an AltiVec register to pass this arg. */
diff --git a/gcc/config/rs6000/rs6000-cpus.def b/gcc/config/rs6000/rs6000-cpus.def
index 6b97a4f2d1e5..6d7582f93499 100644
--- a/gcc/config/rs6000/rs6000-cpus.def
+++ b/gcc/config/rs6000/rs6000-cpus.def
@@ -102,7 +102,7 @@
/* Add ISEL back into ISA 3.0, since it is supposed to be a win. Do not add
FLOAT128_HW here until we are ready to make -mfloat128 on by default. */
#define ISA_3_0_MASKS_SERVER ((ISA_2_7_MASKS_SERVER \
- /* | OPTION_MASK_IEEE16 */ \
+ /* | OPTION_MASK_FLOAT16 */ \
| OPTION_MASK_ISEL \
| OPTION_MASK_MODULO \
| OPTION_MASK_P9_MINMAX \
@@ -166,7 +166,7 @@
| OPTION_MASK_FPRND \
| OPTION_MASK_P10_FUSION \
| OPTION_MASK_HTM \
- | OPTION_MASK_IEEE16 \
+ | OPTION_MASK_FLOAT16 \
| OPTION_MASK_ISEL \
| OPTION_MASK_MFCRF \
| OPTION_MASK_MMA \
diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index 4c69eb05b2cb..a6aef3e9be38 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -2944,7 +2944,7 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p)
}
/* _Float16 support. */
- if (TARGET_IEEE16)
+ if (TARGET_FLOAT16)
{
rs6000_vector_unit[V8HFmode] = VECTOR_VSX;
rs6000_vector_mem[V8HFmode] = VECTOR_VSX;
@@ -3079,7 +3079,7 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p)
reg_addr[TFmode].reload_load = CODE_FOR_reload_tf_di_load;
}
- if (TARGET_IEEE16)
+ if (TARGET_FLOAT16)
{
reg_addr[HFmode].reload_store = CODE_FOR_reload_hf_di_store;
reg_addr[HFmode].reload_load = CODE_FOR_reload_hf_di_load;
@@ -3191,7 +3191,7 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p)
reg_addr[TFmode].reload_load = CODE_FOR_reload_tf_si_load;
}
- if (TARGET_IEEE16)
+ if (TARGET_FLOAT16)
{
reg_addr[HFmode].reload_store = CODE_FOR_reload_hf_si_store;
reg_addr[HFmode].reload_load = CODE_FOR_reload_hf_si_load;
@@ -3942,20 +3942,19 @@ rs6000_option_override_internal (bool global_init_p)
}
}
- /* -mieee16 needs power9 at a minimum. */
- if (TARGET_IEEE16 && !TARGET_P9_VECTOR)
+ /* -mfloat16 and -mbfloat16 needs VSX at a minimum. */
+ if (TARGET_FLOAT16 && !TARGET_VSX)
{
- rs6000_isa_flags &= ~OPTION_MASK_IEEE16;
- if (rs6000_isa_flags_explicit & OPTION_MASK_IEEE16)
- error ("%qs requires at least %qs", "-mieee16", "-mcpu=power9");
+ rs6000_isa_flags &= ~OPTION_MASK_FLOAT16;
+ if (rs6000_isa_flags_explicit & OPTION_MASK_FLOAT16)
+ error ("%qs requires at least %qs", "-mfloat16", "-mvsx");
}
- /* -mbfloat16 needs power10 at a minimum. */
- if (TARGET_BFLOAT16 && !TARGET_POWER10)
+ if (TARGET_BFLOAT16 && !TARGET_VSX)
{
rs6000_isa_flags &= ~OPTION_MASK_BFLOAT16;
if (rs6000_isa_flags_explicit & OPTION_MASK_BFLOAT16)
- error ("%qs requires at least %qs", "-mbfloat16", "-mcpu=power10");
+ error ("%qs requires at least %qs", "-mbfloat16", "-mvsx");
}
/* If hard-float/altivec/vsx were explicitly turned off then don't allow
@@ -24118,7 +24117,7 @@ rs6000_function_value (const_tree valtype,
if (DECIMAL_FLOAT_MODE_P (mode) && TARGET_HARD_FLOAT)
/* _Decimal128 must use an even/odd register pair. */
regno = (mode == TDmode) ? FP_ARG_RETURN + 1 : FP_ARG_RETURN;
- else if (FP16_SCALAR_MODE_P (mode) && TARGET_IEEE16_GPR_ARGS)
+ else if (FP16_SCALAR_MODE_P (mode) && TARGET_FLOAT16_GPR_ARGS)
regno = GP_ARG_RETURN;
else if (SCALAR_FLOAT_TYPE_P (valtype) && TARGET_HARD_FLOAT
&& !FLOAT128_VECTOR_P (mode))
@@ -24446,7 +24445,7 @@ rs6000_floatn_mode (int n, bool extended)
switch (n)
{
case 16:
- return TARGET_IEEE16 ? SFmode : opt_scalar_float_mode ();
+ return TARGET_FLOAT16 ? SFmode : opt_scalar_float_mode ();
case 32:
return DFmode;
@@ -24470,7 +24469,7 @@ rs6000_floatn_mode (int n, bool extended)
switch (n)
{
case 16:
- return TARGET_IEEE16 ? HFmode : opt_scalar_float_mode ();
+ return TARGET_FLOAT16 ? HFmode : opt_scalar_float_mode ();
case 32:
return SFmode;
@@ -24592,7 +24591,7 @@ static struct rs6000_opt_mask const rs6000_opt_masks[] =
{ "fprnd", OPTION_MASK_FPRND, false, true },
{ "hard-dfp", OPTION_MASK_DFP, false, true },
{ "htm", OPTION_MASK_HTM, false, true },
- { "ieee16", OPTION_MASK_IEEE16, false, true },
+ { "float16", OPTION_MASK_FLOAT16, false, true },
{ "isel", OPTION_MASK_ISEL, false, true },
{ "mfcrf", OPTION_MASK_MFCRF, false, true },
{ "mfpgpr", 0, false, true },
diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h
index 310551e87fbb..2c98d1b98493 100644
--- a/gcc/config/rs6000/rs6000.h
+++ b/gcc/config/rs6000/rs6000.h
@@ -345,7 +345,7 @@ extern const char *host_detect_local_cpu (int argc, const char **argv);
/* Is this a valid 16-bit scalar floating point mode? */
#define FP16_SCALAR_MODE_P(MODE) \
- (((MODE) == HFmode && TARGET_IEEE16) \
+ (((MODE) == HFmode && TARGET_FLOAT16) \
|| ((MODE) == BFmode && TARGET_BFLOAT16))
/* Return true for floating point that does not use a vector register. */
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 1f5d659b8bca..5486d9489e18 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -861,7 +861,12 @@
;; Mode iterator for 16-bit floating modes.
(define_mode_iterator FP16 [(BF "TARGET_BFLOAT16")
- (HF "TARGET_IEEE16")])
+ (HF "TARGET_FLOAT16")])
+
+;; Mode iterator for 16-bit floating modes on machines with hardware
+;; support.
+(define_mode_iterator FP16_HW [(BF "TARGET_BFLOAT16 && TARGET_POWER10")
+ (HF "TARGET_FLOAT16 && TARGET_POWER9")])
;; Mode iterator for floating point modes other than SF/DFmode that we
;; convert to/from _Float16 (HFmode) via DFmode.
@@ -5866,7 +5871,7 @@
[(set (match_operand:SFDF 0 "vsx_register_operand" "=wa")
(float_extend:SFDF
(match_operand:HF 1 "vsx_register_operand" "wa")))]
- "TARGET_IEEE16"
+ "TARGET_FLOAT16 && TARGET_POWER9"
"xscvhpdp %x0,%x1"
[(set_attr "type" "fpsimple")])
@@ -5874,7 +5879,7 @@
[(set (match_operand:HF 0 "vsx_register_operand" "=wa")
(float_truncate:HF
(match_operand:SFDF 1 "vsx_register_operand" "wa")))]
- "TARGET_IEEE16"
+ "TARGET_FLOAT16 && TARGET_POWER9"
"xscvdphp %x0,%x1"
[(set_attr "type" "fpsimple")])
@@ -5888,7 +5893,7 @@
(float_extend:SFDF
(match_operand:BF 1 "vsx_register_operand" "v")))
(clobber (match_scratch:V8BF 2 "=v"))]
- "TARGET_BFLOAT16"
+ "TARGET_BFLOAT16 && TARGET_POWER10"
"#"
"&& 1"
[(pc)]
@@ -5928,7 +5933,7 @@
(float_truncate:BF
(match_operand:SFDF 1 "vsx_register_operand" "wa")))
(clobber (match_scratch:V4SF 2 "=wa"))]
- "TARGET_BFLOAT16"
+ "TARGET_BFLOAT16 && TARGET_POWER10"
"#"
"&& 1"
[(pc)]
@@ -5951,14 +5956,14 @@
;; Use DFmode to convert to/from 16-bit floating point types for
;; scalar floating point types other than SF/DFmode.
-(define_expand "extend<FP16:mode><FP16_CONVERT:mode>2"
+(define_expand "extend<FP16_HW:mode><FP16_CONVERT:mode>2"
[(set (match_operand:FP16_CONVERT 0 "vsx_register_operand")
(float_extend:FP16_CONVERT
- (match_operand:FP16 1 "vsx_register_operand")))]
+ (match_operand:FP16_HW 1 "vsx_register_operand")))]
""
{
rtx df_tmp = gen_reg_rtx (DFmode);
- emit_insn (gen_extend<FP16:mode>df2 (df_tmp, operands[1]));
+ emit_insn (gen_extend<FP16_HW:mode>df2 (df_tmp, operands[1]));
/* convert_move handles things like conversion to Decimal types that
we don't have extenddfdd2 insns, so a call is made to do the
@@ -5967,9 +5972,9 @@
DONE;
})
-(define_expand "trunc<FP16_CONVERT:mode><FP16:mode>2"
- [(set (match_operand:FP16 0 "vsx_register_operand")
- (float_truncate:FP16
+(define_expand "trunc<FP16_CONVERT:mode><FP16_HW:mode>2"
+ [(set (match_operand:FP16_HW 0 "vsx_register_operand")
+ (float_truncate:FP16_HW
(match_operand:FP16_CONVERT 1 "vsx_register_operand")))]
""
{
@@ -5980,56 +5985,56 @@
the conversion. */
convert_move (df_tmp, operands[1], 0);
- emit_insn (gen_truncdf<FP16:mode>2 (operands[0], df_tmp));
+ emit_insn (gen_truncdf<FP16_HW:mode>2 (operands[0], df_tmp));
DONE;
})
;; Convert integers to 16-bit floating point modes.
-(define_expand "float<GPR:mode><FP16:mode>2"
- [(set (match_operand:FP16 0 "vsx_register_operand")
- (float:FP16
+(define_expand "float<GPR:mode><FP16_HW:mode>2"
+ [(set (match_operand:FP16_HW 0 "vsx_register_operand")
+ (float:FP16_HW
(match_operand:GPR 1 "nonimmediate_operand")))]
""
{
rtx df_tmp = gen_reg_rtx (DFmode);
emit_insn (gen_float<GPR:mode>df2 (df_tmp, operands[1]));
- emit_insn (gen_truncdf<FP16:mode>2 (operands[0], df_tmp));
+ emit_insn (gen_truncdf<FP16_HW:mode>2 (operands[0], df_tmp));
DONE;
})
-(define_expand "floatuns<GPR:mode><FP16:mode>2"
- [(set (match_operand:FP16 0 "vsx_register_operand")
- (unsigned_float:FP16
+(define_expand "floatuns<GPR:mode><FP16_HW:mode>2"
+ [(set (match_operand:FP16_HW 0 "vsx_register_operand")
+ (unsigned_float:FP16_HW
(match_operand:GPR 1 "nonimmediate_operand")))]
""
{
rtx df_tmp = gen_reg_rtx (DFmode);
emit_insn (gen_floatuns<GPR:mode>df2 (df_tmp, operands[1]));
- emit_insn (gen_truncdf<FP16:mode>2 (operands[0], df_tmp));
+ emit_insn (gen_truncdf<FP16_HW:mode>2 (operands[0], df_tmp));
DONE;
})
;; Convert 16-bit floating point modes to integers
-(define_expand "fix_trunc<FP16:mode><GPR:mode>2"
+(define_expand "fix_trunc<FP16_HW:mode><GPR:mode>2"
[(set (match_operand:GPR 0 "vsx_register_operand")
(fix:GPR
- (match_operand:FP16 1 "vsx_register_operand")))]
+ (match_operand:FP16_HW 1 "vsx_register_operand")))]
""
{
rtx df_tmp = gen_reg_rtx (DFmode);
- emit_insn (gen_extend<FP16:mode>df2 (df_tmp, operands[1]));
+ emit_insn (gen_extend<FP16_HW:mode>df2 (df_tmp, operands[1]));
emit_insn (gen_fix_truncdf<GPR:mode>2 (operands[0], df_tmp));
DONE;
})
-(define_expand "fixuns_trunc<FP16:mode><GPR:mode>2"
+(define_expand "fixuns_trunc<FP16_HW:mode><GPR:mode>2"
[(set (match_operand:GPR 0 "vsx_register_operand")
(unsigned_fix:GPR
- (match_operand:FP16 1 "vsx_register_operand")))]
+ (match_operand:FP16_HW 1 "vsx_register_operand")))]
""
{
rtx df_tmp = gen_reg_rtx (DFmode);
- emit_insn (gen_extend<FP16:mode>df2 (df_tmp, operands[1]));
+ emit_insn (gen_extend<FP16_HW:mode>df2 (df_tmp, operands[1]));
emit_insn (gen_fixuns_truncdf<GPR:mode>2 (operands[0], df_tmp));
DONE;
})
diff --git a/gcc/config/rs6000/rs6000.opt b/gcc/config/rs6000/rs6000.opt
index 1db4e28508af..8198fc07f02f 100644
--- a/gcc/config/rs6000/rs6000.opt
+++ b/gcc/config/rs6000/rs6000.opt
@@ -638,16 +638,16 @@ mieee128-constant
Target Var(TARGET_IEEE128_CONSTANT) Init(1) Save
Generate (do not generate) code that uses the LXVKQ instruction.
-mieee16
-Target Undocumented Mask(IEEE16) Var(rs6000_isa_flags)
+mfloat16
+Target Mask(FLOAT16) Var(rs6000_isa_flags)
Enable or disable _Float16 support.
-mieee16-gpr-args
-Target Undocumented Var(TARGET_IEEE16_GPR_ARGS) Init(1) Save
-Pass _Float16 in GPR registers.
+mfloat16-gpr-args
+Target Undocumented Var(TARGET_FLOAT16_GPR_ARGS) Init(0) Save
+Pass and return _Float16 and __bfloat16 in GPR registers.
mbfloat16
-Target Undocumented Mask(BFLOAT16) Var(rs6000_isa_flags)
+Target Mask(BFLOAT16) Var(rs6000_isa_flags)
Enable or disable __bfloat16 support.
; Documented parameters
diff --git a/gcc/config/rs6000/vector.md b/gcc/config/rs6000/vector.md
index 0a9f092c1951..883cc3dbf516 100644
--- a/gcc/config/rs6000/vector.md
+++ b/gcc/config/rs6000/vector.md
@@ -1226,7 +1226,7 @@
[(match_operand:V8HF 0 "vfloat_operand")
(match_operand:V4SF 1 "vfloat_operand")
(match_operand:V4SF 2 "vfloat_operand")]
- "TARGET_IEEE16"
+ "TARGET_FLOAT16"
{
rtx r1 = gen_reg_rtx (V8HFmode);
rtx r2 = gen_reg_rtx (V8HFmode);
@@ -1313,7 +1313,7 @@
(define_expand "vec_unpacks_hi_v8hf"
[(match_operand:V4SF 0 "vfloat_operand")
(match_operand:V8HF 1 "vfloat_operand")]
- "TARGET_IEEE16"
+ "TARGET_FLOAT16"
{
rtx reg = gen_reg_rtx (V8HFmode);
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index 111457b8fe2e..49c208e115f4 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -49,13 +49,13 @@
;; Iterator for 8 element vectors
(define_mode_iterator VECTOR_16BIT [V8HI
(V8BF "TARGET_BFLOAT16")
- (V8HF "TARGET_IEEE16")])
+ (V8HF "TARGET_FLOAT16")])
;; Iterator for logical types supported by VSX
(define_mode_iterator VSX_L [V16QI
V8HI
(V8BF "TARGET_BFLOAT16")
- (V8HF "TARGET_IEEE16")
+ (V8HF "TARGET_FLOAT16")
V4SI
V2DI
V4SF
@@ -69,7 +69,7 @@
(define_mode_iterator VSX_M [V16QI
V8HI
(V8BF "TARGET_BFLOAT16")
- (V8HF "TARGET_IEEE16")
+ (V8HF "TARGET_FLOAT16")
V4SI
V2DI
V4SF
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index 76ecea550f31..98084d560dfc 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -1363,7 +1363,8 @@ See RS/6000 and PowerPC Options.
-mstack-protector-guard=@var{guard} -mstack-protector-guard-reg=@var{reg}
-mstack-protector-guard-offset=@var{offset} -mprefixed -mno-prefixed
-mpcrel -mno-pcrel -mmma -mno-mmma -mrop-protect -mno-rop-protect
--mprivileged -mno-privileged}
+-mprivileged -mno-privileged
+-mfloat16 -mno-float16 -mbfloat16 -mno-bfloat16}
@emph{RX Options} (@ref{RX Options})
@gccoptlist{-m64bit-doubles -m32bit-doubles -fpu -nofpu
@@ -32963,6 +32964,18 @@ optimization (@option{-fshrink-wrap}).
@itemx -mno-privileged
Generate (do not generate) code that will run in privileged state.
+@opindex mfloat16
+@opindex mno-float16
+@item -mfloat16
+@itemx -mno-float16
+Allow (do not allow) use of the @code{__Float16} type.
+
+@opindex mbfloat16
+@opindex mno-bfloat16
+@item -mbfloat16
+@itemx -mno-bfloat16
+Allow (do not allow) use of the @code{__bfloat16} type.
+
@opindex block-ops-unaligned-vsx
@opindex no-block-ops-unaligned-vsx
@item -mblock-ops-unaligned-vsx
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