[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [RISC-V] Fix ordering of pipeline models

[Jeff Law]

https://gcc.gnu.org/g:a15da95c39125605d408a072b8e3953e364c43a1

commit a15da95c39125605d408a072b8e3953e364c43a1
Author: Jeff Law <jlaw@ventanamicro.com>
Date:   Sun Sep 7 12:11:55 2025 -0600

    [RISC-V] Fix ordering of pipeline models
    
    I missed that the new ascalon pipeline description was put into the wrong place
    during review.  The net is tests which wanted to use generic-ooo explicitly for
    stability in the test output ended up getting  a different pipeline model and
    different codegen than the test expected.
    
    This tripped a small number of vsetvl failures in the testsuite.
    
    This has spun on riscv64-elf and riscv32-elf in my tester and fixes the
    regression.  I'm going to go ahead and push it as I'm likely offline this
    afternoon/evening and don't want anyone else to waste their time chasing the
    regression down.
    
    gcc/
            * config/riscv/riscv-opts.h (riscv_microarchitecture_type): Fix ordering.
    
    (cherry picked from commit 2b7afb69ab42367cd926bffb26ba713e51b91914)

Diff:
---
 gcc/config/riscv/riscv-opts.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h
index 54f89781a55e..4e4e9d8930e2 100644
--- a/gcc/config/riscv/riscv-opts.h
+++ b/gcc/config/riscv/riscv-opts.h
@@ -57,10 +57,10 @@ enum riscv_microarchitecture_type {
   sifive_7,
   sifive_p400,
   sifive_p600,
-  tt_ascalon_d8,
   xiangshan,
   generic_ooo,
   mips_p8700,
+  tt_ascalon_d8,
 };
 extern enum riscv_microarchitecture_type riscv_microarchitecture;