[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Fix scalar code-gen of unsigned SAT_MUL

[Jeff Law]

https://gcc.gnu.org/g:c4b696032b4b08df2572cabb0e97f6f3dc15d340

commit c4b696032b4b08df2572cabb0e97f6f3dc15d340
Author: Pan Li <pan2.li@intel.com>
Date:   Thu Jul 31 12:32:24 2025 +0800

    RISC-V: Fix scalar code-gen of unsigned SAT_MUL
    
    The previous code-gen of scalar unsigned SAT_MUL, aka usmul.
    Leverage the mulhs by mistake, it should be mulhu for the
    hight bit result of mul.  Thus, this patch would like to make
    it correct.
    
    gcc/ChangeLog:
    
            * config/riscv/riscv.cc (riscv_expand_xmode_usmul): Take
            umulhu for high bits mul result.
    
    gcc/testsuite/ChangeLog:
    
            * gcc.target/riscv/sat/sat_u_mul-1-u32-from-u64.c: Add mulhu
            asm check.
            * gcc.target/riscv/sat/sat_u_mul-1-u64-from-u128.c: Ditto.
    
    Signed-off-by: Pan Li <pan2.li@intel.com>
    (cherry picked from commit 01a784e7c5e724be3ff5ab663eb288d3ed66100b)

Diff:
---
 gcc/config/riscv/riscv.cc                                      | 4 ++--
 gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-1-u32-from-u64.c  | 2 ++
 gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-1-u64-from-u128.c | 1 +
 3 files changed, 5 insertions(+), 2 deletions(-)

diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index b342f1218c2c..d0ed83bd6ba9 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -13851,9 +13851,9 @@ riscv_expand_xmode_usmul (rtx dest, rtx x, rtx y)
   riscv_emit_binary (MULT, mul, x, y);
 
   if (TARGET_64BIT)
-    emit_insn (gen_usmuldi3_highpart (mulhu, x, y));
+    emit_insn (gen_umuldi3_highpart (mulhu, x, y));
   else
-    emit_insn (gen_usmulsi3_highpart (mulhu, x, y));
+    emit_insn (gen_umulsi3_highpart (mulhu, x, y));
 
   riscv_emit_binary (NE, overflow_p, mulhu, CONST0_RTX (Xmode));
   riscv_emit_unary (NEG, overflow_p, overflow_p);
diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-1-u32-from-u64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-1-u32-from-u64.c
index 8d5449bf3493..fa3758a2f547 100644
--- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-1-u32-from-u64.c
+++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-1-u32-from-u64.c
@@ -9,3 +9,5 @@
 DEF_SAT_U_MUL_FMT_1_WRAP(NT, WT)
 
 /* { dg-final { scan-tree-dump-times ".SAT_MUL" 1 "optimized" } } */
+/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */
+/* { dg-final { scan-assembler-times "mulhu" 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-1-u64-from-u128.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-1-u64-from-u128.c
index d8a01d1a06fa..b1bf4fae968b 100644
--- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-1-u64-from-u128.c
+++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-1-u64-from-u128.c
@@ -10,3 +10,4 @@ DEF_SAT_U_MUL_FMT_1_WRAP(NT, WT)
 
 /* { dg-final { scan-tree-dump-times ".SAT_MUL" 1 "optimized" } } */
 /* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */
+/* { dg-final { scan-assembler-times "mulhu" 1 } } */