[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [PATCH v2 1/2] The following changes enable P8700 processor for RISCV and P8700 is a high-performanc
Jeff Law
law@gcc.gnu.org
Sat Sep 13 16:08:20 GMT 2025
https://gcc.gnu.org/g:28eefd4624438329fa0cf7e5acd66cc51c7510db
commit 28eefd4624438329fa0cf7e5acd66cc51c7510db
Author: Umesh Kalappa <ukalappa.mips@gmail.com>
Date: Tue May 20 11:50:46 2025 -0600
[PATCH v2 1/2] The following changes enable P8700 processor for RISCV and P8700 is a high-performance processor from MIPS by extending RISCV with custom instructions
Add support for the p8700 design from MIPS.
gcc/
* config/riscv/mips-p8700.md: New scheduler model.
* config/riscv/riscv-cores.def (mips-p87000): New tuning model
and core architecture.
* config/riscv/riscv-opts.h (riscv_microarchitecture_type); Add
mips-p8700.
* config/riscv/riscv.cc (mips_p8700_tune_info): New uarch
tuning parameters.
* config/riscv/riscv.md (tune): Add mips_p8700.
Include mips-p8700.md
* doc/invoke.texi: Document tune/cpu options for the MIPS P8700.
Co-authored-by: Jeff Law <jlaw@ventanamicro.com>
(cherry picked from commit 1186a2bd6e187d512030233171293ee87b608189)
Diff:
---
gcc/config/riscv/mips-p8700.md | 139 +++++++++++++++++++++++++++++++++++++++
gcc/config/riscv/riscv-cores.def | 5 ++
gcc/config/riscv/riscv-opts.h | 3 +-
gcc/config/riscv/riscv.cc | 22 +++++++
gcc/config/riscv/riscv.md | 3 +-
gcc/doc/invoke.texi | 14 ++--
6 files changed, 177 insertions(+), 9 deletions(-)
diff --git a/gcc/config/riscv/mips-p8700.md b/gcc/config/riscv/mips-p8700.md
new file mode 100644
index 000000000000..11d0b1ca7930
--- /dev/null
+++ b/gcc/config/riscv/mips-p8700.md
@@ -0,0 +1,139 @@
+;; DFA-based pipeline description for MIPS P8700.
+;;
+;; Copyright (C) 2025 Free Software Foundation, Inc.
+;;
+;; This file is part of GCC.
+;;
+;; GCC is free software; you can redistribute it and/or modify it
+;; under the terms of the GNU General Public License as published
+;; by the Free Software Foundation; either version 3, or (at your
+;; option) any later version.
+
+;; GCC is distributed in the hope that it will be useful, but WITHOUT
+;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+;; License for more details.
+
+;; You should have received a copy of the GNU General Public License
+;; along with GCC; see the file COPYING3. If not see
+;; <http://www.gnu.org/licenses/>.
+
+(define_automaton "mips_p8700_agen_alq_pipe, mips_p8700_mdu_pipe, mips_p8700_fpu_pipe")
+
+;; The address generation queue (AGQ) has AL2, CTISTD and LDSTA pipes
+(define_cpu_unit "mips_p8700_agq, mips_p8700_al2, mips_p8700_ctistd, mips_p8700_lsu"
+ "mips_p8700_agen_alq_pipe")
+
+(define_cpu_unit "mips_p8700_gpmul, mips_p8700_gpdiv" "mips_p8700_mdu_pipe")
+
+;; The arithmetic-logic-unit queue (ALQ) has ALU pipe
+(define_cpu_unit "mips_p8700_alq, mips_p8700_alu" "mips_p8700_agen_alq_pipe")
+
+;; The floating-point-unit queue (FPQ) has short and long pipes
+(define_cpu_unit "mips_p8700_fpu_short, mips_p8700_fpu_long" "mips_p8700_fpu_pipe")
+
+;; Long FPU pipeline.
+(define_cpu_unit "mips_p8700_fpu_apu" "mips_p8700_fpu_pipe")
+
+(define_reservation "mips_p8700_agq_al2" "mips_p8700_agq, mips_p8700_al2")
+(define_reservation "mips_p8700_agq_ctistd" "mips_p8700_agq, mips_p8700_ctistd")
+(define_reservation "mips_p8700_agq_lsu" "mips_p8700_agq, mips_p8700_lsu")
+(define_reservation "mips_p8700_alq_alu" "mips_p8700_alq, mips_p8700_alu")
+
+;;
+;; FPU pipe
+;;
+
+(define_insn_reservation "mips_p8700_fpu_fadd" 4
+ (and (eq_attr "tune" "mips_p8700")
+ (eq_attr "type" "fadd"))
+ "mips_p8700_fpu_long, mips_p8700_fpu_apu")
+
+(define_insn_reservation "mips_p8700_fpu_fabs" 2
+ (and (eq_attr "tune" "mips_p8700")
+ (eq_attr "type" "fcmp,fmove"))
+ "mips_p8700_fpu_short, mips_p8700_fpu_apu")
+
+(define_insn_reservation "mips_p8700_fpu_fload" 8
+ (and (eq_attr "tune" "mips_p8700")
+ (eq_attr "type" "fpload"))
+ "mips_p8700_agq_lsu")
+
+(define_insn_reservation "mips_p8700_fpu_fstore" 1
+ (and (eq_attr "tune" "mips_p8700")
+ (eq_attr "type" "fpstore"))
+ "mips_p8700_agq_lsu")
+
+(define_insn_reservation "mips_p8700_fpu_fmadd" 8
+ (and (eq_attr "tune" "mips_p8700")
+ (eq_attr "type" "fmadd"))
+ "mips_p8700_fpu_long, mips_p8700_fpu_apu")
+
+(define_insn_reservation "mips_p8700_fpu_fmul" 5
+ (and (eq_attr "tune" "mips_p8700")
+ (eq_attr "type" "fmul"))
+ "mips_p8700_fpu_long, mips_p8700_fpu_apu")
+
+(define_insn_reservation "mips_p8700_fpu_div" 17
+ (and (eq_attr "tune" "mips_p8700")
+ (eq_attr "type" "fdiv,fsqrt"))
+ "mips_p8700_fpu_long, mips_p8700_fpu_apu*17")
+
+(define_insn_reservation "mips_p8700_fpu_fcvt" 4
+ (and (eq_attr "tune" "mips_p8700")
+ (eq_attr "type" "fcvt,fcvt_i2f,fcvt_f2i"))
+ "mips_p8700_fpu_long, mips_p8700_fpu_apu")
+
+(define_insn_reservation "mips_p8700_fpu_fmtc" 7
+ (and (eq_attr "tune" "mips_p8700")
+ (eq_attr "type" "mtc"))
+ "mips_p8700_agq_lsu")
+
+(define_insn_reservation "mips_p8700_fpu_fmfc" 7
+ (and (eq_attr "tune" "mips_p8700")
+ (eq_attr "type" "mfc"))
+ "mips_p8700_agq_lsu")
+
+;;
+;; Integer pipe
+;;
+
+(define_insn_reservation "mips_p8700_int_load" 4
+ (and (eq_attr "tune" "mips_p8700")
+ (eq_attr "type" "load"))
+ "mips_p8700_agq_lsu")
+
+(define_insn_reservation "mips_p8700_int_store" 3
+ (and (eq_attr "tune" "mips_p8700")
+ (eq_attr "type" "store"))
+ "mips_p8700_agq_lsu")
+
+(define_insn_reservation "mips_p8700_int_arith_1" 1
+ (and (eq_attr "tune" "mips_p8700")
+ (eq_attr "type" "unknown,const,arith,shift,slt,multi,auipc,logical,move,bitmanip,min,max,minu,maxu,clz,ctz,rotate,atomic,condmove,crypto,mvpair,zicond"))
+ "mips_p8700_alq_alu | mips_p8700_agq_al2")
+
+(define_insn_reservation "mips_p8700_int_nop" 0
+ (and (eq_attr "tune" "mips_p8700")
+ (eq_attr "type" "nop"))
+ "mips_p8700_alq_alu | mips_p8700_agq_al2")
+
+(define_insn_reservation "mips_p8700_dsp_mult" 4
+ (and (eq_attr "tune" "mips_p8700")
+ (eq_attr "type" "imul,cpop,clmul"))
+ "mips_p8700_gpmul")
+
+(define_insn_reservation "mips_p8700_int_div" 8
+ (and (eq_attr "tune" "mips_p8700")
+ (eq_attr "type" "idiv"))
+ "mips_p8700_gpdiv*5")
+
+(define_insn_reservation "mips_p8700_int_branch" 1
+ (and (eq_attr "tune" "mips_p8700")
+ (eq_attr "type" "branch,jump,ret,sfb_alu,trap"))
+ "mips_p8700_agq_ctistd")
+
+(define_insn_reservation "mips_p8700_int_call" 2
+ (and (eq_attr "tune" "mips_p8700")
+ (eq_attr "type" "call,jalr"))
+ "mips_p8700_agq_ctistd")
diff --git a/gcc/config/riscv/riscv-cores.def b/gcc/config/riscv/riscv-cores.def
index e31afc3fe701..118fef23cad4 100644
--- a/gcc/config/riscv/riscv-cores.def
+++ b/gcc/config/riscv/riscv-cores.def
@@ -50,6 +50,7 @@ RISCV_TUNE("xt-c920v2", generic, generic_ooo_tune_info)
RISCV_TUNE("xiangshan-nanhu", xiangshan, xiangshan_nanhu_tune_info)
RISCV_TUNE("generic-ooo", generic_ooo, generic_ooo_tune_info)
RISCV_TUNE("size", generic, optimize_size_tune_info)
+RISCV_TUNE("mips-p8700", mips_p8700, mips_p8700_tune_info)
#undef RISCV_TUNE
@@ -152,4 +153,8 @@ RISCV_CORE("xiangshan-nanhu", "rv64imafdc_zba_zbb_zbc_zbs_"
"zbkb_zbkc_zbkx_zknd_zkne_zknh_zksed_zksh_"
"svinval_zicbom_zicboz",
"xiangshan-nanhu")
+
+RISCV_CORE("mips-p8700", "rv64imafd_zicsr_zmmul_"
+ "zaamo_zalrsc_zba_zbb",
+ "mips-p8700")
#undef RISCV_CORE
diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h
index 0f3bca5bb7c7..c02c599ed397 100644
--- a/gcc/config/riscv/riscv-opts.h
+++ b/gcc/config/riscv/riscv-opts.h
@@ -58,7 +58,8 @@ enum riscv_microarchitecture_type {
sifive_p400,
sifive_p600,
xiangshan,
- generic_ooo
+ generic_ooo,
+ mips_p8700,
};
extern enum riscv_microarchitecture_type riscv_microarchitecture;
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 955a3580d3a6..025158c302a1 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -642,6 +642,28 @@ static const struct riscv_tune_param optimize_size_tune_info = {
NULL, /* loop_align */
};
+/* Costs to use when optimizing for MIPS P8700 */
+static const struct riscv_tune_param mips_p8700_tune_info = {
+ {COSTS_N_INSNS (4), COSTS_N_INSNS (4)}, /* fp_add */
+ {COSTS_N_INSNS (5), COSTS_N_INSNS (5)}, /* fp_mul */
+ {COSTS_N_INSNS (17), COSTS_N_INSNS (17)}, /* fp_div */
+ {COSTS_N_INSNS (5), COSTS_N_INSNS (5)}, /* int_mul */
+ {COSTS_N_INSNS (8), COSTS_N_INSNS (8)}, /* int_div */
+ 4, /* issue_rate */
+ 8, /* branch_cost */
+ 4, /* memory_cost */
+ 8, /* fmv_cost */
+ true, /* slow_unaligned_access */
+ false, /* vector_unaligned_access */
+ true, /* use_divmod_expansion */
+ false, /* overlap_op_by_pieces */
+ RISCV_FUSE_NOTHING, /* fusible_ops */
+ NULL, /* vector cost */
+ NULL, /* function_align */
+ NULL, /* jump_align */
+ NULL, /* loop_align */
+};
+
static bool riscv_avoid_shrink_wrapping_separate ();
static tree riscv_handle_fndecl_attribute (tree *, tree, tree, int, bool *);
static tree riscv_handle_type_attribute (tree *, tree, tree, int, bool *);
diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index eb9d89c641fa..e22feca4babf 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -672,7 +672,7 @@
;; Microarchitectures we know how to tune for.
;; Keep this in sync with enum riscv_microarchitecture.
(define_attr "tune"
- "generic,sifive_7,sifive_p400,sifive_p600,xiangshan,generic_ooo"
+ "generic,sifive_7,sifive_p400,sifive_p600,xiangshan,generic_ooo,mips_p8700"
(const (symbol_ref "((enum attr_tune) riscv_microarchitecture)")))
;; Describe a user's asm statement.
@@ -4869,3 +4869,4 @@
(include "zc.md")
(include "corev.md")
(include "xiangshan.md")
+(include "mips-p8700.md")
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index 2687e0cd5542..09c555b76671 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -31127,12 +31127,12 @@ extension set if they weren't added explicitly.
@item -mcpu=@var{processor-string}
Use architecture of and optimize the output for the given processor, specified
by particular CPU name.
-Permissible values for this option are: @samp{sifive-e20}, @samp{sifive-e21},
-@samp{sifive-e24}, @samp{sifive-e31}, @samp{sifive-e34}, @samp{sifive-e76},
-@samp{sifive-s21}, @samp{sifive-s51}, @samp{sifive-s54}, @samp{sifive-s76},
-@samp{sifive-u54}, @samp{sifive-u74}, @samp{sifive-x280}, @samp{sifive-xp450},
-@samp{sifive-x670}, @samp{thead-c906}, @samp{tt-ascalon-d8}, @samp{xiangshan-nanhu},
-@samp{xt-c908}, @samp{xt-c908v}, @samp{xt-c910}, @samp{xt-c910v2},
+Permissible values for this option are: @samp{mips-p8700}, @samp{sifive-e20},
+@samp{sifive-e21}, @samp{sifive-e24}, @samp{sifive-e31}, @samp{sifive-e34},
+@samp{sifive-e76}, @samp{sifive-s21}, @samp{sifive-s51}, @samp{sifive-s54},
+@samp{sifive-s76}, @samp{sifive-u54}, @samp{sifive-u74}, @samp{sifive-x280},
+@samp{sifive-xp450}, @samp{sifive-x670}, @samp{thead-c906}, @samp{tt-ascalon-d8},
+@samp{xiangshan-nanhu}, @samp{xt-c908}, @samp{xt-c908v}, @samp{xt-c910}, @samp{xt-c910v2},
@samp{xt-c920}, @samp{xt-c920v2}.
Note that @option{-mcpu} does not override @option{-march} or @option{-mtune}.
@@ -31141,7 +31141,7 @@ Note that @option{-mcpu} does not override @option{-march} or @option{-mtune}.
@item -mtune=@var{processor-string}
Optimize the output for the given processor, specified by microarchitecture or
particular CPU name. Permissible values for this option are:
-@samp{generic-ooo}, @samp{rocket}, @samp{sifive-3-series},
+@samp{generic-ooo}, @samp{mips-p8700}, @samp{rocket}, @samp{sifive-3-series},
@samp{sifive-5-series}, @samp{sifive-7-series}, @samp{size},
@samp{sifive-p400-series}, @samp{sifive-p600-series}, and all valid options for
@option{-mcpu=}.
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