[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [PATCH] [RISC-V]Support -mcpu for Xuantie cpu
Jeff Law
law@gcc.gnu.org
Sat Sep 13 16:00:46 GMT 2025
https://gcc.gnu.org/g:4f89088344f6f5b9245f20efc5fdad56748d9b22
commit 4f89088344f6f5b9245f20efc5fdad56748d9b22
Author: Yixuan Chen <chenyixuan@iscas.ac.cn>
Date: Tue Apr 22 04:45:44 2025 -0600
[PATCH] [RISC-V]Support -mcpu for Xuantie cpu
Support -mcpu=xt-c908, xt-c908v, xt-c910, xt-c910v2, xt-c920, xt-c920v2
for Xuantie series cpu.
ref:https://www.xrvm.cn/community/download?id=4224248662731067392
without fmv_cost, vector_unaligned_access, use_divmod_expansion, overlap_op_by_pieces, fill the tune info with generic ooo for further modification.
gcc/ChangeLog:
* config/riscv/riscv-cores.def (RISCV_TUNE): Add xt-c908, xt-c908v,
xt-c910, xt-c910v2, xt-c920, xt-c920v2.
(RISCV_CORE): Add xt-c908, xt-c908v, xt-c910, xt-c910v2, xt-c920,
xt-c920v2.
* doc/invoke.texi: Add xt-c908, xt-c908v, xt-c910, xt-c910v2,
xt-c920, xt-c920v2.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/mcpu-xt-c908.c: test -mcpu=xt-c908.
* gcc.target/riscv/mcpu-xt-c910.c: test -mcpu=xt-c910.
* gcc.target/riscv/mcpu-xt-c920v2.c: test -mcpu=xt-c920v2.
* gcc.target/riscv/mcpu-xt-c908v.c: test -mcpu=xt-c908v.
* gcc.target/riscv/mcpu-xt-c910v2.c: test -mcpu=xt-c910v2.
* gcc.target/riscv/mcpu-xt-c920.c: test -mcpu=xt-c920.
(cherry picked from commit bd8a48500c1e775ab9cb4a737314cb800444ab4b)
Diff:
---
gcc/config/riscv/riscv-cores.def | 48 +++++++++++++++++++++
gcc/doc/invoke.texi | 5 ++-
gcc/testsuite/gcc.target/riscv/mcpu-xt-c908.c | 48 +++++++++++++++++++++
gcc/testsuite/gcc.target/riscv/mcpu-xt-c908v.c | 50 ++++++++++++++++++++++
gcc/testsuite/gcc.target/riscv/mcpu-xt-c910.c | 35 ++++++++++++++++
gcc/testsuite/gcc.target/riscv/mcpu-xt-c910v2.c | 51 ++++++++++++++++++++++
gcc/testsuite/gcc.target/riscv/mcpu-xt-c920.c | 34 +++++++++++++++
gcc/testsuite/gcc.target/riscv/mcpu-xt-c920v2.c | 56 +++++++++++++++++++++++++
8 files changed, 325 insertions(+), 2 deletions(-)
diff --git a/gcc/config/riscv/riscv-cores.def b/gcc/config/riscv/riscv-cores.def
index 2918496bcd06..e31afc3fe701 100644
--- a/gcc/config/riscv/riscv-cores.def
+++ b/gcc/config/riscv/riscv-cores.def
@@ -41,6 +41,12 @@ RISCV_TUNE("sifive-p400-series", sifive_p400, sifive_p400_tune_info)
RISCV_TUNE("sifive-p600-series", sifive_p600, sifive_p600_tune_info)
RISCV_TUNE("tt-ascalon-d8", generic_ooo, tt_ascalon_d8_tune_info)
RISCV_TUNE("thead-c906", generic, thead_c906_tune_info)
+RISCV_TUNE("xt-c908", generic, generic_ooo_tune_info)
+RISCV_TUNE("xt-c908v", generic, generic_ooo_tune_info)
+RISCV_TUNE("xt-c910", generic, generic_ooo_tune_info)
+RISCV_TUNE("xt-c910v2", generic, generic_ooo_tune_info)
+RISCV_TUNE("xt-c920", generic, generic_ooo_tune_info)
+RISCV_TUNE("xt-c920v2", generic, generic_ooo_tune_info)
RISCV_TUNE("xiangshan-nanhu", xiangshan, xiangshan_nanhu_tune_info)
RISCV_TUNE("generic-ooo", generic_ooo, generic_ooo_tune_info)
RISCV_TUNE("size", generic, optimize_size_tune_info)
@@ -93,6 +99,48 @@ RISCV_CORE("thead-c906", "rv64imafdc_xtheadba_xtheadbb_xtheadbs_xtheadcmo_"
"xtheadmemidx_xtheadmempair_xtheadsync",
"thead-c906")
+RISCV_CORE("xt-c908", "rv64imafdc_zicbom_zicbop_zicboz_zicntr_zicsr_"
+ "zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_"
+ "sstc_svinval_svnapot_svpbmt_xtheadba_xtheadbb_"
+ "xtheadbs_xtheadcmo_xtheadcondmov_xtheadfmemidx_"
+ "xtheadmac_xtheadmemidx_xtheadmempair_xtheadsync",
+ "xt-c908")
+RISCV_CORE("xt-c908v", "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicsr_"
+ "zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_"
+ "zvfh_sstc_svinval_svnapot_svpbmt__xtheadba_"
+ "xtheadbb_xtheadbs_xtheadcmo_xtheadcondmov_"
+ "xtheadfmemidx_xtheadmac_xtheadmemidx_"
+ "xtheadmempair_xtheadsync_xtheadvdot",
+ "xt-c908")
+RISCV_CORE("xt-c910", "rv64imafdc_zicntr_zicsr_zifencei_zihpm_zfh_"
+ "xtheadba_xtheadbb_xtheadbs_xtheadcmo_"
+ "xtheadcondmov_xtheadfmemidx_xtheadmac_"
+ "xtheadmemidx_xtheadmempair_xtheadsync",
+ "xt-c910")
+RISCV_CORE("xt-c910v2", "rv64imafdc_zicbom_zicbop_zicboz_zicntr_zicond_"
+ "zicsr_zifencei _zihintntl_zihintpause_zihpm_"
+ "zawrs_zfa_zfbfmin_zfh_zca_zcb_zcd_zba_zbb_zbc_"
+ "zbs_sscofpmf_sstc_svinval_svnapot_svpbmt_"
+ "xtheadba_xtheadbb_xtheadbs_xtheadcmo_"
+ "xtheadcondmov_xtheadfmemidx_xtheadmac_"
+ "xtheadmemidx_xtheadmempair_xtheadsync",
+ "xt-c910v2")
+RISCV_CORE("xt-c920", "rv64imafdc_zicntr_zicsr_zifencei_zihpm_zfh_"
+ "xtheadba_xtheadbb_xtheadbs_xtheadcmo_"
+ "xtheadcondmov_xtheadfmemidx_xtheadmac_"
+ "xtheadmemidx_xtheadmempair_xtheadsync_"
+ "xtheadvector",
+ "xt-c910")
+RISCV_CORE("xt-c920v2", "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_"
+ "zicsr_zifencei _zihintntl_zihintpause_zihpm_"
+ "zawrs_zfa_zfbfmin_zfh_zca_zcb_zcd_zba_zbb_zbc_"
+ "zbs_zvfbfmin_zvfbfwma_zvfh_sscofpmf_sstc_"
+ "svinval_svnapot_svpbmt_xtheadba_xtheadbb_"
+ "xtheadbs_xtheadcmo_xtheadcondmov_xtheadfmemidx_"
+ "xtheadmac_xtheadmemidx_xtheadmempair_"
+ "xtheadsync_xtheadvdot",
+ "xt-c920v2")
+
RISCV_CORE("tt-ascalon-d8", "rv64imafdcv_zic64b_zicbom_zicbop_zicboz_"
"ziccamoa_ziccif_zicclsm_ziccrse_zicond_zicsr_"
"zifencei_zihintntl_zihintpause_zimop_za64rs_"
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index 64a3131c1906..0c15fa28289c 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -31611,8 +31611,9 @@ Permissible values for this option are: @samp{sifive-e20}, @samp{sifive-e21},
@samp{sifive-e24}, @samp{sifive-e31}, @samp{sifive-e34}, @samp{sifive-e76},
@samp{sifive-s21}, @samp{sifive-s51}, @samp{sifive-s54}, @samp{sifive-s76},
@samp{sifive-u54}, @samp{sifive-u74}, @samp{sifive-x280}, @samp{sifive-xp450},
-@samp{sifive-x670}, @samp{thead-c906}, @samp{tt-ascalon-d8},
-@samp{xiangshan-nanhu}.
+@samp{sifive-x670}, @samp{thead-c906}, @samp{tt-ascalon-d8}, @samp{xiangshan-nanhu},
+@samp{xt-c908}, @samp{xt-c908v}, @samp{xt-c910}, @samp{xt-c910v2},
+@samp{xt-c920}, @samp{xt-c920v2}.
Note that @option{-mcpu} does not override @option{-march} or @option{-mtune}.
diff --git a/gcc/testsuite/gcc.target/riscv/mcpu-xt-c908.c b/gcc/testsuite/gcc.target/riscv/mcpu-xt-c908.c
new file mode 100644
index 000000000000..cb28baf1ce72
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/mcpu-xt-c908.c
@@ -0,0 +1,48 @@
+/* { dg-do compile } */
+/* { dg-skip-if "-march given" { *-*-* } { "-march=*" } } */
+/* { dg-options "-mcpu=xt-c908" { target { rv64 } } } */
+/* XuanTie C908 => rv64imafdc_zicbom_zicbop_zicboz_zicntr_zicsr_zifencei_
+zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_sstc_svinval_svnapot_svpbmt_xtheadba_
+xtheadbb_xtheadbs_xtheadcmo_xtheadcondmov_xtheadfmemidx_xtheadmac_
+xtheadmemidx_xtheadmempair_xtheadsync */
+
+#if !((__riscv_xlen == 64) \
+ && !defined(__riscv_32e) \
+ && defined(__riscv_mul) \
+ && defined(__riscv_atomic) \
+ && (__riscv_flen == 64) \
+ && defined(__riscv_compressed) \
+ && defined(__riscv_zicbom) \
+ && defined(__riscv_zicbop) \
+ && defined(__riscv_zicboz) \
+ && defined(__riscv_zicntr) \
+ && defined(__riscv_zicsr) \
+ && defined(__riscv_zifencei) \
+ && defined(__riscv_zihintpause) \
+ && defined(__riscv_zihpm) \
+ && defined(__riscv_zfh) \
+ && defined(__riscv_zba) \
+ && defined(__riscv_zbb) \
+ && defined(__riscv_zbc) \
+ && defined(__riscv_zbs) \
+ && defined(__riscv_sstc) \
+ && defined(__riscv_svinval) \
+ && defined(__riscv_svnapot) \
+ && defined(__riscv_svpbmt) \
+ && defined(__riscv_xtheadba) \
+ && defined(__riscv_xtheadbb) \
+ && defined(__riscv_xtheadbs) \
+ && defined(__riscv_xtheadcmo) \
+ && defined(__riscv_xtheadcondmov) \
+ && defined(__riscv_xtheadfmemidx) \
+ && defined(__riscv_xtheadmac) \
+ && defined(__riscv_xtheadmemidx) \
+ && defined(__riscv_xtheadmempair) \
+ && defined(__riscv_xtheadsync))
+#error "unexpected arch"
+#endif
+
+int main()
+{
+ return 0;
+}
diff --git a/gcc/testsuite/gcc.target/riscv/mcpu-xt-c908v.c b/gcc/testsuite/gcc.target/riscv/mcpu-xt-c908v.c
new file mode 100644
index 000000000000..1b1ee188229f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/mcpu-xt-c908v.c
@@ -0,0 +1,50 @@
+/* { dg-do compile } */
+/* { dg-skip-if "-march given" { *-*-* } { "-march=*" } } */
+/* { dg-options "-mcpu=xt-c908v" { target { rv64 } } } */
+/* XuanTie C908v => rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicsr_zifencei_
+zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_sstc_svinval_svnapot_svpbmt_xtheadba_
+xtheadbb_xtheadbs_xtheadcmo_xtheadcondmov_xtheadfmemidx_xtheadmac_
+xtheadmemidx_xtheadmempair_xtheadsync_xtheadvdot */
+
+#if !((__riscv_xlen == 64) \
+ && !defined(__riscv_32e) \
+ && defined(__riscv_mul) \
+ && defined(__riscv_atomic) \
+ && (__riscv_flen == 64) \
+ && defined(__riscv_compressed) \
+ && defined(__riscv_v) \
+ && defined(__riscv_zicbom) \
+ && defined(__riscv_zicbop) \
+ && defined(__riscv_zicboz) \
+ && defined(__riscv_zicntr) \
+ && defined(__riscv_zicsr) \
+ && defined(__riscv_zifencei) \
+ && defined(__riscv_zihintpause) \
+ && defined(__riscv_zihpm) \
+ && defined(__riscv_zfh) \
+ && defined(__riscv_zba) \
+ && defined(__riscv_zbb) \
+ && defined(__riscv_zbc) \
+ && defined(__riscv_zbs) \
+ && defined(__riscv_sstc) \
+ && defined(__riscv_svinval) \
+ && defined(__riscv_svnapot) \
+ && defined(__riscv_svpbmt) \
+ && defined(__riscv_xtheadba) \
+ && defined(__riscv_xtheadbb) \
+ && defined(__riscv_xtheadbs) \
+ && defined(__riscv_xtheadcmo) \
+ && defined(__riscv_xtheadcondmov) \
+ && defined(__riscv_xtheadfmemidx) \
+ && defined(__riscv_xtheadmac) \
+ && defined(__riscv_xtheadmemidx) \
+ && defined(__riscv_xtheadmempair) \
+ && defined(__riscv_xtheadsync) \
+ && defined (__riscv__xtheadvdot))
+#error "unexpected arch"
+#endif
+
+int main()
+{
+ return 0;
+}
diff --git a/gcc/testsuite/gcc.target/riscv/mcpu-xt-c910.c b/gcc/testsuite/gcc.target/riscv/mcpu-xt-c910.c
new file mode 100644
index 000000000000..1e276659c3ea
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/mcpu-xt-c910.c
@@ -0,0 +1,35 @@
+/* { dg-do compile } */
+/* { dg-skip-if "-march given" { *-*-* } { "-march=*" } } */
+/* { dg-options "-mcpu=xt-c910" { target { rv64 } } } */
+/* XuanTie C910 => rv64imafdc_zicntr_zicsr_zifencei_zihpm_zfh_xtheadba_
+xtheadbb_xtheadbs_xtheadcmo_xtheadcondmov_xtheadfmemidx_xtheadmac_
+xtheadmemidx_xtheadmempair_xtheadsync */
+
+#if !((__riscv_xlen == 64) \
+ && !defined(__riscv_32e) \
+ && defined(__riscv_mul) \
+ && defined(__riscv_atomic) \
+ && (__riscv_flen == 64) \
+ && defined(__riscv_compressed) \
+ && defined(__riscv_zicntr) \
+ && defined(__riscv_zicsr) \
+ && defined(__riscv_zifencei) \
+ && defined(__riscv_zihpm) \
+ && defined(__riscv_zfh) \
+ && defined(__riscv_xtheadba) \
+ && defined(__riscv_xtheadbb) \
+ && defined(__riscv_xtheadbs) \
+ && defined(__riscv_xtheadcmo) \
+ && defined(__riscv_xtheadcondmov) \
+ && defined(__riscv_xtheadfmemidx) \
+ && defined(__riscv_xtheadmac) \
+ && defined(__riscv_xtheadmemidx) \
+ && defined(__riscv_xtheadmempair) \
+ && defined(__riscv_xtheadsync))
+#error "unexpected arch"
+#endif
+
+int main()
+{
+ return 0;
+}
diff --git a/gcc/testsuite/gcc.target/riscv/mcpu-xt-c910v2.c b/gcc/testsuite/gcc.target/riscv/mcpu-xt-c910v2.c
new file mode 100644
index 000000000000..6a54f0988780
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/mcpu-xt-c910v2.c
@@ -0,0 +1,51 @@
+/* { dg-do compile } */
+/* { dg-skip-if "-march given" { *-*-* } { "-march=*" } } */
+/* { dg-options "-mcpu=xt-c910v2" { target { rv64 } } } */
+/* XuanTie C910v2 => rv64imafdc_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_
+zifencei _zihintntl_zihintpause_zihpm_zawrs_zfa_zfbfmin_zfh_zca_zcb_zcd_zba_
+zbb_zbc_xtheadba_xtheadbb_xtheadbs_xtheadcmo_xtheadcondmov_xtheadfmemidx_
+xtheadmac_xtheadmemidx_xtheadmempair_xtheadsync */
+
+#if !((__riscv_xlen == 64) \
+ && !defined(__riscv_32e) \
+ && defined(__riscv_mul) \
+ && defined(__riscv_atomic) \
+ && (__riscv_flen == 64) \
+ && defined(__riscv_compressed) \
+ && defined(__riscv_zicbom) \
+ && defined(__riscv_zicbop) \
+ && defined(__riscv_zicboz) \
+ && defined(__riscv_zicntr) \
+ && defined(__riscv_zicond) \
+ && defined(__riscv_zicsr) \
+ && defined(__riscv_zifencei ) \
+ && defined(__riscv_zihintntl) \
+ && defined(__riscv_zihintpause) \
+ && defined(__riscv_zihpm) \
+ && defined(__riscv_zawrs) \
+ && defined(__riscv_zfa) \
+ && defined(__riscv_zfbfmin) \
+ && defined(__riscv_zfh) \
+ && defined(__riscv_zca) \
+ && defined(__riscv_zcb) \
+ && defined(__riscv_zcd) \
+ && defined(__riscv_zba) \
+ && defined(__riscv_zbb) \
+ && defined(__riscv_zbc) \
+ && defined(__riscv_xtheadba) \
+ && defined(__riscv_xtheadbb) \
+ && defined(__riscv_xtheadbs) \
+ && defined(__riscv_xtheadcmo) \
+ && defined(__riscv_xtheadcondmov) \
+ && defined(__riscv_xtheadfmemidx) \
+ && defined(__riscv_xtheadmac) \
+ && defined(__riscv_xtheadmemidx) \
+ && defined(__riscv_xtheadmempair) \
+ && defined(__riscv_xtheadsync))
+#error "unexpected arch"
+#endif
+
+int main()
+{
+ return 0;
+}
diff --git a/gcc/testsuite/gcc.target/riscv/mcpu-xt-c920.c b/gcc/testsuite/gcc.target/riscv/mcpu-xt-c920.c
new file mode 100644
index 000000000000..6bcd687e7424
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/mcpu-xt-c920.c
@@ -0,0 +1,34 @@
+/* { dg-do compile } */
+/* { dg-skip-if "-march given" { *-*-* } { "-march=*" } } */
+/* { dg-options "-mcpu=xt-c920" { target { rv64 } } } */
+/* XuanTie c920 => rv64imafdc_zicntr_zicsr_zifencei_zihpm_zfh_"xtheadba_xtheadbb_xtheadbs_xtheadcmo_xtheadcondmov_xtheadfmemidx_xtheadmac_xtheadmemidx_xtheadmempair_xtheadsync_xtheadvector */
+
+#if !((__riscv_xlen == 64) \
+ && !defined(__riscv_32e) \
+ && defined(__riscv_mul) \
+ && defined(__riscv_atomic) \
+ && (__riscv_flen == 64) \
+ && defined(__riscv_compressed) \
+ && defined(__riscv_zicntr) \
+ && defined(__riscv_zicsr) \
+ && defined(__riscv_zifencei) \
+ && defined(__riscv_zihpm) \
+ && defined(__riscv_zfh) \
+ && defined(__riscv_xtheadba) \
+ && defined(__riscv_xtheadbb) \
+ && defined(__riscv_xtheadbs) \
+ && defined(__riscv_xtheadcmo) \
+ && defined(__riscv_xtheadcondmov) \
+ && defined(__riscv_xtheadfmemidx) \
+ && defined(__riscv_xtheadmac) \
+ && defined(__riscv_xtheadmemidx) \
+ && defined(__riscv_xtheadmempair) \
+ && defined(__riscv_xtheadsync) \
+ && defined(__riscv_xtheadvector))
+#error "unexpected arch"
+#endif
+
+int main()
+{
+ return 0;
+}
diff --git a/gcc/testsuite/gcc.target/riscv/mcpu-xt-c920v2.c b/gcc/testsuite/gcc.target/riscv/mcpu-xt-c920v2.c
new file mode 100644
index 000000000000..36a6267849bf
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/mcpu-xt-c920v2.c
@@ -0,0 +1,56 @@
+/* { dg-do compile } */
+/* { dg-skip-if "-march given" { *-*-* } { "-march=*" } } */
+/* { dg-options "-mcpu=xt-c920v2" { target { rv64 } } } */
+/* XuanTie C920v2 => rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei _zihintntl_zihintpause_zihpm_zawrs_zfa_zfbfmin_zfh_zca_zcb_zcd_zba_zbb_zbc_zbs_zvfbfmin_zvfbfwma_zvfh_sscofpmf_sstc_svinval_svnapot_svpbmt_xtheadba_xtheadbb_xtheadbs_xtheadcmo_xtheadcondmov_xtheadfmemidx_xtheadsync_xtheadvdot */
+
+#if !((__riscv_xlen == 64) \
+ && !defined(__riscv_32e) \
+ && defined(__riscv_mul) \
+ && defined(__riscv_atomic) \
+ && (__riscv_flen == 64) \
+ && defined(__riscv_compressed) \
+ && defined(__riscv_v) \
+ && defined(__riscv_zicbom) \
+ && defined(__riscv_zicbop) \
+ && defined(__riscv_zicboz) \
+ && defined(__riscv_zicntr) \
+ && defined(__riscv_zicond) \
+ && defined(__riscv_zicsr) \
+ && defined(__riscv_zifencei ) \
+ && defined(__riscv_zihintntl) \
+ && defined(__riscv_zihintpause) \
+ && defined(__riscv_zihpm) \
+ && defined(__riscv_zawrs) \
+ && defined(__riscv_zfa) \
+ && defined(__riscv_zfbfmin) \
+ && defined(__riscv_zfh) \
+ && defined(__riscv_zca) \
+ && defined(__riscv_zcb) \
+ && defined(__riscv_zcd) \
+ && defined(__riscv_zba) \
+ && defined(__riscv_zbb) \
+ && defined(__riscv_zbc) \
+ && defined(__riscv_zbs) \
+ && defined(__riscv_zvfbfmin) \
+ && defined(__riscv_zvfbfwma) \
+ && defined(__riscv_zvfh) \
+ && defined(__riscv_sscofpmf) \
+ && defined(__riscv_sstc) \
+ && defined(__riscv_svinval) \
+ && defined(__riscv_svnapot) \
+ && defined(__riscv_svpbmt) \
+ && defined(__riscv_xtheadba) \
+ && defined(__riscv_xtheadbb) \
+ && defined(__riscv_xtheadbs) \
+ && defined(__riscv_xtheadcmo) \
+ && defined(__riscv_xtheadcondmov) \
+ && defined(__riscv_xtheadfmemidx) \
+ && defined(__riscv_xtheadsync) \
+ && defined(__riscv_xtheadvdot))
+#error "unexpected arch"
+#endif
+
+int main()
+{
+ return 0;
+}
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