[gcc(refs/users/meissner/heads/work221-float)] Add convert from fp scalar to __bfloat16.

[Michael Meissner]

https://gcc.gnu.org/g:52df4c41096f87b0e46b41a00983c611ba3280ac

commit 52df4c41096f87b0e46b41a00983c611ba3280ac
Author: Michael Meissner <meissner@linux.ibm.com>
Date:   Thu Sep 11 20:12:55 2025 -0400

    Add convert from fp scalar to __bfloat16.
    
    2025-09-11  Michael Meissner  <meissner@linux.ibm.com>
    
    gcc/
    
            * config/rs6000/altivec.md (altivec_vsplth_v8bf): Move location.
            * config/rs6000/rs6000.md (extendbf<mode>2): Rename xvcvbf16spn_v8bf.
            (trunc<mode>bf2): New insn.
            * config/rs6000/vsx.md (vsx_xscvdpsp_sf): Likewise.
            (vsx_xscvdpspn_sf): Likewise.
            (vsx_xvcvbf16spn_v8bf): Rename from xvcvbf16spn_v8bf.
            (xvcvspbf16_bf): New insn.

Diff:
---
 gcc/config/rs6000/altivec.md | 20 +++++++++++---------
 gcc/config/rs6000/rs6000.md  | 34 +++++++++++++++++++++++++++++++++-
 gcc/config/rs6000/vsx.md     | 26 +++++++++++++++++++++++++-
 3 files changed, 69 insertions(+), 11 deletions(-)

diff --git a/gcc/config/rs6000/altivec.md b/gcc/config/rs6000/altivec.md
index 9bfa72018f9a..ba47c4d597ab 100644
--- a/gcc/config/rs6000/altivec.md
+++ b/gcc/config/rs6000/altivec.md
@@ -2411,15 +2411,6 @@
   "vsplth %0,%1,%2"
   [(set_attr "type" "vecperm")])
 
-(define_insn "altivec_vsplth_v8bf"
-  [(set (match_operand:V8BF 0 "register_operand" "=v")
-        (unspec:V8BF [(match_operand:BF 1 "register_operand" "v")
-                      (match_operand:QI 2 "const_0_to_7_operand" "i")]
-                     UNSPEC_VSPLT_DIRECT))]
-  "TARGET_BFLOAT16"
-  "vsplth %0,%1,%2"
-  [(set_attr "type" "vecperm")])
-
 (define_expand "altivec_vspltw"
   [(use (match_operand:V4SI 0 "register_operand"))
    (use (match_operand:V4SI 1 "register_operand"))
@@ -2487,6 +2478,17 @@
 }
   [(set_attr "type" "vecperm")])
 
+;; Splat instruction needed to allow conversion of __bfloat16
+;; (i.e. BFmode) to SFmode/DFmode.
+(define_insn "altivec_vsplth_v8bf"
+  [(set (match_operand:V8BF 0 "register_operand" "=v")
+        (unspec:V8BF [(match_operand:BF 1 "register_operand" "v")
+                      (match_operand:QI 2 "const_0_to_7_operand" "i")]
+                     UNSPEC_VSPLT_DIRECT))]
+  "TARGET_BFLOAT16"
+  "vsplth %0,%1,%2"
+  [(set_attr "type" "vecperm")])
+
 (define_insn "altivec_vspltis<VI_char>"
   [(set (match_operand:VI 0 "register_operand" "=v")
 	(vec_duplicate:VI
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 10e81ad1eb2e..4ab420d1637f 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -5982,17 +5982,49 @@
   emit_insn (gen_altivec_vsplth_v8bf (op2_v8bf, op1, GEN_INT (3)));
 
   /* XVCVBF16SPN -- convert even V8BFmode elements to V4SFmode.  */
-  emit_insn (gen_xvcvbf16spn_v8bf (op2_v4sf, op2_v8bf));
+  emit_insn (gen_vsx_xvcvbf16spn_v8bf (op2_v4sf, op2_v8bf));
 
   /* XSCVSPNDP -- convert single V4SFmode element to DFmode.  */
   emit_insn (GET_MODE (op0) == SFmode
 	     ? gen_vsx_xscvspdpn_sf (op0, op2_v4sf)
 	     : gen_vsx_xscvspdpn (op0, op2_v4sf));
+
   DONE;
 }
   [(set_attr "type" "fpsimple")
    (set_attr "length" "12")])
 
+;; Convert SFmode/DFmode to BFmode.
+;; 2 instructions are generated:
+;;	XSCVDPSPN	-- convert SFmode/DFmode scalar to V4SFmode
+;;	XVCVSPBF16	-- convert V4SFmode to even V8BFmode
+
+(define_insn_and_split "trunc<mode>bf2"
+  [(set (match_operand:BF 0 "vsx_register_operand" "=wa")
+	(float_truncate:BF
+	 (match_operand:SFDF 1 "vsx_register_operand" "wa")))
+   (clobber (match_scratch:V4SF 2 "=wa"))]
+  "TARGET_BFLOAT16"
+  "#"
+  "&& 1"
+  [(pc)]
+{
+  rtx op0 = operands[0];
+  rtx op1 = operands[1];
+  rtx op2 = operands[2];
+
+  if (GET_CODE (op2) == SCRATCH)
+    op2 = gen_reg_rtx (V4SFmode);
+
+  emit_insn (GET_MODE (op1) == SFmode
+	     ? gen_vsx_xscvdpspn_sf (op2, op1)
+	     : gen_vsx_xscvdpspn (op2, op1));
+
+  emit_insn (gen_vsx_xvcvspbf16_bf (op0, op2));
+  DONE;
+}
+  [(set_attr "type" "fpsimple")])
+
 
 ;; Conversions to and from floating-point.
 
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index d2cb299fe191..111457b8fe2e 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -2390,6 +2390,14 @@
   "xscvdpsp %x0,%x1"
   [(set_attr "type" "fp")])
 
+(define_insn "vsx_xscvdpsp_sf"
+  [(set (match_operand:V4SF 0 "vsx_register_operand" "=f,?wa")
+	(unspec:V4SF [(match_operand:SF 1 "vsx_register_operand" "f,wa")]
+			      UNSPEC_VSX_CVSPDP))]
+  "VECTOR_UNIT_VSX_P (DFmode)"
+  "xscvdpsp %x0,%x1"
+  [(set_attr "type" "fp")])
+
 (define_insn "vsx_xvcvspdp_be"
   [(set (match_operand:V2DF 0 "vsx_register_operand" "=v,?wa")
      (float_extend:V2DF
@@ -2503,6 +2511,14 @@
   "xscvdpspn %x0,%x1"
   [(set_attr "type" "fp")])
 
+(define_insn "vsx_xscvdpspn_sf"
+  [(set (match_operand:V4SF 0 "vsx_register_operand" "=wa")
+	(unspec:V4SF [(match_operand:SF 1 "vsx_register_operand" "wa")]
+		     UNSPEC_VSX_CVDPSPN))]
+  "TARGET_XSCVDPSPN"
+  "xscvdpspn %x0,%x1"
+  [(set_attr "type" "fp")])
+
 (define_insn "vsx_xscvspdpn"
   [(set (match_operand:DF 0 "vsx_register_operand" "=wa")
 	(unspec:DF [(match_operand:V4SF 1 "vsx_register_operand" "wa")]
@@ -6505,7 +6521,7 @@
   "<xvcvbf16> %x0,%x1"
   [(set_attr "type" "vecfloat")])
 
-(define_insn "xvcvbf16spn_v8bf"
+(define_insn "vsx_xvcvbf16spn_v8bf"
   [(set (match_operand:V4SF 0 "vsx_register_operand" "=wa")
 	(unspec:V4SF [(match_operand:V8BF 1 "vsx_register_operand" "wa")]
 		     UNSPEC_VSX_XVCVBF16SPN))]
@@ -6513,6 +6529,14 @@
   "xvcvbf16spn %x0,%x1"
   [(set_attr "type" "vecfloat")])
 
+(define_insn "vsx_xvcvspbf16_bf"
+  [(set (match_operand:BF 0 "vsx_register_operand" "=wa")
+	(unspec:BF [(match_operand:V4SF 1 "vsx_register_operand" "wa")]
+		   UNSPEC_VSX_XVCVSPBF16))]
+  "TARGET_BFLOAT16"
+  "xvcvspbf16 %x0,%x1"
+  [(set_attr "type" "vecfloat")])
+
 (define_insn "vec_mtvsrbmi"
   [(set (match_operand:V16QI 0 "altivec_register_operand" "=v")
         (unspec:V16QI [(match_operand:QI 1 "u6bit_cint_operand" "n")]