[gcc(refs/users/meissner/heads/work221-float)] Add -mieee16 switch.

[Michael Meissner]

https://gcc.gnu.org/g:2d353e05c4e46d79d8e86f3e9eb8244345c1b26c

commit 2d353e05c4e46d79d8e86f3e9eb8244345c1b26c
Author: Michael Meissner <meissner@linux.ibm.com>
Date:   Thu Sep 11 00:58:59 2025 -0400

    Add -mieee16 switch.
    
    2025-09-11  Michael Meissner  <meissner@linux.ibm.com>
    
    gcc/
    
            * config/rs6000/rs6000-cpus.def (ISA_3_0_MASKS_SERVER): Add -mieee16
            support.
            (POWERPC_MASKS): Likewise.
            * config/rs6000/rs6000.cc (rs6000_option_override_internal): Likewise.
            (rs6000_opt_masks): Likewise.
            * config/rs6000/rs6000.h (TARGET_IEEE16): Delete.
            * config/rs6000/rs6000.opt (-mieee16): New switch.

Diff:
---
 gcc/config/rs6000/rs6000-cpus.def | 2 ++
 gcc/config/rs6000/rs6000.cc       | 9 +++++++++
 gcc/config/rs6000/rs6000.h        | 3 ---
 gcc/config/rs6000/rs6000.opt      | 4 ++++
 4 files changed, 15 insertions(+), 3 deletions(-)

diff --git a/gcc/config/rs6000/rs6000-cpus.def b/gcc/config/rs6000/rs6000-cpus.def
index df833e3d54b4..5523a749f18b 100644
--- a/gcc/config/rs6000/rs6000-cpus.def
+++ b/gcc/config/rs6000/rs6000-cpus.def
@@ -61,6 +61,7 @@
 /* Add ISEL back into ISA 3.0, since it is supposed to be a win.  Do not add
    FLOAT128_HW here until we are ready to make -mfloat128 on by default.  */
 #define ISA_3_0_MASKS_SERVER	((ISA_2_7_MASKS_SERVER			\
+				  | OPTION_MASK_IEEE16			\
 				  | OPTION_MASK_ISEL			\
 				  | OPTION_MASK_MODULO			\
 				  | OPTION_MASK_P9_MINMAX		\
@@ -125,6 +126,7 @@
 				 | OPTION_MASK_POWER11			\
 				 | OPTION_MASK_P10_FUSION		\
 				 | OPTION_MASK_HTM			\
+				 | OPTION_MASK_IEEE16			\
 				 | OPTION_MASK_ISEL			\
 				 | OPTION_MASK_MFCRF			\
 				 | OPTION_MASK_MMA			\
diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index 7a6b16d30866..92511a8928b9 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -3917,6 +3917,14 @@ rs6000_option_override_internal (bool global_init_p)
 	}
     }
 
+  /* -mieee16 needs power9 at a minimum.  */
+  if (TARGET_IEEE16 && !TARGET_P9_VECTOR)
+    {
+      rs6000_isa_flags &= ~OPTION_MASK_IEEE16;
+      if (rs6000_isa_flags_explicit & OPTION_MASK_IEEE16)
+	error ("%qs requires at least %qs", "-mieee16", "-mcpu=power9");
+    }
+
   /* If hard-float/altivec/vsx were explicitly turned off then don't allow
      the -mcpu setting to enable options that conflict. */
   if ((!TARGET_HARD_FLOAT || !TARGET_ALTIVEC || !TARGET_VSX)
@@ -24550,6 +24558,7 @@ static struct rs6000_opt_mask const rs6000_opt_masks[] =
   { "power11",			OPTION_MASK_POWER11,		false, false },
   { "hard-dfp",			OPTION_MASK_DFP,		false, true  },
   { "htm",			OPTION_MASK_HTM,		false, true  },
+  { "ieee16",			OPTION_MASK_IEEE16,		false, true  },
   { "isel",			OPTION_MASK_ISEL,		false, true  },
   { "mfcrf",			OPTION_MASK_MFCRF,		false, true  },
   { "mfpgpr",			0,				false, true  },
diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h
index 31c1d8f613a6..cffe2750ba9a 100644
--- a/gcc/config/rs6000/rs6000.h
+++ b/gcc/config/rs6000/rs6000.h
@@ -567,9 +567,6 @@ extern int rs6000_vector_align[];
    below.  */
 #define RS6000_FN_TARGET_INFO_HTM 1
 
-/* Support for IEEE 16-bit floating point.  */
-#define TARGET_IEEE16		TARGET_P9_VECTOR
-
 /* Whether the various reciprocal divide/square root estimate instructions
    exist, and whether we should automatically generate code for the instruction
    by default.  */
diff --git a/gcc/config/rs6000/rs6000.opt b/gcc/config/rs6000/rs6000.opt
index 5f81d3426a2c..779c13d233b9 100644
--- a/gcc/config/rs6000/rs6000.opt
+++ b/gcc/config/rs6000/rs6000.opt
@@ -642,6 +642,10 @@ mieee128-constant
 Target Var(TARGET_IEEE128_CONSTANT) Init(1) Save
 Generate (do not generate) code that uses the LXVKQ instruction.
 
+mieee16
+Target Undocumented Mask(IEEE16) Var(rs6000_isa_flags)
+Enable or disable _Float16 support.
+
 mieee16-gpr-args
 Target Undocumented Var(TARGET_IEEE16_GPR_ARGS) Init(1) Save
 Pass _Float16 in GPR registers.