[gcc(refs/users/meissner/heads/work221-float)] Add converts between 16-bit fp and integers

[Michael Meissner]

https://gcc.gnu.org/g:c9304e623e354a257b855ddac3a23dc5b79bb3d7

commit c9304e623e354a257b855ddac3a23dc5b79bb3d7
Author: Michael Meissner <meissner@linux.ibm.com>
Date:   Tue Sep 9 22:47:20 2025 -0400

    Add converts between 16-bit fp and integers
    
    2025-09-09  Michael Meissner  <meissner@linux.ibm.com>
    
    gcc/
    
            * config/rs6000/rs6000.md (float<GPR:mode>hf2): New insns.
            (floatuns<GPR:mode>hf2): Likewise.
            (fix_trunchf<mode>2): Likewise.
            (fixuns_trunchf<mode>): Likewise.

Diff:
---
 gcc/config/rs6000/rs6000.md | 50 +++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 50 insertions(+)

diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 5455f22315c7..7b6cc75b3e38 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -5899,6 +5899,56 @@
   DONE;
 })
 
+;; Convert integers to 16-bit floating point modes.
+(define_expand "float<GPR:mode>hf2"
+  [(set (match_operand:HF 0 "vsx_register_operand")
+	(float:HF
+	 (match_operand:GPR 1 "nonimmediate_operand")))]
+  ""
+{
+  rtx df_tmp = gen_reg_rtx (DFmode);
+  emit_insn (gen_float<mode>df2 (df_tmp, operands[1]));
+  emit_insn (gen_truncdfhf2 (operands[0], df_tmp));
+  DONE;
+})
+
+(define_expand "floatuns<GPR:mode>hf2"
+  [(set (match_operand:HF 0 "vsx_register_operand")
+	(unsigned_float:HF
+	 (match_operand:GPR 1 "nonimmediate_operand")))]
+  ""
+{
+  rtx df_tmp = gen_reg_rtx (DFmode);
+  emit_insn (gen_floatuns<mode>df2 (df_tmp, operands[1]));
+  emit_insn (gen_truncdfhf2 (operands[0], df_tmp));
+  DONE;
+})
+
+;; Convert 16-bit floating point modes to integers
+(define_expand "fix_trunchf<mode>2"
+  [(set (match_operand:GPR 0 "vsx_register_operand")
+	(fix:GPR
+	 (match_operand:HF 1 "vsx_register_operand")))]
+  ""
+{
+  rtx df_tmp = gen_reg_rtx (DFmode);
+  emit_insn (gen_extendhfdf2 (df_tmp, operands[1]));
+  emit_insn (gen_fix_truncdf<mode>2 (operands[0], df_tmp));
+  DONE;
+})
+
+(define_expand "fixuns_trunchf<mode>2"
+  [(set (match_operand:GPR 0 "vsx_register_operand")
+	(unsigned_fix:GPR
+	 (match_operand:HF 1 "vsx_register_operand")))]
+  ""
+{
+  rtx df_tmp = gen_reg_rtx (DFmode);
+  emit_insn (gen_extendhfdf2 (df_tmp, operands[1]));
+  emit_insn (gen_fixuns_truncdf<GPR:mode>2 (operands[0], df_tmp));
+  DONE;
+})
+
 
 ;; Conversions to and from floating-point.