[gcc(refs/users/meissner/heads/work221-float)] Add converts between 16-bit fp and integers

[Michael Meissner]

https://gcc.gnu.org/g:960b98674a37b00859e0f2588e2bc978349fe54c

commit 960b98674a37b00859e0f2588e2bc978349fe54c
Author: Michael Meissner <meissner@linux.ibm.com>
Date:   Tue Sep 9 20:32:06 2025 -0400

    Add converts between 16-bit fp and integers
    
    2025-09-09  Michael Meissner  <meissner@linux.ibm.com>
    
    gcc/
    
            * config/rs6000/rs6000.md (extendbf<mode>2): Add dummy define_expand.
            (trunc<mode>bf2): Likewise.
            (extend<CONVERT_FP16:mode><FP16:mode>2): Convert from just HFmode to
            both HFmode and BFmode.
            (trunc<CONVERT_FP16:mode><FP16:mode>2): Likewise.
            (float<FP16:mode><GPR:mode>2): New insns.
            (floatuns<GPR:mode><FP16:mode>2): Likewise.
            (fix_trunc<FP16:mode><GPR:mode>2): Likewise.
            (fixuns_trunc<FP16:mode><GPR:mode>2"): Likewise.

Diff:
---
 gcc/config/rs6000/rs6000.md | 82 +++++++++++++++++++++++++++++++++++++++++----
 1 file changed, 75 insertions(+), 7 deletions(-)

diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index c6b6d7e9ad54..57e4a05be714 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -5877,12 +5877,30 @@
   "xscvdphp %x0,%1"
   [(set_attr "type" "fpsimple")])
 
+(define_expand "extendbf<mode>2"
+  [(set (match_operand:SFDF 0 "vsx_register_operand")
+	(float_extend:SFDF
+	 (match_operand:BF 1 "vsx_register_operand")))]
+  "TARGET_BFLOAT16"
+{
+  /* TBD -- if invokved, this will get an insn not found errors.  */
+})
+
+(define_expand "trunc<mode>bf2"
+  [(set (match_operand:BF 0 "vsx_register_operand")
+	(float_truncate:BF
+	 (match_operand:SFDF 1 "vsx_register_operand")))]
+  "TARGET_BFLOAT16"
+{
+  /* TBD -- if invokved, this will get an insn not found errors.  */
+})
+
 ;; Use DFmode to convert to/from HFmode for floating point types other
 ;; than SF/DFmode.
-(define_expand "extendhf<mode>2"
-  [(set (match_operand:CONVERT_FP16 0 "vsx_register_operand" "=wa")
+(define_expand "extend<CONVERT_FP16:mode><FP16:mode>2"
+  [(set (match_operand:CONVERT_FP16 0 "vsx_register_operand")
 	(float_extend:CONVERT_FP16
-	 (match_operand:HF 1 "vsx_register_operand" "wa")))]
+	 (match_operand:FP16 1 "vsx_register_operand")))]
   "TARGET_IEEE16"
 {
   rtx df_tmp = gen_reg_rtx (DFmode);
@@ -5891,10 +5909,10 @@
   DONE;
 })
 
-(define_expand "trunc<mode>hf2"
-  [(set (match_operand:HF 0 "vsx_register_operand" "=wa")
-	(float_truncate:HF
-	 (match_operand:CONVERT_FP16 1 "vsx_register_operand" "wa")))]
+(define_expand "trunc<CONVERT_FP16:mode><FP16:mode>2"
+  [(set (match_operand:FP16 0 "vsx_register_operand")
+	(float_truncate:FP16
+	 (match_operand:CONVERT_FP16 1 "vsx_register_operand")))]
   "TARGET_IEEE16"
 {
   rtx df_tmp = gen_reg_rtx (DFmode);
@@ -5903,6 +5921,56 @@
   DONE;
 })
 
+;; Convert integers to 16-bit floating point modes.
+(define_expand "float<FP16:mode><GPR:mode>2"
+  [(set (match_operand:FP16 0 "vsx_register_operand")
+	(float:FP16
+	 (match_operand:GPR 1 "nonimmediate_operand")))]
+  ""
+{
+  rtx df_tmp = gen_reg_rtx (DFmode);
+  emit_insn (gen_float<GPR:mode>df2 (df_tmp, operands[1]));
+  emit_insn (gen_truncdf<FP16:mode>2 (operands[0], df_tmp));
+  DONE;
+})
+
+(define_expand "floatuns<GPR:mode><FP16:mode>2"
+  [(set (match_operand:FP16 0 "vsx_register_operand")
+	(unsigned_float:FP16
+	 (match_operand:GPR 1 "nonimmediate_operand")))]
+  ""
+{
+  rtx df_tmp = gen_reg_rtx (DFmode);
+  emit_insn (gen_floatuns<GPR:mode>df2 (df_tmp, operands[1]));
+  emit_insn (gen_truncdf<FP16:mode>2 (operands[0], df_tmp));
+  DONE;
+})
+
+;; Convert 16-bit floating point modes to integers
+(define_expand "fix_trunc<FP16:mode><GPR:mode>2"
+  [(set (match_operand:GPR 0 "vsx_register_operand")
+	(fix:GPR
+	 (match_operand:FP16 1 "vsx_register_operand")))]
+  ""
+{
+  rtx df_tmp = gen_reg_rtx (DFmode);
+  emit_insn (gen_extend<FP16:mode>df2 (df_tmp, operands[1]));
+  emit_insn (gen_fix_truncdf<GPR:mode>2 (operands[0], df_tmp));
+  DONE;
+})
+
+(define_expand "fixuns_trunc<FP16:mode><GPR:mode>2"
+  [(set (match_operand:GPR 0 "vsx_register_operand")
+	(unsigned_fix:GPR
+	 (match_operand:FP16 1 "vsx_register_operand")))]
+  ""
+{
+  rtx df_tmp = gen_reg_rtx (DFmode);
+  emit_insn (gen_extend<FP16:mode>df2 (df_tmp, operands[1]));
+  emit_insn (gen_fixuns_truncdf<GPR:mode>2 (operands[0], df_tmp));
+  DONE;
+})
+
 
 ;; Conversions to and from floating-point.