[gcc(refs/users/meissner/heads/work221-float)] Update conversions between _Float16 and various floating point types.

[Michael Meissner]

https://gcc.gnu.org/g:fde5b8c4c9fb16fb9aab1c9aff6e2beab61e24a3

commit fde5b8c4c9fb16fb9aab1c9aff6e2beab61e24a3
Author: Michael Meissner <meissner@linux.ibm.com>
Date:   Mon Sep 8 23:30:04 2025 -0400

    Update conversions between _Float16 and various floating point types.
    
    2025-09-08  Michael Meissner  <meissner@linux.ibm.com>
    
    gcc/
    
            * config/rs6000/rs6000.md (HF_CONVERT): New mode iterator.
            (extendhf<mode>2): Move from vsx.md, add conversion to/from decimal
            types.
            (trunc<mode>2): Likewise.
            * config/rs6000/vsx.md (extendhf<mode>2): Move to vsx.md.
            (trunc<mode>hf2): Likewise.

Diff:
---
 gcc/config/rs6000/rs6000.md | 49 +++++++++++++++++++++++++++++++++++++
 gcc/config/rs6000/vsx.md    | 59 ---------------------------------------------
 2 files changed, 49 insertions(+), 59 deletions(-)

diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 7ba2088884d5..a81758e62a02 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -858,6 +858,10 @@
 				     (SF "TARGET_P8_VECTOR")
 				     (DI "TARGET_POWERPC64")])
 
+;; Mode iterator for floating point modes other than SF/DFmode that we
+;; convert to/from _Float16 (HFmode) via DFmode.
+(define_mode_iterator HF_CONVERT [TF KF IF SD DD TD])
+
 (include "darwin.md")
 
 ;; Start with fixed-point load and store insns.  Here we put only the more
@@ -5850,6 +5854,51 @@
   "xxsel %x0,%x4,%x3,%x1"
   [(set_attr "type" "vecmove")])
 
+
+;; Convert IEEE 16-bit floating point to/from other floating point modes.
+
+(define_insn "extendhf<mode>2"
+  [(set (match_operand:SFDF 0 "vsx_register_operand" "=wa")
+	(float_extend:SFDF
+	 (match_operand:HF 1 "vsx_register_operand" "wa")))]
+  "TARGET_IEEE16"
+  "xscvhpdp %x0,%x1"
+  [(set_attr "type" "fpsimple")])
+
+(define_insn "trunc<mode>hf2"
+  [(set (match_operand:HF 0 "vsx_register_operand" "=wa")
+	(float_truncate:HF
+	 (match_operand:SFDF 1 "vsx_register_operand" "wa")))]
+  "TARGET_IEEE16"
+  "xscvdphp %x0,%1"
+  [(set_attr "type" "fpsimple")])
+
+;; Use DFmode to convert to/from HFmode for floating point types other
+;; than SF/DFmode.
+(define_expand "extendhf<mode>2"
+  [(set (match_operand:HF_CONVERT 0 "vsx_register_operand" "=wa")
+	(float_extend:HF_CONVERT
+	 (match_operand:HF 1 "vsx_register_operand" "wa")))]
+  "TARGET_IEEE16"
+{
+  rtx df_tmp = gen_reg_rtx (DFmode);
+  convert_move (df_tmp, operands[1], 0);
+  convert_move (operands[0], df_tmp, 0);
+  DONE;
+})
+
+(define_expand "trunc<mode>hf2"
+  [(set (match_operand:HF 0 "vsx_register_operand" "=wa")
+	(float_truncate:HF
+	 (match_operand:HF_CONVERT 1 "vsx_register_operand" "wa")))]
+  "TARGET_IEEE16"
+{
+  rtx df_tmp = gen_reg_rtx (DFmode);
+  convert_move (df_tmp, operands[1], 0);
+  convert_move (operands[0], df_tmp, 0);
+  DONE;
+})
+
 
 ;; Conversions to and from floating-point.
 
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index 3e429bdb1765..09b4d53813ba 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -3155,65 +3155,6 @@
   "xvrdpiz %x0,%x1"
   [(set_attr "type" "vecdouble")])
 
-
-;; Convert IEEE 16-bit floating point to/from binary floating point modes.
-
-(define_insn "extendhf<mode>2"
-  [(set (match_operand:SFDF 0 "vsx_register_operand" "=wa")
-	(float_extend:SFDF
-	 (match_operand:HF 1 "vsx_register_operand" "wa")))]
-  "TARGET_IEEE16"
-  "xscvhpdp %x0,%x1"
-  [(set_attr "type" "fpsimple")])
-
-(define_insn_and_split "extendhf<mode>2"
-  [(set (match_operand:FLOAT128 0 "vsx_register_operand" "=wa")
-	(float_extend:FLOAT128
-	 (match_operand:HF 1 "vsx_register_operand" "wa")))
-   (clobber (match_scratch:DF 2 "=wa"))]
-  "TARGET_IEEE16
-   && (FLOAT128_IBM_P (<MODE>mode) || FLOAT128_IEEE_P (<MODE>mode))"
-  "#"
-  "&& 1"
-  [(set (match_dup 2)
-	(float_extend:DF (match_dup 1)))
-   (set (match_dup 0)
-	(float_extend:FLOAT128 (match_dup 2)))]
-{
-  if (GET_CODE (operands[2]) == SCRATCH)
-    operands[2] = gen_reg_rtx (DFmode);
-}
-  [(set_attr "type" "fpsimple")
-   (set_attr "length" "8")])
-
-(define_insn "trunc<mode>hf2"
-  [(set (match_operand:HF 0 "vsx_register_operand" "=wa")
-	(float_truncate:HF
-	 (match_operand:SFDF 1 "vsx_register_operand" "wa")))]
-  "TARGET_IEEE16"
-  "xscvdphp %x0,%1"
-  [(set_attr "type" "fpsimple")])
-
-(define_insn_and_split "trunc<mode>hf2"
-  [(set (match_operand:HF 0 "vsx_register_operand" "=wa")
-	(float_truncate:HF
-	 (match_operand:FLOAT128 1 "vsx_register_operand" "wa")))
-   (clobber (match_scratch:DF 2 "=wa"))]
-  "TARGET_IEEE16
-   && (FLOAT128_IBM_P (<MODE>mode) || FLOAT128_IEEE_P (<MODE>mode))"
-  "#"
-  "&& 1"
-  [(set (match_dup 2)
-	(float_truncate:DF (match_dup 1)))
-   (set (match_dup 0)
-	(float_truncate:HF (match_dup 2)))]
-{
-  if (GET_CODE (operands[2]) == SCRATCH)
-    operands[2] = gen_reg_rtx (DFmode);
-}
-  [(set_attr "type" "fpsimple")
-   (set_attr "length" "8")])
-
 
 ;; Permute operations