[gcc(refs/users/meissner/heads/work221-sha)] PR target/117251: Improve vector nand to vector nand fusion

[Michael Meissner]

https://gcc.gnu.org/g:2f85422483914e5c6c0e5faf748c5a15adf5c500

commit 2f85422483914e5c6c0e5faf748c5a15adf5c500
Author: Michael Meissner <meissner@linux.ibm.com>
Date:   Mon Sep 8 15:44:31 2025 -0400

    PR target/117251: Improve vector nand to vector nand fusion
    
    See the following post for a complete explanation of what the patches
    for PR target/117251:
    
     * https://gcc.gnu.org/pipermail/gcc-patches/2025-June/686474.html
    
    This is patch #37 of 45 to generate the 'XXEVAL' instruction on power10
    and power11 instead of using the Altivec 'VNAND' instruction feeding
    into 'VNAND'.  The 'XXEVAL' instruction can use all 64 vector
    registers, instead of the 32 registers that traditional Altivec vector
    instructions use.  By allowing all of the vector registers to be used,
    it reduces the amount of spilling that a large benchmark generated.
    
    Currently the following code:
    
            vector int a, b, c, d;
            a = ~ ((~ (c & d)) & b);
    
    Generates:
    
            vnand  t,c,d
            vnand  a,t,b
    
    Now in addition with this patch, if the arguments or result is
    allocated to a traditional FPR register, the GCC compiler will now
    generate the following code instead of adding vector move instructions:
    
            xxeval a,b,c,241
    
    Since fusion using 2 Altivec instructions is slightly faster than using
    the 'XXEVAL' instruction we prefer to generate the Altivec instructions
    if we can.  In addition, because 'XXEVAL' is a prefixed instruction, it
    possibly might generate an extra NOP instruction to align the 'XXEVAL'
    instruction.
    
    I have tested these patches on both big endian and little endian
    PowerPC servers, with no regressions.  Can I check these patchs into
    the trunk?
    
    2025-09-08  Michael Meissner  <meissner@linux.ibm.com>
    
    gcc/
    
            PR target/117251
            * config/rs6000/fusion.md: Regenerate.
            * config/rs6000/genfusion.pl (gen_logical_addsubf): Add support
            to generate vector nand => nand fusion if XXEVAL is supported.

Diff:
---
 gcc/config/rs6000/fusion.md    | 15 +++++++++------
 gcc/config/rs6000/genfusion.pl |  1 +
 2 files changed, 10 insertions(+), 6 deletions(-)

diff --git a/gcc/config/rs6000/fusion.md b/gcc/config/rs6000/fusion.md
index ba3a5a52b990..241b8a494fb1 100644
--- a/gcc/config/rs6000/fusion.md
+++ b/gcc/config/rs6000/fusion.md
@@ -2390,20 +2390,23 @@
 ;; logical-logical fusion pattern generated by gen_logical_addsubf
 ;; vector vnand -> vnand
 (define_insn "*fuse_vnand_vnand"
-  [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v")
-        (ior:VM (not:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v"))
-                          (not:VM (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))))
-                 (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))))
-   (clobber (match_scratch:VM 4 "=X,X,X,&v"))]
+  [(set (match_operand:VM 3 "vector_fusion_operand" "=&0,&1,&v,wa,v")
+        (ior:VM (not:VM (ior:VM (not:VM (match_operand:VM 0 "vector_fusion_operand" "v,v,v,wa,v"))
+                          (not:VM (match_operand:VM 1 "vector_fusion_operand" "v,v,v,wa,v"))))
+                 (not:VM (match_operand:VM 2 "vector_fusion_operand" "v,v,v,wa,v"))))
+   (clobber (match_scratch:VM 4 "=X,X,X,X,&v"))]
   "(TARGET_P10_FUSION)"
   "@
    vnand %3,%1,%0\;vnand %3,%3,%2
    vnand %3,%1,%0\;vnand %3,%3,%2
    vnand %3,%1,%0\;vnand %3,%3,%2
+   xxeval %x3,%x2,%x1,%x0,241
    vnand %4,%1,%0\;vnand %3,%4,%2"
   [(set_attr "type" "fused_vector")
    (set_attr "cost" "6")
-   (set_attr "length" "8")])
+   (set_attr "length" "8")
+   (set_attr "prefixed" "*,*,*,yes,*")
+   (set_attr "isa" "*,*,*,xxeval,*")])
 
 ;; logical-logical fusion pattern generated by gen_logical_addsubf
 ;; vector vnor -> vnand
diff --git a/gcc/config/rs6000/genfusion.pl b/gcc/config/rs6000/genfusion.pl
index 54699d199fc5..728a447c65a9 100755
--- a/gcc/config/rs6000/genfusion.pl
+++ b/gcc/config/rs6000/genfusion.pl
@@ -251,6 +251,7 @@ sub gen_logical_addsubf
       "vand_vnor"   => 224,
       "vnand_vxor"  => 225,
       "vnand_vor"   => 239,
+      "vnand_vnand" => 241,
     );
 
     KIND: foreach $kind ('scalar','vector') {