[gcc(refs/users/meissner/heads/work221-sha)] PR target/117251: Improve vector eqv to vector or fusion

[Michael Meissner]

https://gcc.gnu.org/g:7e7416fd02912c26c085b47bb4240be4d59ca959

commit 7e7416fd02912c26c085b47bb4240be4d59ca959
Author: Michael Meissner <meissner@linux.ibm.com>
Date:   Mon Sep 8 15:36:35 2025 -0400

    PR target/117251: Improve vector eqv to vector or fusion
    
    See the following post for a complete explanation of what the patches
    for PR target/117251:
    
     * https://gcc.gnu.org/pipermail/gcc-patches/2025-June/686474.html
    
    This is patch #29 of 45 to generate the 'XXEVAL' instruction on power10
    and power11 instead of using the Altivec 'VEQV' instruction feeding
    into 'VOR'.  The 'XXEVAL' instruction can use all 64 vector registers,
    instead of the 32 registers that traditional Altivec vector
    instructions use.  By allowing all of the vector registers to be used,
    it reduces the amount of spilling that a large benchmark generated.
    
    Currently the following code:
    
            vector int a, b, c, d;
            a = (~ (c ^ d)) | b;
    
    Generates:
    
            veqv   t,c,d
            vor    a,t,b
    
    Now in addition with this patch, if the arguments or result is
    allocated to a traditional FPR register, the GCC compiler will now
    generate the following code instead of adding vector move instructions:
    
            xxeval a,b,c,159
    
    Since fusion using 2 Altivec instructions is slightly faster than using
    the 'XXEVAL' instruction we prefer to generate the Altivec instructions
    if we can.  In addition, because 'XXEVAL' is a prefixed instruction, it
    possibly might generate an extra NOP instruction to align the 'XXEVAL'
    instruction.
    
    I have tested these patches on both big endian and little endian
    PowerPC servers, with no regressions.  Can I check these patchs into
    the trunk?
    
    2025-09-08  Michael Meissner  <meissner@linux.ibm.com>
    
    gcc/
    
            PR target/117251
            * config/rs6000/fusion.md: Regenerate.
            * config/rs6000/genfusion.pl (gen_logical_addsubf): Add support
            to generate vector eqv => or fusion if XXEVAL is supported.

Diff:
---
 gcc/config/rs6000/fusion.md    | 15 +++++++++------
 gcc/config/rs6000/genfusion.pl |  1 +
 2 files changed, 10 insertions(+), 6 deletions(-)

diff --git a/gcc/config/rs6000/fusion.md b/gcc/config/rs6000/fusion.md
index bb62ae26445a..cb1ad8b4c0cc 100644
--- a/gcc/config/rs6000/fusion.md
+++ b/gcc/config/rs6000/fusion.md
@@ -2681,20 +2681,23 @@
 ;; logical-logical fusion pattern generated by gen_logical_addsubf
 ;; vector veqv -> vor
 (define_insn "*fuse_veqv_vor"
-  [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v")
-        (ior:VM (not:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")
-                          (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")))
-                 (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))
-   (clobber (match_scratch:VM 4 "=X,X,X,&v"))]
+  [(set (match_operand:VM 3 "vector_fusion_operand" "=&0,&1,&v,wa,v")
+        (ior:VM (not:VM (xor:VM (match_operand:VM 0 "vector_fusion_operand" "v,v,v,wa,v")
+                          (match_operand:VM 1 "vector_fusion_operand" "v,v,v,wa,v")))
+                 (match_operand:VM 2 "vector_fusion_operand" "v,v,v,wa,v")))
+   (clobber (match_scratch:VM 4 "=X,X,X,X,&v"))]
   "(TARGET_P10_FUSION)"
   "@
    veqv %3,%1,%0\;vor %3,%3,%2
    veqv %3,%1,%0\;vor %3,%3,%2
    veqv %3,%1,%0\;vor %3,%3,%2
+   xxeval %x3,%x2,%x1,%x0,159
    veqv %4,%1,%0\;vor %3,%4,%2"
   [(set_attr "type" "fused_vector")
    (set_attr "cost" "6")
-   (set_attr "length" "8")])
+   (set_attr "length" "8")
+   (set_attr "prefixed" "*,*,*,yes,*")
+   (set_attr "isa" "*,*,*,xxeval,*")])
 
 ;; logical-logical fusion pattern generated by gen_logical_addsubf
 ;; vector vnand -> vor
diff --git a/gcc/config/rs6000/genfusion.pl b/gcc/config/rs6000/genfusion.pl
index 726e29c798bc..9400aed267a6 100755
--- a/gcc/config/rs6000/genfusion.pl
+++ b/gcc/config/rs6000/genfusion.pl
@@ -243,6 +243,7 @@ sub gen_logical_addsubf
       "vnor_vor"    => 143,
       "vxor_vnor"   => 144,
       "veqv_vxor"   => 150,
+      "veqv_vor"    => 159,
     );
 
     KIND: foreach $kind ('scalar','vector') {