[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [RISC-V][PR target/121113] Handle HFmode in various insn reservations

[Jeff Law]

https://gcc.gnu.org/g:24a34c6140d99ef0fe383d0c535213ad3eac5eed

commit 24a34c6140d99ef0fe383d0c535213ad3eac5eed
Author: Jeff Law <jlaw@ventanamicro.com>
Date:   Tue Aug 12 20:29:50 2025 -0600

    [RISC-V][PR target/121113] Handle HFmode in various insn reservations
    
    So this is a minor bug in a few DFA descriptions such as the Xiangshan and a
    couple of the SiFive descriptions.
    
    While Xiangshan covers every insn type, some of the reservations check the mode
    of the operation.   Concretely the fdiv/fsqrt unit reservations vary based on
    the mode.  They handled DF/SF, but not HF (the relevant iterators don't include
    BF).
    
    This patch just adds HF support with the same characteristics as SF. Those who
    know these designs better could perhaps improve the reservation, but this at
    least keeps us from aborting.
    
    I did check the other published DFAs for mode dependent reservations. That's
    show I found the p400/p600 issue.
    
    Tested in my tester, waiting for CI to render its verdict before pushing.
    
            PR target/121113
    gcc/
            * config/riscv/sifive-p400.md: Handle HFmode for fdiv/fsqrt.
            * config/riscv/sifive-p600.md: Likewise.
            * config/riscv/xiangshan.md: Likewise.
    
    gcc/testsuite/
            * gcc.target/riscv/pr121113.c: New test.
    
    (cherry picked from commit 2e2589616ac18a0473e4f1e05dec6903d8131740)

Diff:
---
 gcc/config/riscv/sifive-p400.md           | 5 ++++-
 gcc/config/riscv/sifive-p600.md           | 5 ++++-
 gcc/config/riscv/xiangshan.md             | 4 ++--
 gcc/testsuite/gcc.target/riscv/pr121113.c | 5 +++++
 4 files changed, 15 insertions(+), 4 deletions(-)

diff --git a/gcc/config/riscv/sifive-p400.md b/gcc/config/riscv/sifive-p400.md
index ed8b8ec9da7b..d6f6e2a3b6c0 100644
--- a/gcc/config/riscv/sifive-p400.md
+++ b/gcc/config/riscv/sifive-p400.md
@@ -153,10 +153,13 @@
        (eq_attr "type" "fmove,fcvt"))
   "p400_float_pipe,sifive_p400_fpu")
 
+;; We need something for HF so that we don't abort during
+;; scheduling if someone was to ask for p400 scheduling, but
+;; enable the various HF mode extensions.
 (define_insn_reservation "sifive_p400_fdiv_s" 18
   (and (eq_attr "tune" "sifive_p400")
        (eq_attr "type" "fdiv,fsqrt")
-       (eq_attr "mode" "SF"))
+       (eq_attr "mode" "HF,SF"))
   "sifive_p400_FM, sifive_p400_fdiv*5")
 
 (define_insn_reservation "sifive_p400_fdiv_d" 31
diff --git a/gcc/config/riscv/sifive-p600.md b/gcc/config/riscv/sifive-p600.md
index 240134976fa1..ff51149f9b70 100644
--- a/gcc/config/riscv/sifive-p600.md
+++ b/gcc/config/riscv/sifive-p600.md
@@ -157,10 +157,13 @@
        (eq_attr "type" "fmove,fcvt"))
   "float_pipe,sifive_p600_fpu")
 
+;; We need something for HF so that we don't abort during
+;; scheduling if someone was to ask for p600 scheduling, but
+;; enable the various HF mode extensions.
 (define_insn_reservation "sifive_p600_fdiv_s" 11
   (and (eq_attr "tune" "sifive_p600")
        (eq_attr "type" "fdiv,fsqrt")
-       (eq_attr "mode" "SF"))
+       (eq_attr "mode" "HF,SF"))
   "sifive_p600_FM, sifive_p600_fdiv*5")
 
 (define_insn_reservation "sifive_p600_fdiv_d" 19
diff --git a/gcc/config/riscv/xiangshan.md b/gcc/config/riscv/xiangshan.md
index 34b4a8f1f3fc..617914087815 100644
--- a/gcc/config/riscv/xiangshan.md
+++ b/gcc/config/riscv/xiangshan.md
@@ -144,13 +144,13 @@
 (define_insn_reservation "xiangshan_sfdiv" 11
   (and (eq_attr "tune" "xiangshan")
        (eq_attr "type" "fdiv")
-       (eq_attr "mode" "SF"))
+       (eq_attr "mode" "HF,SF"))
   "xs_fmisc_rs")
 
 (define_insn_reservation "xiangshan_sfsqrt" 17
   (and (eq_attr "tune" "xiangshan")
        (eq_attr "type" "fsqrt")
-       (eq_attr "mode" "SF"))
+       (eq_attr "mode" "HF,SF"))
   "xs_fmisc_rs")
 
 (define_insn_reservation "xiangshan_dfdiv" 21
diff --git a/gcc/testsuite/gcc.target/riscv/pr121113.c b/gcc/testsuite/gcc.target/riscv/pr121113.c
new file mode 100644
index 000000000000..091fa828ef32
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/pr121113.c
@@ -0,0 +1,5 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-std=c23 -mcpu=xiangshan-kunminghu" } */
+
+_Float16 f, g;
+void foo() { f /= g; }