[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Fix another vf FP16 combine run test failures

[Jeff Law]

https://gcc.gnu.org/g:b8b9747dc0a814f12af8a0688d609fede8129173

commit b8b9747dc0a814f12af8a0688d609fede8129173
Author: Pan Li <pan2.li@intel.com>
Date:   Fri Jul 25 22:11:13 2025 +0800

    RISC-V: Fix another vf FP16 combine run test failures
    
    Like Robin's fix for vf combine f16.c run tests, there is still
    another failures similar.  This patch would like to fix it as
    previous.
    
    will commit it directly if the CI agrees.
    
    gcc/testsuite/ChangeLog:
    
            * gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwnmacc-run-1-f16.c:
            Add zvfh requirements and options.
            * gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwnmsac-run-1-f16.c:
            Ditto.
    
    Signed-off-by: Pan Li <pan2.li@intel.com>
    (cherry picked from commit 62f8a246bbaa1a1f5aedba4c84f7fe4c7eca799f)

Diff:
---
 .../gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwnmacc-run-1-f16.c      | 6 +++++-
 .../gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwnmsac-run-1-f16.c      | 6 +++++-
 2 files changed, 10 insertions(+), 2 deletions(-)

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwnmacc-run-1-f16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwnmacc-run-1-f16.c
index 6be7d720603d..ddf49d5b2f23 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwnmacc-run-1-f16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwnmacc-run-1-f16.c
@@ -1,5 +1,9 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "-march=rv64gcv_zvfh --param=fpr2vr-cost=0" } */
+/* { dg-require-effective-target riscv_v_ok } */
+/* { dg-require-effective-target riscv_zvfh } */
+/* { dg-add-options "riscv_v" } */
+/* { dg-add-options "riscv_zvfh" } */
+/* { dg-additional-options "--param=fpr2vr-cost=0" } */
 
 #include "vf_mulop.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwnmsac-run-1-f16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwnmsac-run-1-f16.c
index dd28234b6e0e..a8749915569a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwnmsac-run-1-f16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwnmsac-run-1-f16.c
@@ -1,5 +1,9 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "-march=rv64gcv_zvfh --param=fpr2vr-cost=0" } */
+/* { dg-require-effective-target riscv_v_ok } */
+/* { dg-require-effective-target riscv_zvfh } */
+/* { dg-add-options "riscv_v" } */
+/* { dg-add-options "riscv_zvfh" } */
+/* { dg-additional-options "--param=fpr2vr-cost=0" } */
 
 #include "vf_mulop.h"