[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] riscv: testsuite: Fix misalignment check.

[Jeff Law]

https://gcc.gnu.org/g:2f5fe116c8483f3c33ea00fffca3537189c1df05

commit 2f5fe116c8483f3c33ea00fffca3537189c1df05
Author: Robin Dapp <rdapp@ventanamicro.com>
Date:   Wed Jul 2 10:28:57 2025 +0200

    riscv: testsuite: Fix misalignment check.
    
    This fixes a thinko in the misalignment check.  If we want to check for
    vector misalignment support we need to load 16-byte elements, not
    8-byte elements that will never be misaligned.
    
    gcc/testsuite/ChangeLog:
    
            * lib/target-supports.exp: Fix misalignment check.
    
    (cherry picked from commit 45665da440d07e5f559a7638e40e40099acbe78a)

Diff:
---
 gcc/testsuite/lib/target-supports.exp | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp
index 93f2bb17c57e..0e9de5da5bac 100644
--- a/gcc/testsuite/lib/target-supports.exp
+++ b/gcc/testsuite/lib/target-supports.exp
@@ -2354,7 +2354,7 @@ proc check_effective_target_riscv_v_misalign_ok { } {
 		= {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15};
 	      asm ("vsetivli zero,7,e8,m1,ta,ma");
 	      asm ("addi a7,%0,1" : : "r" (a) : "a7" );
-	      asm ("vle8.v v8,0(a7)" : : : "v8");
+	      asm ("vle16.v v8,0(a7)" : : : "v8");
 	      return 0; } } "-march=${gcc_march}"] } {
 	return 1
     }