[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Reconcile the existing test for vrem.vx combine

[Jeff Law]

https://gcc.gnu.org/g:d573b748d5ed408622c629e8a6827d0cdf32caae

commit d573b748d5ed408622c629e8a6827d0cdf32caae
Author: Pan Li <pan2.li@intel.com>
Date:   Sun Jun 8 16:50:52 2025 +0800

    RISC-V: Reconcile the existing test for vrem.vx combine
    
    Some existing vrem related test need some adjust for the
    asm check due to cost model.
    
    gcc/testsuite/ChangeLog:
    
            * gcc.target/riscv/rvv/autovec/binop/vrem-rv32gcv.c: Adjust the
            asm check for vrem.
            * gcc.target/riscv/rvv/autovec/binop/vrem-rv64gcv.c: Ditto.
    
    Signed-off-by: Pan Li <pan2.li@intel.com>
    (cherry picked from commit 4df4acf002cc3672478edb43f374cef3ffbd1f54)

Diff:
---
 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrem-rv32gcv.c | 4 ++--
 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrem-rv64gcv.c | 4 ++--
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrem-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrem-rv32gcv.c
index a87a6c70df1f..ad918a9b800a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrem-rv32gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrem-rv32gcv.c
@@ -2,8 +2,8 @@
 
 #include "vrem-template.h"
 
-/* { dg-final { scan-assembler-times {\tvrem\.vv} 5 } } */
-/* { dg-final { scan-assembler-times {\tvrem\.vx} 3 } } */
+/* { dg-final { scan-assembler-times {\tvrem\.vv} 8 } } */
+/* { dg-final { scan-assembler-not {\tvrem\.vx} } } */
 /* { dg-final { scan-assembler-times {\tvremu\.vv} 5 } } */
 /* { dg-final { scan-assembler-times {\tvremu\.vx} 3 } } */
 /* { dg-final { scan-tree-dump-times "\.COND_LEN_MOD" 16 "optimized" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrem-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrem-rv64gcv.c
index 938169574aac..4e28f99e2886 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrem-rv64gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrem-rv64gcv.c
@@ -3,8 +3,8 @@
 
 #include "vrem-template.h"
 
-/* { dg-final { scan-assembler-times {\tvrem\.vv} 4 } } */
-/* { dg-final { scan-assembler-times {\tvrem\.vx} 4 } } */
+/* { dg-final { scan-assembler-times {\tvrem\.vv} 8 } } */
+/* { dg-final { scan-assembler-not {\tvrem\.vx} } } */
 /* { dg-final { scan-assembler-times {\tvremu\.vv} 4 } } */
 /* { dg-final { scan-assembler-times {\tvremu\.vx} 4 } } */
 /* { dg-final { scan-tree-dump-times "\.COND_LEN_MOD" 16 "optimized" } } */