[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Support Sstvala extension.

[Jeff Law]

https://gcc.gnu.org/g:ae427a97aeff70fb430ba7593566b2f138a2af8d

commit ae427a97aeff70fb430ba7593566b2f138a2af8d
Author: Jiawei <jiawei@iscas.ac.cn>
Date:   Thu Jun 5 13:46:39 2025 +0800

    RISC-V: Support Sstvala extension.
    
    Support the Sstvala extension, which provides all needed values in
    Supervisor Trap Value register (stval).
    
    gcc/ChangeLog:
    
            * config/riscv/riscv-ext.def: New extension definition.
            * config/riscv/riscv-ext.opt: New extension mask.
            * doc/riscv-ext.texi: Document the new extension.
    
    gcc/testsuite/ChangeLog:
    
            * gcc.target/riscv/arch-sstvala.c: New test.
    
    Signed-off-by: Jiawei <jiawei@iscas.ac.cn>
    (cherry picked from commit 37f0e8395c279b5eb969bf678e5c571c1f3d3b32)

Diff:
---
 gcc/config/riscv/riscv-ext.def                | 13 +++++++++++++
 gcc/config/riscv/riscv-ext.opt                |  2 ++
 gcc/doc/riscv-ext.texi                        |  4 ++++
 gcc/testsuite/gcc.target/riscv/arch-sstvala.c |  5 +++++
 4 files changed, 24 insertions(+)

diff --git a/gcc/config/riscv/riscv-ext.def b/gcc/config/riscv/riscv-ext.def
index dab8cb8d69d6..69ff712d8e57 100644
--- a/gcc/config/riscv/riscv-ext.def
+++ b/gcc/config/riscv/riscv-ext.def
@@ -1909,6 +1909,19 @@ DEFINE_RISCV_EXT(
   /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED,
   /* EXTRA_EXTENSION_FLAGS */ 0)
 
+DEFINE_RISCV_EXT(
+  /* NAME */ sstvala,
+  /* UPPERCASE_NAME */ SSTVALA,
+  /* FULL_NAME */ "Stval provides all needed values",
+  /* DESC */ "",
+  /* URL */ ,
+  /* DEP_EXTS */ ({"zicsr"}),
+  /* SUPPORTED_VERSIONS */ ({{1, 0}}),
+  /* FLAG_GROUP */ ss,
+  /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED,
+  /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED,
+  /* EXTRA_EXTENSION_FLAGS */ 0)
+
 DEFINE_RISCV_EXT(
   /* NAME */ ssstrict,
   /* UPPERCASE_NAME */ SSSTRICT,
diff --git a/gcc/config/riscv/riscv-ext.opt b/gcc/config/riscv/riscv-ext.opt
index ad9e1d68069c..115a1c5de8dc 100644
--- a/gcc/config/riscv/riscv-ext.opt
+++ b/gcc/config/riscv/riscv-ext.opt
@@ -371,6 +371,8 @@ Mask(SSSTATEEN) Var(riscv_ss_subext)
 
 Mask(SSTC) Var(riscv_ss_subext)
 
+Mask(SSTVALA) Var(riscv_ss_subext)
+
 Mask(SSSTRICT) Var(riscv_ss_subext)
 
 Mask(SSDBLTRP) Var(riscv_ss_subext)
diff --git a/gcc/doc/riscv-ext.texi b/gcc/doc/riscv-ext.texi
index 2b23366607d5..075cef2c7d8c 100644
--- a/gcc/doc/riscv-ext.texi
+++ b/gcc/doc/riscv-ext.texi
@@ -566,6 +566,10 @@
 @tab 1.0
 @tab Supervisor-mode timer interrupts extension
 
+@item sstvala
+@tab 1.0
+@tab Stval provides all needed values
+
 @item ssstrict
 @tab 1.0
 @tab ssstrict extension
diff --git a/gcc/testsuite/gcc.target/riscv/arch-sstvala.c b/gcc/testsuite/gcc.target/riscv/arch-sstvala.c
new file mode 100644
index 000000000000..21ea8a6360c0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/arch-sstvala.c
@@ -0,0 +1,5 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64i_sstvala -mabi=lp64" } */
+int foo()
+{
+}