[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add Shlcofideleg extension.

[Jeff Law]

https://gcc.gnu.org/g:c1b5a3b9562c1f34f0f90fc9b4660c1679f3c3df

commit c1b5a3b9562c1f34f0f90fc9b4660c1679f3c3df
Author: Jiawei <jiawei@iscas.ac.cn>
Date:   Tue May 27 14:37:03 2025 +0800

    RISC-V: Add Shlcofideleg extension.
    
    This patch add the RISC-V Shlcofideleg extension. It supports delegating
    LCOFI interrupts(the count-overflow interrupts) to VS-mode.[1]
    
    [1] https://riscv.github.io/riscv-isa-manual/snapshot/privileged
    
    gcc/ChangeLog:
    
            * config/riscv/riscv-ext.def: New extension defs.
            * config/riscv/riscv-ext.opt: Ditto.
            * doc/riscv-ext.texi: Ditto.
    
    gcc/testsuite/ChangeLog:
    
            * gcc.target/riscv/arch-shlocofideleg.c: New test.
    
    Signed-off-by: Jiawei <jiawei@iscas.ac.cn>
    (cherry picked from commit f8251b4fce20f030fb133de1cadb06f95f01656e)

Diff:
---
 gcc/config/riscv/riscv-ext.def                      | 13 +++++++++++++
 gcc/config/riscv/riscv-ext.opt                      |  2 ++
 gcc/doc/riscv-ext.texi                              |  4 ++++
 gcc/testsuite/gcc.target/riscv/arch-shlocofideleg.c |  5 +++++
 4 files changed, 24 insertions(+)

diff --git a/gcc/config/riscv/riscv-ext.def b/gcc/config/riscv/riscv-ext.def
index d0adc2b6569b..2d052c152068 100644
--- a/gcc/config/riscv/riscv-ext.def
+++ b/gcc/config/riscv/riscv-ext.def
@@ -1610,6 +1610,19 @@ DEFINE_RISCV_EXT(
   /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED,
   /* EXTRA_EXTENSION_FLAGS */ 0)
 
+DEFINE_RISCV_EXT(
+  /* NAME */ shlcofideleg,
+  /* UPPERCASE_NAME */ SHLCOFIDELEG,
+  /* FULL_NAME */ "Delegating LCOFI interrupts to VS-mode",
+  /* DESC */ "",
+  /* URL */ ,
+  /* DEP_EXTS */ ({"h"}),
+  /* SUPPORTED_VERSIONS */ ({{1, 0}}),
+  /* FLAG_GROUP */ sh,
+  /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED,
+  /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED,
+  /* EXTRA_EXTENSION_FLAGS */ 0)
+
 DEFINE_RISCV_EXT(
   /* NAME */ shtvala,
   /* UPPERCAE_NAME */ SHTVALA,
diff --git a/gcc/config/riscv/riscv-ext.opt b/gcc/config/riscv/riscv-ext.opt
index c0dcde652930..e0314430ffb1 100644
--- a/gcc/config/riscv/riscv-ext.opt
+++ b/gcc/config/riscv/riscv-ext.opt
@@ -325,6 +325,8 @@ Mask(SHCOUNTERENW) Var(riscv_sh_subext)
 
 Mask(SHGATPA) Var(riscv_sh_subext)
 
+Mask(SHLCOFIDELEG) Var(riscv_sh_subext)
+
 Mask(SHTVALA) Var(riscv_sh_subext)
 
 Mask(SHVSTVALA) Var(riscv_sh_subext)
diff --git a/gcc/doc/riscv-ext.texi b/gcc/doc/riscv-ext.texi
index e64c0d653a9f..e7e1f75cca6d 100644
--- a/gcc/doc/riscv-ext.texi
+++ b/gcc/doc/riscv-ext.texi
@@ -474,6 +474,10 @@
 @tab 1.0
 @tab SvNNx4 mode supported for all modes supported by satp
 
+@item shlcofideleg
+@tab 1.0
+@tab Delegating LCOFI interrupts to VS-mode
+
 @item shtvala
 @tab 1.0
 @tab The htval register provides all needed values
diff --git a/gcc/testsuite/gcc.target/riscv/arch-shlocofideleg.c b/gcc/testsuite/gcc.target/riscv/arch-shlocofideleg.c
new file mode 100644
index 000000000000..de9f9fc6e53b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/arch-shlocofideleg.c
@@ -0,0 +1,5 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64i_shlcofideleg -mabi=lp64" } */
+int foo()
+{
+}