[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add new operand constraint: cR

[Jeff Law]

https://gcc.gnu.org/g:94b41ed01f858cf424de65f7b5a7263609024e0c

commit 94b41ed01f858cf424de65f7b5a7263609024e0c
Author: Kito Cheng <kito.cheng@sifive.com>
Date:   Mon May 12 14:36:07 2025 +0800

    RISC-V: Add new operand constraint: cR
    
    This commit introduces a new operand constraint `cR` for the RISC-V
    architecture, which allows the use of an even-odd RVC general purpose register
    (x8-x15) in inline asm.
    
    Ref: https://github.com/riscv-non-isa/riscv-c-api-doc/pull/102
    
    gcc/ChangeLog:
    
            * config/riscv/constraints.md (cR): New constraint.
            * doc/md.texi (Machine Constraints::RISC-V): Document the new cR
            constraint.
    
    gcc/testsuite/ChangeLog:
    
            * gcc.target/riscv/constraint-cR-pair.c: New test case.
    
    (cherry picked from commit c9eb473fb9946f642506d24f4131d7c83855fd78)

Diff:
---
 gcc/config/riscv/constraints.md                     |  4 ++++
 gcc/doc/md.texi                                     |  3 +++
 gcc/testsuite/gcc.target/riscv/constraint-cR-pair.c | 13 +++++++++++++
 3 files changed, 20 insertions(+)

diff --git a/gcc/config/riscv/constraints.md b/gcc/config/riscv/constraints.md
index 18556a591411..58355cf03f2f 100644
--- a/gcc/config/riscv/constraints.md
+++ b/gcc/config/riscv/constraints.md
@@ -43,6 +43,10 @@
 (define_register_constraint "cf" "TARGET_HARD_FLOAT ? RVC_FP_REGS : (TARGET_ZFINX ? RVC_GR_REGS : NO_REGS)"
   "RVC floating-point registers (f8-f15), if available, reuse GPR as FPR when use zfinx.")
 
+(define_register_constraint "cR" "RVC_GR_REGS"
+  "Even-odd RVC general purpose register (x8-x15)."
+  "regno % 2 == 0")
+
 ;; General constraints
 
 (define_constraint "I"
diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi
index ae7a6017a25e..cdf99cb79798 100644
--- a/gcc/doc/md.texi
+++ b/gcc/doc/md.texi
@@ -3703,6 +3703,9 @@ RVC general purpose register (x8-x15).
 RVC floating-point registers (f8-f15), if available, reuse GPR as FPR when use
 zfinx.
 
+@item cR
+Even-odd RVC general purpose register pair.
+
 @item R
 Even-odd general purpose register pair.
 
diff --git a/gcc/testsuite/gcc.target/riscv/constraint-cR-pair.c b/gcc/testsuite/gcc.target/riscv/constraint-cR-pair.c
new file mode 100644
index 000000000000..479246b632a7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/constraint-cR-pair.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-flto" } { "" } } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+void foo(int a0, int a1, int a2, int a3, int a4, int a5, int a6, int a7, int m0, int m1) {
+/*
+** foo:
+**   ...
+**   addi\s*t0,\s*(a[024]|s0),\s*(a[024]|s0)
+**   ...
+*/
+    __asm__ volatile("addi t0, %0, %0" : : "cR" (m0) : "memory");
+}