[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add augmented hypervisor series extensions.
Jeff Law
law@gcc.gnu.org
Sat Sep 6 14:36:15 GMT 2025
https://gcc.gnu.org/g:5c9c74c067ae4dc9df9fb61a48b691dc893bba7e
commit 5c9c74c067ae4dc9df9fb61a48b691dc893bba7e
Author: Jiawei <jiawei@iscas.ac.cn>
Date: Tue May 13 15:23:39 2025 +0800
RISC-V: Add augmented hypervisor series extensions.
The augmented hypervisor series extensions 'sha'[1] is a new profile-defined
extension series that captures the full set of features that are mandated to
be supported along with the 'H' extension.
[1] https://github.com/riscv/riscv-profiles/blob/main/src/rva23-profile.adoc#rva23s64-profile
Version log: Update implements， fix testcase format.
gcc/ChangeLog:
* config/riscv/riscv-ext.def: New extension defs.
* config/riscv/riscv-ext.opt: Ditto.
* doc/riscv-ext.texi: Ditto.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/arch-55.c: New test.
(cherry picked from commit 0cbace3b142c087335e245245e97f6605a6cd1f7)
Diff:
---
gcc/config/riscv/riscv-ext.def | 91 ++++++++++++++++++++++++++++++++
gcc/config/riscv/riscv-ext.opt | 17 ++++++
gcc/doc/riscv-ext.texi | 28 ++++++++++
gcc/testsuite/gcc.target/riscv/arch-55.c | 9 ++++
4 files changed, 145 insertions(+)
diff --git a/gcc/config/riscv/riscv-ext.def b/gcc/config/riscv/riscv-ext.def
index 34742d912f83..97b576617add 100644
--- a/gcc/config/riscv/riscv-ext.def
+++ b/gcc/config/riscv/riscv-ext.def
@@ -1571,6 +1571,97 @@ DEFINE_RISCV_EXT(
/* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED,
/* EXTRA_EXTENSION_FLAGS */ 0)
+DEFINE_RISCV_EXT(
+ /* NAME */ sha,
+ /* UPPERCAE_NAME */ SHA,
+ /* FULL_NAME */ "The augmented hypervisor extension",
+ /* DESC */ "",
+ /* URL */ ,
+ /* DEP_EXTS */ ({"h", "shcounterenw", "shgatpa", "shtvala", "shvstvala", "shvstvecd", "shvsatpa", "ssstateen"}),
+ /* SUPPORTED_VERSIONS */ ({{1, 0}}),
+ /* FLAG_GROUP */ sh,
+ /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED,
+ /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED,
+ /* EXTRA_EXTENSION_FLAGS */ 0)
+
+DEFINE_RISCV_EXT(
+ /* NAME */ shcounterenw,
+ /* UPPERCAE_NAME */ SHCOUNTERENW,
+ /* FULL_NAME */ "Support writeable enables for any supported counter",
+ /* DESC */ "",
+ /* URL */ ,
+ /* DEP_EXTS */ ({"h", "zihpm"}),
+ /* SUPPORTED_VERSIONS */ ({{1, 0}}),
+ /* FLAG_GROUP */ sh,
+ /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED,
+ /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED,
+ /* EXTRA_EXTENSION_FLAGS */ 0)
+
+DEFINE_RISCV_EXT(
+ /* NAME */ shgatpa,
+ /* UPPERCAE_NAME */ SHGATPA,
+ /* FULL_NAME */ "SvNNx4 mode supported for all modes supported by satp",
+ /* DESC */ "",
+ /* URL */ ,
+ /* DEP_EXTS */ ({"h", "ssstateen"}),
+ /* SUPPORTED_VERSIONS */ ({{1, 0}}),
+ /* FLAG_GROUP */ sh,
+ /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED,
+ /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED,
+ /* EXTRA_EXTENSION_FLAGS */ 0)
+
+DEFINE_RISCV_EXT(
+ /* NAME */ shtvala,
+ /* UPPERCAE_NAME */ SHTVALA,
+ /* FULL_NAME */ "The htval register provides all needed values",
+ /* DESC */ "",
+ /* URL */ ,
+ /* DEP_EXTS */ ({"h"}),
+ /* SUPPORTED_VERSIONS */ ({{1, 0}}),
+ /* FLAG_GROUP */ sh,
+ /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED,
+ /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED,
+ /* EXTRA_EXTENSION_FLAGS */ 0)
+
+DEFINE_RISCV_EXT(
+ /* NAME */ shvstvala,
+ /* UPPERCAE_NAME */ SHVSTVALA,
+ /* FULL_NAME */ "The vstval register provides all needed values",
+ /* DESC */ "",
+ /* URL */ ,
+ /* DEP_EXTS */ ({"h"}),
+ /* SUPPORTED_VERSIONS */ ({{1, 0}}),
+ /* FLAG_GROUP */ sh,
+ /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED,
+ /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED,
+ /* EXTRA_EXTENSION_FLAGS */ 0)
+
+DEFINE_RISCV_EXT(
+ /* NAME */ shvstvecd,
+ /* UPPERCAE_NAME */ SHVSTVECD,
+ /* FULL_NAME */ "The vstvec register supports Direct mode",
+ /* DESC */ "",
+ /* URL */ ,
+ /* DEP_EXTS */ ({"h"}),
+ /* SUPPORTED_VERSIONS */ ({{1, 0}}),
+ /* FLAG_GROUP */ sh,
+ /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED,
+ /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED,
+ /* EXTRA_EXTENSION_FLAGS */ 0)
+
+DEFINE_RISCV_EXT(
+ /* NAME */ shvsatpa,
+ /* UPPERCAE_NAME */ SHVSATPA,
+ /* FULL_NAME */ "The vsatp register supports all modes supported by satp",
+ /* DESC */ "",
+ /* URL */ ,
+ /* DEP_EXTS */ ({"h"}),
+ /* SUPPORTED_VERSIONS */ ({{1, 0}}),
+ /* FLAG_GROUP */ sh,
+ /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED,
+ /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED,
+ /* EXTRA_EXTENSION_FLAGS */ 0)
+
DEFINE_RISCV_EXT(
/* NAME */ smaia,
/* UPPERCAE_NAME */ SMAIA,
diff --git a/gcc/config/riscv/riscv-ext.opt b/gcc/config/riscv/riscv-ext.opt
index 0c56dc9b2710..9199aa31b420 100644
--- a/gcc/config/riscv/riscv-ext.opt
+++ b/gcc/config/riscv/riscv-ext.opt
@@ -28,6 +28,9 @@ int riscv_base_subext
TargetVariable
int riscv_sd_subext
+TargetVariable
+int riscv_sh_subext
+
TargetVariable
int riscv_sm_subext
@@ -316,6 +319,20 @@ Mask(ZHINXMIN) Var(riscv_zinx_subext)
Mask(SDTRIG) Var(riscv_sd_subext)
+Mask(SHA) Var(riscv_sh_subext)
+
+Mask(SHCOUNTERENW) Var(riscv_sh_subext)
+
+Mask(SHGATPA) Var(riscv_sh_subext)
+
+Mask(SHTVALA) Var(riscv_sh_subext)
+
+Mask(SHVSTVALA) Var(riscv_sh_subext)
+
+Mask(SHVSTVECD) Var(riscv_sh_subext)
+
+Mask(SHVSATPA) Var(riscv_sh_subext)
+
Mask(SMAIA) Var(riscv_sm_subext)
Mask(SMEPMP) Var(riscv_sm_subext)
diff --git a/gcc/doc/riscv-ext.texi b/gcc/doc/riscv-ext.texi
index 968654bc39b0..bd3d29c75ab5 100644
--- a/gcc/doc/riscv-ext.texi
+++ b/gcc/doc/riscv-ext.texi
@@ -462,6 +462,34 @@
@tab 1.0
@tab sdtrig extension
+@item sha
+@tab 1.0
+@tab The augmented hypervisor extension
+
+@item shcounterenw
+@tab 1.0
+@tab Support writeable enables for any supported counter
+
+@item shgatpa
+@tab 1.0
+@tab SvNNx4 mode supported for all modes supported by satp
+
+@item shtvala
+@tab 1.0
+@tab The htval register provides all needed values
+
+@item shvstvala
+@tab 1.0
+@tab The vstval register provides all needed values
+
+@item shvstvecd
+@tab 1.0
+@tab The vstvec register supports Direct mode
+
+@item shvsatpa
+@tab 1.0
+@tab The vsatp register supports all modes supported by satp
+
@item smaia
@tab 1.0
@tab Advanced interrupt architecture extension
diff --git a/gcc/testsuite/gcc.target/riscv/arch-55.c b/gcc/testsuite/gcc.target/riscv/arch-55.c
new file mode 100644
index 000000000000..0e8a2940b58d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/arch-55.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64g_sha -mabi=lp64d" } */
+
+void foo(){}
+
+/* { dg-final { scan-assembler ".attribute arch, \"rv64i2p1_m2p0_a2p1_f2p2"
+"_d2p2_h1p0_zicsr2p0_zifencei2p0_zmmul1p0_zaamo1p0_zalrsc1p0_sha1p0"
+"_shcounterenw1p0_shgatpa1p0_shtvala1p0_shvsatpa1p0_shvstvala1p0_shvstvecd1p0"
+"_ssstateen1p0\"" } } */
\ No newline at end of file
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