[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Adjust the vmacc.vx combine test cases
Jeff Law
law@gcc.gnu.org
Sat Nov 8 06:26:04 GMT 2025
https://gcc.gnu.org/g:c9b62a509dce116ee2ff5b3d23dc600ee272f67c
commit c9b62a509dce116ee2ff5b3d23dc600ee272f67c
Author: Pan Li <pan2.li@intel.com>
Date: Tue Sep 2 12:34:40 2025 +0800
RISC-V: Adjust the vmacc.vx combine test cases
To avoid generating the vmadd.vx code.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/vx_vf/vx_ternary.h: Adjust the
vmacc.vx to avoid generating vmadd.
Signed-off-by: Pan Li <pan2.li@intel.com>
(cherry picked from commit 927ba84ec20e0a163ac20add4896909a0fa96c1e)
Diff:
---
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_ternary.h | 8 ++++++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_ternary.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_ternary.h
index 58bd94325d6f..06fde11fea8a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_ternary.h
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_ternary.h
@@ -12,12 +12,16 @@ typedef signed __int128 int128_t;
#endif
#define DEF_VX_TERNARY_CASE_0(T, OP_1, OP_2, NAME) \
-void \
+T \
test_vx_ternary_##NAME##_##T##_case_0 (T * restrict vd, T * restrict vs2, \
T rs1, unsigned n) \
{ \
- for (unsigned i = 0; i < n; i++) \
+ unsigned i; \
+ \
+ for (i = 0; i < n; i++) \
vd[i] = vd[i] OP_2 vs2[i] OP_1 rs1; \
+ \
+ return vs2[i - 1]; \
}
#define DEF_VX_TERNARY_CASE_0_WRAP(T, OP_1, OP_2, NAME) \
DEF_VX_TERNARY_CASE_0(T, OP_1, OP_2, NAME)
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