[gcc r16-1586] or1k: Implement *extendbisi* to fix ICE in convert_mode_scalar [PR120587]

[Stafford Horne]

https://gcc.gnu.org/g:625a3807dabd5130bc6ec153d80dfbbb096d00f8

commit r16-1586-g625a3807dabd5130bc6ec153d80dfbbb096d00f8
Author: Stafford Horne <shorne@gmail.com>
Date:   Wed Jun 18 21:47:03 2025 +0100

    or1k: Implement *extendbisi* to fix ICE in convert_mode_scalar [PR120587]
    
    After commit 2dcc6dbd8a0 ("emit-rtl: Use simplify_subreg_regno to
    validate hardware subregs [PR119966]") the OpenRISC port is broken
    again.
    
    Add extend* iinstruction patterns for the SR_F pseudo registers to avoid
    having to use the subreg conversions which no longer work.
    
    gcc/ChangeLog:
    
            PR target/120587
            * config/or1k/or1k.md (zero_extendbisi2_sr_f): New expand.
            (extendbisi2_sr_f): New expand.
            * config/or1k/predicates.md (sr_f_reg_operand): New predicate.
    
    Signed-off-by: Stafford Horne <shorne@gmail.com>

Diff:
---
 gcc/config/or1k/or1k.md       | 25 +++++++++++++++++++++++++
 gcc/config/or1k/predicates.md |  4 ++++
 2 files changed, 29 insertions(+)

diff --git a/gcc/config/or1k/or1k.md b/gcc/config/or1k/or1k.md
index 627e40084b34..a30cc18892da 100644
--- a/gcc/config/or1k/or1k.md
+++ b/gcc/config/or1k/or1k.md
@@ -515,6 +515,31 @@
 	(ne:SI (reg:BI SR_F_REGNUM) (const_int 0)))]
   "")
 
+;; Allowing "extending" the BImode SR_F to a general register
+;; avoids 'convert_mode_scalar' from trying to do subregging
+;; which we don't have support for.
+;; We require signed and unsigned extend instructions because
+;; signed comparisons require signed extention, but for SR_F
+;; it doesn't matter.
+
+(define_expand "zero_extendbisi2_sr_f"
+  [(set (match_operand:SI 0 "register_operand" "")
+	(zero_extend:SI (match_operand:BI 1 "sr_f_reg_operand" "")))]
+  ""
+{
+  emit_insn(gen_sne_sr_f (operands[0]));
+  DONE;
+})
+
+(define_expand "extendbisi2_sr_f"
+  [(set (match_operand:SI 0 "register_operand" "")
+	(sign_extend:SI (match_operand:BI 1 "sr_f_reg_operand" "")))]
+  ""
+{
+  emit_insn(gen_sne_sr_f (operands[0]));
+  DONE;
+})
+
 (define_insn_and_split "*scc"
   [(set (match_operand:SI 0 "register_operand" "=r")
 	(match_operator:SI 1 "equality_comparison_operator"
diff --git a/gcc/config/or1k/predicates.md b/gcc/config/or1k/predicates.md
index 144f4d7b5778..7ccfd09985dd 100644
--- a/gcc/config/or1k/predicates.md
+++ b/gcc/config/or1k/predicates.md
@@ -60,6 +60,10 @@
     (and (match_operand 0 "register_operand")
 	 (match_test "TARGET_ROR"))))
 
+(define_predicate "sr_f_reg_operand"
+  (and (match_operand 0 "register_operand")
+       (match_test "REGNO (op) == SR_F_REGNUM")))
+
 (define_predicate "call_insn_operand"
   (ior (and (match_code "symbol_ref")
 	    (match_test "!TARGET_CMODEL_LARGE"))