[gcc r16-1573] RISC-V: Add generic tune as default.

[Kito Cheng]

https://gcc.gnu.org/g:20f593018519fec1602dc39c08ba2e674a2d8a1c

commit r16-1573-g20f593018519fec1602dc39c08ba2e674a2d8a1c
Author: Dongyan Chen <chendongyan@isrc.iscas.ac.cn>
Date:   Wed Jun 18 19:47:28 2025 +0800

    RISC-V: Add generic tune as default.
    
    According to the discussion in
    https://gcc.gnu.org/pipermail/gcc-patches/2025-June/686893.html, by creating
    a -mtune=generic may be a good idea to slove the question regarding the branch
    cost.
    
    Changes for v2:
    - Delete the code about -mcpu=generic.
    
    gcc/ChangeLog:
    
            * config/riscv/riscv-cores.def (RISCV_TUNE): Add "generic" tune.
            * config/riscv/riscv.cc: Add generic_tune_info.
            * config/riscv/riscv.h (RISCV_TUNE_STRING_DEFAULT): Change default tune.
    
    gcc/testsuite/ChangeLog:
    
            * gcc.target/riscv/zicond-primitiveSemantics_compare_reg_reg_return_reg_reg.c: New test.

Diff:
---
 gcc/config/riscv/riscv-cores.def                   |  1 +
 gcc/config/riscv/riscv.cc                          | 23 ++++++++++++++++++++++
 gcc/config/riscv/riscv.h                           |  2 +-
 ...itiveSemantics_compare_reg_reg_return_reg_reg.c | 21 ++++++++++++++++++++
 4 files changed, 46 insertions(+), 1 deletion(-)

diff --git a/gcc/config/riscv/riscv-cores.def b/gcc/config/riscv/riscv-cores.def
index cff7c77a0bd7..2096c0095d4e 100644
--- a/gcc/config/riscv/riscv-cores.def
+++ b/gcc/config/riscv/riscv-cores.def
@@ -33,6 +33,7 @@
 #define RISCV_TUNE(TUNE_NAME, PIPELINE_MODEL, TUNE_INFO)
 #endif
 
+RISCV_TUNE("generic", generic, generic_tune_info)
 RISCV_TUNE("rocket", generic, rocket_tune_info)
 RISCV_TUNE("sifive-3-series", generic, rocket_tune_info)
 RISCV_TUNE("sifive-5-series", generic, rocket_tune_info)
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 5fa84e0466da..86444b0bef8e 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -450,6 +450,29 @@ static const struct cpu_vector_cost generic_vector_cost = {
   &rvv_regmove_vector_cost, /* regmove  */
 };
 
+/* Costs to use when optimizing for generic.  */
+static const struct riscv_tune_param generic_tune_info = {
+  {COSTS_N_INSNS (4), COSTS_N_INSNS (5)},	/* fp_add */
+  {COSTS_N_INSNS (4), COSTS_N_INSNS (5)},	/* fp_mul */
+  {COSTS_N_INSNS (20), COSTS_N_INSNS (20)},	/* fp_div */
+  {COSTS_N_INSNS (4), COSTS_N_INSNS (4)},	/* int_mul */
+  {COSTS_N_INSNS (33), COSTS_N_INSNS (65)},	/* int_div */
+  1,						/* issue_rate */
+  4,						/* branch_cost */
+  5,						/* memory_cost */
+  8,						/* fmv_cost */
+  true,						/* slow_unaligned_access */
+  false,					/* vector_unaligned_access */
+  false,					/* use_divmod_expansion */
+  false,					/* overlap_op_by_pieces */
+  false,					/* speculative_sched_vsetvl */
+  RISCV_FUSE_NOTHING,                           /* fusible_ops */
+  NULL,						/* vector cost */
+  NULL,						/* function_align */
+  NULL,						/* jump_align */
+  NULL,						/* loop_align */
+};
+
 /* Costs to use when optimizing for rocket.  */
 static const struct riscv_tune_param rocket_tune_info = {
   {COSTS_N_INSNS (4), COSTS_N_INSNS (5)},	/* fp_add */
diff --git a/gcc/config/riscv/riscv.h b/gcc/config/riscv/riscv.h
index 2759a4cb1c9f..45fa521f219f 100644
--- a/gcc/config/riscv/riscv.h
+++ b/gcc/config/riscv/riscv.h
@@ -43,7 +43,7 @@ along with GCC; see the file COPYING3.  If not see
 #endif
 
 #ifndef RISCV_TUNE_STRING_DEFAULT
-#define RISCV_TUNE_STRING_DEFAULT "rocket"
+#define RISCV_TUNE_STRING_DEFAULT "generic"
 #endif
 
 extern const char *riscv_expand_arch (int argc, const char **argv);
diff --git a/gcc/testsuite/gcc.target/riscv/zicond-primitiveSemantics_compare_reg_reg_return_reg_reg.c b/gcc/testsuite/gcc.target/riscv/zicond-primitiveSemantics_compare_reg_reg_return_reg_reg.c
new file mode 100644
index 000000000000..1ad1b77a2e65
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/zicond-primitiveSemantics_compare_reg_reg_return_reg_reg.c
@@ -0,0 +1,21 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_zicond -mabi=lp64d -mtune=generic" { target { rv64 } } } */
+/* { dg-options "-march=rv32gc_zicond -mabi=ilp32f -mtune=generic" { target { rv32 } } } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" "-O3" } } */
+
+#define N 10000
+
+int primitiveSemantics_compare_reg_reg_return_reg_reg_00(int *a, int min_v)
+{
+  int last = 0;
+
+  for (int i = 0; i < N; i++)
+  {
+    if (a[i] < min_v)
+      last = a[i];
+  }
+  return last;
+}
+
+/* { dg-final { scan-assembler-times {\mczero\.nez\M} 1 } } */
+/* { dg-final { scan-assembler-times {\mczero\.eqz\M} 1 } } */