[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Update Profiles string in RV23.

[Jeff Law]

https://gcc.gnu.org/g:b5c60ee96b72e26334979441f2877b316a3cb7ed

commit b5c60ee96b72e26334979441f2877b316a3cb7ed
Author: Jiawei <jiawei@iscas.ac.cn>
Date:   Mon Jun 16 11:21:29 2025 +0800

    RISC-V: Update Profiles string in RV23.
    
    Add b-ext in RVA/B23 as independent extension flags and add supm in
    RVA23.
    
    gcc/ChangeLog:
    
            * common/config/riscv/riscv-common.cc: Add b-ext and supm.
    
    gcc/testsuite/ChangeLog:
    
            * gcc.target/riscv/arch-53.c: Update testcase.
    
    (cherry picked from commit b2af07bac21862d038bc1583cff97c2f3fb99e74)

Diff:
---
 gcc/common/config/riscv/riscv-common.cc  | 6 +++---
 gcc/testsuite/gcc.target/riscv/arch-53.c | 2 +-
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc
index 6b5440365e33..3c25848ccd38 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -290,15 +290,15 @@ static const riscv_profiles riscv_profiles_table[] =
   /* RVA23 contains all mandatory base ISA for RVA22U64 and the new extension
      'v,zihintntl,zvfhmin,zvbb,zvkt,zicond,zimop,zcmop,zfa,zawrs' as mandatory
      extensions.  */
-  {"rva23u64", "rv64imafdcv_zicsr_zicntr_zihpm_ziccif_ziccrse_ziccamoa"
+  {"rva23u64", "rv64imafdcbv_zicsr_zicntr_zihpm_ziccif_ziccrse_ziccamoa"
    "_zicclsm_zic64b_za64rs_zihintpause_zba_zbb_zbs_zicbom_zicbop"
    "_zicboz_zfhmin_zkt_zvfhmin_zvbb_zvkt_zihintntl_zicond_zimop_zcmop_zcb"
-   "_zfa_zawrs"},
+   "_zfa_zawrs_supm"},
 
   /* RVB23 contains all mandatory base ISA for RVA22U64 and the new extension
      'zihintntl,zicond,zimop,zcmop,zfa,zawrs' as mandatory
      extensions.  */
-  {"rvb23u64", "rv64imafdc_zicsr_zicntr_zihpm_ziccif_ziccrse_ziccamoa"
+  {"rvb23u64", "rv64imafdcb_zicsr_zicntr_zihpm_ziccif_ziccrse_ziccamoa"
    "_zicclsm_zic64b_za64rs_zihintpause_zba_zbb_zbs_zicbom_zicbop"
    "_zicboz_zfhmin_zkt_zihintntl_zicond_zimop_zcmop_zcb"
    "_zfa_zawrs"},
diff --git a/gcc/testsuite/gcc.target/riscv/arch-53.c b/gcc/testsuite/gcc.target/riscv/arch-53.c
index 8210978ee8ba..43ab23aee4d8 100644
--- a/gcc/testsuite/gcc.target/riscv/arch-53.c
+++ b/gcc/testsuite/gcc.target/riscv/arch-53.c
@@ -8,4 +8,4 @@ void foo(){}
 _ziccrse1p0_zicntr2p0_zicond1p0_zicsr2p0_zihintntl1p0_zihintpause2p0_zihpm2p0_zimop1p0"
 _za64rs1p0_zaamo1p0_zalrsc1p0_zawrs1p0_zfa1p0_zfhmin1p0_zca1p0_zcb1p0_zcd1p0_zcmop1p0"
 _zba1p0_zbb1p0_zbs1p0_zkt1p0_zvbb1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0"
-_zvfhmin1p0_zvkb1p0_zvkt1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0\"" } } */
+_zvfhmin1p0_zvkb1p0_zvkt1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_supm1p0\"" } } */