[gcc(refs/users/meissner/heads/work210-sha)] PR target/117251: Add PowerPC XXEVAL support to speed up SHA3 calculations

[Michael Meissner]

https://gcc.gnu.org/g:539aa4e4b24ae01bdf157cd10feb7dc9ce63c5ca

commit 539aa4e4b24ae01bdf157cd10feb7dc9ce63c5ca
Author: Michael Meissner <meissner@linux.ibm.com>
Date:   Tue Jun 10 17:22:37 2025 -0400

    PR target/117251: Add PowerPC XXEVAL support to speed up SHA3 calculations
    
    2025-06-10  Michael Meissner  <meissner@linux.ibm.com>
    
    gcc/
    
            PR target/117251
            * config/rs6000/fusion.md: Regenerate.
            * config/rs6000/genfusion.pl (gen_logical_addsubf): Add support to
            generate vector xor => nor fusion if XXEVAL is supported.

Diff:
---
 gcc/config/rs6000/fusion.md    | 15 +++++++++------
 gcc/config/rs6000/genfusion.pl |  1 +
 2 files changed, 10 insertions(+), 6 deletions(-)

diff --git a/gcc/config/rs6000/fusion.md b/gcc/config/rs6000/fusion.md
index 66d98f4537e1..e5ea37c567d6 100644
--- a/gcc/config/rs6000/fusion.md
+++ b/gcc/config/rs6000/fusion.md
@@ -2618,20 +2618,23 @@
 ;; logical-logical fusion pattern generated by gen_logical_addsubf
 ;; vector vxor -> vnor
 (define_insn "*fuse_vxor_vnor"
-  [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v")
-        (and:VM (not:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")
-                          (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")))
-                 (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))))
-   (clobber (match_scratch:VM 4 "=X,X,X,&v"))]
+  [(set (match_operand:VM 3 "vector_fusion_operand" "=&0,&1,&v,wa,v")
+        (and:VM (not:VM (xor:VM (match_operand:VM 0 "vector_fusion_operand" "v,v,v,wa,v")
+                          (match_operand:VM 1 "vector_fusion_operand" "v,v,v,wa,v")))
+                 (not:VM (match_operand:VM 2 "vector_fusion_operand" "v,v,v,wa,v"))))
+   (clobber (match_scratch:VM 4 "=X,X,X,X,&v"))]
   "(TARGET_P10_FUSION)"
   "@
    vxor %3,%1,%0\;vnor %3,%3,%2
    vxor %3,%1,%0\;vnor %3,%3,%2
    vxor %3,%1,%0\;vnor %3,%3,%2
+   xxeval %x3,%x2,%x1,%x0,144
    vxor %4,%1,%0\;vnor %3,%4,%2"
   [(set_attr "type" "fused_vector")
    (set_attr "cost" "6")
-   (set_attr "length" "8")])
+   (set_attr "length" "8")
+   (set_attr "prefixed" "*,*,*,yes,*")
+   (set_attr "isa" "*,*,*,xxeval,*")])
 
 ;; logical-logical fusion pattern generated by gen_logical_addsubf
 ;; vector vand -> vor
diff --git a/gcc/config/rs6000/genfusion.pl b/gcc/config/rs6000/genfusion.pl
index 98b56b788f03..d713d10a1dbc 100755
--- a/gcc/config/rs6000/genfusion.pl
+++ b/gcc/config/rs6000/genfusion.pl
@@ -241,6 +241,7 @@ sub gen_logical_addsubf
       "vor_vnor"    => 128,
       "vnor_vxor"   => 135,
       "vnor_vor"    => 143,
+      "vxor_vnor"   => 144,
     );
 
     KIND: foreach $kind ('scalar','vector') {