[gcc r16-1174] RISC-V: Support Sm/scsrind extensions.

[Jiawei Chen]

https://gcc.gnu.org/g:d4129d83135527823730566468ac111067d0dc2d

commit r16-1174-gd4129d83135527823730566468ac111067d0dc2d
Author: Jiawei <jiawei@iscas.ac.cn>
Date:   Thu Jun 5 10:16:19 2025 +0800

    RISC-V: Support Sm/scsrind extensions.
    
    Support the Sm/scsrind extensions, which provide indirect access to
    machine-level CSRs.
    
    gcc/ChangeLog:
    
            * config/riscv/riscv-ext.def: New extension definition.
            * config/riscv/riscv-ext.opt: New extension mask.
            * doc/riscv-ext.texi: Document the new extension.
    
    gcc/testsuite/ChangeLog:
    
            * gcc.target/riscv/arch-smcsrind.c: New test.
    
    Signed-off-by: Jiawei <jiawei@iscas.ac.cn>

Diff:
---
 gcc/config/riscv/riscv-ext.def                 | 26 ++++++++++++++++++++++++++
 gcc/config/riscv/riscv-ext.opt                 |  4 ++++
 gcc/doc/riscv-ext.texi                         |  8 ++++++++
 gcc/testsuite/gcc.target/riscv/arch-smcsrind.c |  5 +++++
 4 files changed, 43 insertions(+)

diff --git a/gcc/config/riscv/riscv-ext.def b/gcc/config/riscv/riscv-ext.def
index 0d715a163c74..6c122c3987b0 100644
--- a/gcc/config/riscv/riscv-ext.def
+++ b/gcc/config/riscv/riscv-ext.def
@@ -1701,6 +1701,19 @@ DEFINE_RISCV_EXT(
   /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED,
   /* EXTRA_EXTENSION_FLAGS */ 0)
 
+DEFINE_RISCV_EXT(
+  /* NAME */ smcsrind,
+  /* UPPERCASE_NAME */ SMCSRIND,
+  /* FULL_NAME */ "Machine-Level Indirect CSR Access",
+  /* DESC */ "",
+  /* URL */ ,
+  /* DEP_EXTS */ ({"zicsr", "sscsrind"}),
+  /* SUPPORTED_VERSIONS */ ({{1, 0}}),
+  /* FLAG_GROUP */ sm,
+  /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED,
+  /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED,
+  /* EXTRA_EXTENSION_FLAGS */ 0)
+
 DEFINE_RISCV_EXT(
   /* NAME */ smepmp,
   /* UPPERCASE_NAME */ SMEPMP,
@@ -1792,6 +1805,19 @@ DEFINE_RISCV_EXT(
   /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED,
   /* EXTRA_EXTENSION_FLAGS */ 0)
 
+DEFINE_RISCV_EXT(
+  /* NAME */ sscsrind,
+  /* UPPERCASE_NAME */ SSCSRIND,
+  /* FULL_NAME */ "Supervisor-Level Indirect CSR Access",
+  /* DESC */ "",
+  /* URL */ ,
+  /* DEP_EXTS */ ({"zicsr"}),
+  /* SUPPORTED_VERSIONS */ ({{1, 0}}),
+  /* FLAG_GROUP */ ss,
+  /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED,
+  /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED,
+  /* EXTRA_EXTENSION_FLAGS */ 0)
+
 DEFINE_RISCV_EXT(
   /* NAME */ ssnpm,
   /* UPPERCASE_NAME */ SSNPM,
diff --git a/gcc/config/riscv/riscv-ext.opt b/gcc/config/riscv/riscv-ext.opt
index 3e5cbb34898e..725dc8793494 100644
--- a/gcc/config/riscv/riscv-ext.opt
+++ b/gcc/config/riscv/riscv-ext.opt
@@ -339,6 +339,8 @@ Mask(SMAIA) Var(riscv_sm_subext)
 
 Mask(SMCNTRPMF) Var(riscv_sm_subext)
 
+Mask(SMCSRIND) Var(riscv_sm_subext)
+
 Mask(SMEPMP) Var(riscv_sm_subext)
 
 Mask(SMMPM) Var(riscv_sm_subext)
@@ -353,6 +355,8 @@ Mask(SSAIA) Var(riscv_ss_subext)
 
 Mask(SSCOFPMF) Var(riscv_ss_subext)
 
+Mask(SSCSRIND) Var(riscv_ss_subext)
+
 Mask(SSNPM) Var(riscv_ss_subext)
 
 Mask(SSPM) Var(riscv_ss_subext)
diff --git a/gcc/doc/riscv-ext.texi b/gcc/doc/riscv-ext.texi
index 3e6541ac732b..ca7414e0c7a0 100644
--- a/gcc/doc/riscv-ext.texi
+++ b/gcc/doc/riscv-ext.texi
@@ -502,6 +502,10 @@
 @tab 1.0
 @tab Cycle and instret privilege mode filtering
 
+@item smcsrind
+@tab 1.0
+@tab Machine-Level Indirect CSR Access
+
 @item smepmp
 @tab 1.0
 @tab PMP Enhancements for memory access and execution prevention on Machine mode
@@ -530,6 +534,10 @@
 @tab 1.0
 @tab Count overflow & filtering extension
 
+@item sscsrind
+@tab 1.0
+@tab Supervisor-Level Indirect CSR Access
+
 @item ssnpm
 @tab 1.0
 @tab ssnpm extension
diff --git a/gcc/testsuite/gcc.target/riscv/arch-smcsrind.c b/gcc/testsuite/gcc.target/riscv/arch-smcsrind.c
new file mode 100644
index 000000000000..4d1c10453993
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/arch-smcsrind.c
@@ -0,0 +1,5 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64i_smcsrind -mabi=lp64" } */
+int foo()
+{
+}