[gcc(refs/users/meissner/heads/work230)] Revert changes
Michael Meissner
meissner@gcc.gnu.org
Mon Dec 8 19:21:21 GMT 2025
https://gcc.gnu.org/g:8a69bd1316546c01ad2821f5f1286cc3dffcbf9f
commit 8a69bd1316546c01ad2821f5f1286cc3dffcbf9f
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Thu Dec 4 23:51:07 2025 -0500
Revert changes
Diff:
---
gcc/config.gcc | 4 ++--
gcc/config/rs6000/aix71.h | 1 -
gcc/config/rs6000/aix72.h | 1 -
gcc/config/rs6000/aix73.h | 1 -
gcc/config/rs6000/rs6000-c.cc | 2 --
gcc/config/rs6000/rs6000-cpus.def | 13 -------------
gcc/config/rs6000/rs6000-opts.h | 2 --
gcc/config/rs6000/rs6000-tables.opt | 11 ++++-------
gcc/config/rs6000/rs6000.cc | 5 +----
gcc/config/rs6000/rs6000.h | 1 -
gcc/config/rs6000/rs6000.opt | 5 -----
gcc/doc/invoke.texi | 2 +-
gcc/testsuite/gcc.target/powerpc/future-1.c | 13 -------------
gcc/testsuite/gcc.target/powerpc/future-2.c | 24 ------------------------
gcc/testsuite/gcc.target/powerpc/future-3.c | 22 ----------------------
15 files changed, 8 insertions(+), 99 deletions(-)
diff --git a/gcc/config.gcc b/gcc/config.gcc
index 74b6aee9656a..fb465dac1477 100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -543,7 +543,7 @@ powerpc*-*-*)
extra_headers="${extra_headers} ppu_intrinsics.h spu2vmx.h vec_types.h si2vmx.h"
extra_headers="${extra_headers} amo.h"
case x$with_cpu in
- xpowerpc64|xdefault64|x6[23]0|x970|xG5|xpower[3456789]|xpower1[01]|xpower6x|xrs64a|xcell|xa2|xe500mc64|xe5500|xe6500|xfuture)
+ xpowerpc64|xdefault64|x6[23]0|x970|xG5|xpower[3456789]|xpower1[01]|xpower6x|xrs64a|xcell|xa2|xe500mc64|xe5500|xe6500)
cpu_is_64bit=yes
;;
esac
@@ -5750,7 +5750,7 @@ case "${target}" in
tm_defines="${tm_defines} CONFIG_PPC405CR"
eval "with_$which=405"
;;
- "" | common | native | future \
+ "" | common | native \
| power[3456789] | power1[01] | power5+ | power6x \
| powerpc | powerpc64 | powerpc64le \
| rs64 \
diff --git a/gcc/config/rs6000/aix71.h b/gcc/config/rs6000/aix71.h
index 77651f5ea309..2b21dd7cd1e0 100644
--- a/gcc/config/rs6000/aix71.h
+++ b/gcc/config/rs6000/aix71.h
@@ -79,7 +79,6 @@ do { \
#undef ASM_CPU_SPEC
#define ASM_CPU_SPEC \
"%{mcpu=native: %(asm_cpu_native); \
- mcpu=future: -mfuture; \
mcpu=power11: -mpwr11; \
mcpu=power10: -mpwr10; \
mcpu=power9: -mpwr9; \
diff --git a/gcc/config/rs6000/aix72.h b/gcc/config/rs6000/aix72.h
index 652f60c7f494..53c0bde5ad4a 100644
--- a/gcc/config/rs6000/aix72.h
+++ b/gcc/config/rs6000/aix72.h
@@ -79,7 +79,6 @@ do { \
#undef ASM_CPU_SPEC
#define ASM_CPU_SPEC \
"%{mcpu=native: %(asm_cpu_native); \
- mcpu=future: -mfuture; \
mcpu=power11: -mpwr11; \
mcpu=power10: -mpwr10; \
mcpu=power9: -mpwr9; \
diff --git a/gcc/config/rs6000/aix73.h b/gcc/config/rs6000/aix73.h
index 3c66ac1d9171..c7639368a264 100644
--- a/gcc/config/rs6000/aix73.h
+++ b/gcc/config/rs6000/aix73.h
@@ -79,7 +79,6 @@ do { \
#undef ASM_CPU_SPEC
#define ASM_CPU_SPEC \
"%{mcpu=native: %(asm_cpu_native); \
- mcpu=future: -mfuture; \
mcpu=power11: -mpwr11; \
mcpu=power10: -mpwr10; \
mcpu=power9: -mpwr9; \
diff --git a/gcc/config/rs6000/rs6000-c.cc b/gcc/config/rs6000/rs6000-c.cc
index 6757a2477ad1..d3b0a5668212 100644
--- a/gcc/config/rs6000/rs6000-c.cc
+++ b/gcc/config/rs6000/rs6000-c.cc
@@ -437,8 +437,6 @@ rs6000_target_modify_macros (bool define_p, HOST_WIDE_INT flags)
rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR10");
if ((flags & OPTION_MASK_POWER11) != 0)
rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR11");
- if ((flags & OPTION_MASK_FUTURE) != 0)
- rs6000_define_or_undefine_macro (define_p, "_ARCH_FUTURE");
if ((flags & OPTION_MASK_SOFT_FLOAT) != 0)
rs6000_define_or_undefine_macro (define_p, "_SOFT_FLOAT");
if ((flags & OPTION_MASK_RECIP_PRECISION) != 0)
diff --git a/gcc/config/rs6000/rs6000-cpus.def b/gcc/config/rs6000/rs6000-cpus.def
index 5a031fe6e483..4a1037616d7f 100644
--- a/gcc/config/rs6000/rs6000-cpus.def
+++ b/gcc/config/rs6000/rs6000-cpus.def
@@ -83,16 +83,6 @@
#define POWER11_MASKS_SERVER (ISA_3_1_MASKS_SERVER \
| OPTION_MASK_POWER11)
-/* -mcpu=future flags.
-
- During the development of the power10 support for GCC, using load/store
- vector pair instructions for string operations was turned off by default,
- because there was a use case that had really bad performance. Assume this
- will be fixed in potential future machines. */
-#define FUTURE_MASKS_SERVER (POWER11_MASKS_SERVER \
- | OPTION_MASK_BLOCK_OPS_VECTOR_PAIR \
- | OPTION_MASK_FUTURE)
-
/* Flags that need to be turned off if -mno-vsx. */
#define OTHER_VSX_VECTOR_MASKS (OPTION_MASK_EFFICIENT_UNALIGNED_VSX \
| OPTION_MASK_FLOAT128_KEYWORD \
@@ -121,7 +111,6 @@
/* Mask of all options to set the default isa flags based on -mcpu=<xxx>. */
#define POWERPC_MASKS (OPTION_MASK_ALTIVEC \
- | OPTION_MASK_BLOCK_OPS_VECTOR_PAIR \
| OPTION_MASK_CMPB \
| OPTION_MASK_CRYPTO \
| OPTION_MASK_DFP \
@@ -130,7 +119,6 @@
| OPTION_MASK_FLOAT128_HW \
| OPTION_MASK_FLOAT128_KEYWORD \
| OPTION_MASK_FPRND \
- | OPTION_MASK_FUTURE \
| OPTION_MASK_POWER10 \
| OPTION_MASK_POWER11 \
| OPTION_MASK_P10_FUSION \
@@ -261,7 +249,6 @@ RS6000_CPU ("power9", PROCESSOR_POWER9, MASK_POWERPC64 | ISA_3_0_MASKS_SERVER
| OPTION_MASK_HTM)
RS6000_CPU ("power10", PROCESSOR_POWER10, MASK_POWERPC64 | ISA_3_1_MASKS_SERVER)
RS6000_CPU ("power11", PROCESSOR_POWER11, MASK_POWERPC64 | POWER11_MASKS_SERVER)
-RS6000_CPU ("future", PROCESSOR_FUTURE, MASK_POWERPC64 | FUTURE_MASKS_SERVER)
RS6000_CPU ("powerpc", PROCESSOR_POWERPC, 0)
RS6000_CPU ("powerpc64", PROCESSOR_POWERPC64, OPTION_MASK_PPC_GFXOPT
| MASK_POWERPC64)
diff --git a/gcc/config/rs6000/rs6000-opts.h b/gcc/config/rs6000/rs6000-opts.h
index e13ba2ba5274..c31d2975f046 100644
--- a/gcc/config/rs6000/rs6000-opts.h
+++ b/gcc/config/rs6000/rs6000-opts.h
@@ -71,8 +71,6 @@ enum processor_type
PROCESSOR_TITAN
};
-/* For now, just use power11 as the base processor for -mcpu=future. */
-#define PROCESSOR_FUTURE PROCESSOR_POWER11
/* Types of costly dependences. */
enum rs6000_dependence_cost
diff --git a/gcc/config/rs6000/rs6000-tables.opt b/gcc/config/rs6000/rs6000-tables.opt
index 518324e7aead..f5bbed5ea746 100644
--- a/gcc/config/rs6000/rs6000-tables.opt
+++ b/gcc/config/rs6000/rs6000-tables.opt
@@ -189,17 +189,14 @@ EnumValue
Enum(rs6000_cpu_opt_value) String(power11) Value(53)
EnumValue
-Enum(rs6000_cpu_opt_value) String(future) Value(54)
+Enum(rs6000_cpu_opt_value) String(powerpc) Value(54)
EnumValue
-Enum(rs6000_cpu_opt_value) String(powerpc) Value(55)
+Enum(rs6000_cpu_opt_value) String(powerpc64) Value(55)
EnumValue
-Enum(rs6000_cpu_opt_value) String(powerpc64) Value(56)
+Enum(rs6000_cpu_opt_value) String(powerpc64le) Value(56)
EnumValue
-Enum(rs6000_cpu_opt_value) String(powerpc64le) Value(57)
-
-EnumValue
-Enum(rs6000_cpu_opt_value) String(rs64) Value(58)
+Enum(rs6000_cpu_opt_value) String(rs64) Value(57)
diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index cb087640ebcf..bf899adc5315 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -5911,10 +5911,8 @@ rs6000_machine_from_flags (void)
/* Disable the flags that should never influence the .machine selection. */
flags &= ~(OPTION_MASK_PPC_GFXOPT | OPTION_MASK_PPC_GPOPT | OPTION_MASK_ISEL
- | OPTION_MASK_ALTIVEC | OPTION_MASK_BLOCK_OPS_VECTOR_PAIR);
+ | OPTION_MASK_ALTIVEC);
- if ((flags & (FUTURE_MASKS_SERVER & ~POWER11_MASKS_SERVER)) != 0)
- return "future";
if ((flags & (POWER11_MASKS_SERVER & ~ISA_3_1_MASKS_SERVER)) != 0)
return "power11";
if ((flags & (ISA_3_1_MASKS_SERVER & ~ISA_3_0_MASKS_SERVER)) != 0)
@@ -24467,7 +24465,6 @@ static struct rs6000_opt_mask const rs6000_opt_masks[] =
{ "fprnd", OPTION_MASK_FPRND, false, true },
{ "power10", OPTION_MASK_POWER10, false, true },
{ "power11", OPTION_MASK_POWER11, false, false },
- { "future", OPTION_MASK_FUTURE, false, false },
{ "hard-dfp", OPTION_MASK_DFP, false, true },
{ "htm", OPTION_MASK_HTM, false, true },
{ "isel", OPTION_MASK_ISEL, false, true },
diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h
index 76c6cd1ab8ef..db6112a09e11 100644
--- a/gcc/config/rs6000/rs6000.h
+++ b/gcc/config/rs6000/rs6000.h
@@ -101,7 +101,6 @@
you make changes here, make them also there. */
#define ASM_CPU_SPEC \
"%{mcpu=native: %(asm_cpu_native); \
- mcpu=future: -mfuture; \
mcpu=power11: -mpower11; \
mcpu=power10: -mpower10; \
mcpu=power9: -mpower9; \
diff --git a/gcc/config/rs6000/rs6000.opt b/gcc/config/rs6000/rs6000.opt
index b53d480bf547..88cf16ca581a 100644
--- a/gcc/config/rs6000/rs6000.opt
+++ b/gcc/config/rs6000/rs6000.opt
@@ -595,11 +595,6 @@ Target Undocumented Mask(POWER10) Var(rs6000_isa_flags) WarnRemoved
mpower11
Target Undocumented Mask(POWER11) Var(rs6000_isa_flags) WarnRemoved
-;; Potential future machine
-mfuture
-Target Undocumented Mask(FUTURE) Var(rs6000_isa_flags) Warn(Do not use %<-mfuture>, use %<-mcpu=future>)
-Generate (do not generate) potential future instructions.
-
mprefixed
Target Mask(PREFIXED) Var(rs6000_isa_flags)
Generate (do not generate) prefixed memory instructions.
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index e1e559796966..b89fbf8dbbc1 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -32462,7 +32462,7 @@ Supported values for @var{cpu_type} are @samp{401}, @samp{403},
@samp{titan}, @samp{power3}, @samp{power4}, @samp{power5}, @samp{power5+},
@samp{power6}, @samp{power6x}, @samp{power7}, @samp{power8},
@samp{power9}, @samp{power10}, @samp{power11}, @samp{powerpc}, @samp{powerpc64},
-@samp{powerpc64le}, @samp{rs64}, @samp{future}, and @samp{native}.
+@samp{powerpc64le}, @samp{rs64}, and @samp{native}.
@option{-mcpu=powerpc}, @option{-mcpu=powerpc64}, and
@option{-mcpu=powerpc64le} specify pure 32-bit PowerPC (either
diff --git a/gcc/testsuite/gcc.target/powerpc/future-1.c b/gcc/testsuite/gcc.target/powerpc/future-1.c
deleted file mode 100644
index 7bd8e5ddbd00..000000000000
--- a/gcc/testsuite/gcc.target/powerpc/future-1.c
+++ /dev/null
@@ -1,13 +0,0 @@
-/* { dg-do compile } */
-/* { dg-options "-mdejagnu-cpu=future -O2" } */
-
-/* Basic check to see if the compiler supports -mcpu=future and if it defines
- _ARCH_FUTURE. */
-
-#ifndef _ARCH_FUTURE
-#error "-mcpu=future is not supported"
-#endif
-
-void foo (void)
-{
-}
diff --git a/gcc/testsuite/gcc.target/powerpc/future-2.c b/gcc/testsuite/gcc.target/powerpc/future-2.c
deleted file mode 100644
index 5552cefa3c2e..000000000000
--- a/gcc/testsuite/gcc.target/powerpc/future-2.c
+++ /dev/null
@@ -1,24 +0,0 @@
-/* { dg-do compile } */
-/* { dg-options "-O2" } */
-
-/* Check if we can set the future target via a target attribute. */
-
-__attribute__((__target__("cpu=power9")))
-void foo_p9 (void)
-{
-}
-
-__attribute__((__target__("cpu=power10")))
-void foo_p10 (void)
-{
-}
-
-__attribute__((__target__("cpu=power11")))
-void foo_p11 (void)
-{
-}
-
-__attribute__((__target__("cpu=future")))
-void foo_future (void)
-{
-}
diff --git a/gcc/testsuite/gcc.target/powerpc/future-3.c b/gcc/testsuite/gcc.target/powerpc/future-3.c
deleted file mode 100644
index afa22228b96d..000000000000
--- a/gcc/testsuite/gcc.target/powerpc/future-3.c
+++ /dev/null
@@ -1,22 +0,0 @@
-/* 32-bit doesn't generate vector pair instructions. */
-/* { dg-do compile { target lp64 } } */
-/* { dg-options "-mdejagnu-cpu=future -O2" } */
-
-/* Test to see that memcpy will use load/store vector pair with
- -mcpu=future. */
-
-#ifndef SIZE
-#define SIZE 4
-#endif
-
-extern vector double to[SIZE], from[SIZE];
-
-void
-copy (void)
-{
- __builtin_memcpy (to, from, sizeof (to));
- return;
-}
-
-/* { dg-final { scan-assembler {\mlxvpx?\M} } } */
-/* { dg-final { scan-assembler {\mstxvpx?\M} } } */
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