[gcc/devel/sh-lra] SH: try to workaround fp-reg related move insns
Oleg Endo
olegendo@gcc.gnu.org
Wed Sep 25 01:25:31 GMT 2024
https://gcc.gnu.org/g:b924a79f5d3a8d32e4e65e62b63dc4432076af1d
commit b924a79f5d3a8d32e4e65e62b63dc4432076af1d
Author: Kaz Kojima <kkojima@rr.iij4u.or.jp>
Date: Fri Sep 20 18:17:31 2024 +0900
SH: try to workaround fp-reg related move insns
LRA will try to satisfy the constraints in match_scratch for the memory
displacements and it will make issues on this target. To mitigate the
issue, split movsf_ie_ra into several new patterns to remove
match_scratch. Also define a new sub-pattern of movdf for constant
loads.
gcc/ChangeLog:
* gcc/config/sh/predicates.md (pc_relative_load_operand):
New predicate.
* gcc/config/sh/sh-protos.h (sh_movsf_ie_ra_split_p): Remove.
(sh_movsf_ie_y_split_p): New proto.
* gcc/config/sh/sh.cc: (sh_movsf_ie_ra_split_p): Remove.
(sh_movsf_ie_y_split_p): New function.
(broken_move): Take movsf_ie_ra into account for fldi cases.
* gcc/config/sh/sh.md (movdf_i4_F_z): New insn pattern.
(movdf): Use it.
(movsf_ie_ra): Use define_insn instead of define_insn_and_split.
(movsf_ie_F_z, movsf_ie_Q_z, movsf_ie_y): New insn pattern.
(movsf): Use new patterns.
(movsf-1): Don't split when operands[0] or operands[1]
is fpul.
(movdf_i4_F_z+7): New splitter.
Diff:
---
gcc/config/sh/predicates.md | 11 +++++
gcc/config/sh/sh-protos.h | 2 +-
gcc/config/sh/sh.cc | 30 ++++---------
gcc/config/sh/sh.md | 103 +++++++++++++++++++++++++++++++-------------
4 files changed, 95 insertions(+), 51 deletions(-)
diff --git a/gcc/config/sh/predicates.md b/gcc/config/sh/predicates.md
index da32329b4b54..3732cec9608b 100644
--- a/gcc/config/sh/predicates.md
+++ b/gcc/config/sh/predicates.md
@@ -485,6 +485,17 @@
&& sh_legitimate_index_p (mode, XEXP (plus0_rtx, 1), TARGET_SH2A, true);
})
+;; Returns true if OP is a pc relative load operand.
+(define_predicate "pc_relative_load_operand"
+ (match_code "mem")
+{
+ if (GET_MODE (op) != QImode
+ && IS_PC_RELATIVE_LOAD_ADDR_P (XEXP (op, 0)))
+ return true;
+
+ return false;
+})
+
;; Returns true if OP is a valid source operand for a logical operation.
(define_predicate "logical_operand"
(and (match_code "subreg,reg,const_int")
diff --git a/gcc/config/sh/sh-protos.h b/gcc/config/sh/sh-protos.h
index 5e5bd0aff7e7..ffbe5164f08c 100644
--- a/gcc/config/sh/sh-protos.h
+++ b/gcc/config/sh/sh-protos.h
@@ -103,7 +103,7 @@ extern rtx sh_find_equiv_gbr_addr (rtx_insn* cur_insn, rtx mem);
extern int sh_eval_treg_value (rtx op);
extern HOST_WIDE_INT sh_disp_addr_displacement (rtx mem_op);
extern int sh_max_mov_insn_displacement (machine_mode mode, bool consider_sh2a);
-extern bool sh_movsf_ie_ra_split_p (rtx, rtx, rtx);
+extern bool sh_movsf_ie_y_split_p (rtx, rtx);
extern void sh_expand_sym_label2reg (rtx, rtx, rtx, bool);
/* Result value of sh_find_set_of_reg. */
diff --git a/gcc/config/sh/sh.cc b/gcc/config/sh/sh.cc
index c9222c3e6ac0..b2ba7488c5de 100644
--- a/gcc/config/sh/sh.cc
+++ b/gcc/config/sh/sh.cc
@@ -4832,6 +4832,7 @@ broken_move (rtx_insn *insn)
we changed this to do a constant load. In that case
we don't have an r0 clobber, hence we must use fldi. */
&& (TARGET_FMOVD
+ || sh_lra_p ()
|| (GET_CODE (XEXP (XVECEXP (PATTERN (insn), 0, 2), 0))
== SCRATCH))
&& REG_P (SET_DEST (pat))
@@ -11455,30 +11456,17 @@ sh_legitimize_address_displacement (rtx *offset1, rtx *offset2,
return false;
}
-/* Return true if movsf insn should be splited with an additional
- register. */
+/* Return true if movsf insn should be splited with fpul register. */
bool
-sh_movsf_ie_ra_split_p (rtx op0, rtx op1, rtx op2)
+sh_movsf_ie_y_split_p (rtx op0, rtx op1)
{
- /* op0 == op1 */
- if (rtx_equal_p (op0, op1))
+ /* f, r */
+ if (REG_P (op0)
+ && (SUBREG_P (op1) && GET_MODE (SUBREG_REG (op1)) == SImode))
return true;
- /* fy, FQ, reg */
- if (GET_CODE (op1) == CONST_DOUBLE
- && ! satisfies_constraint_G (op1)
- && ! satisfies_constraint_H (op1)
- && REG_P (op0)
- && REG_P (op2))
- return true;
- /* f, r, y */
- if (REG_P (op0) && FP_REGISTER_P (REGNO (op0))
- && REG_P (op1) && GENERAL_REGISTER_P (REGNO (op1))
- && REG_P (op2) && (REGNO (op2) == FPUL_REG))
- return true;
- /* r, f, y */
- if (REG_P (op1) && FP_REGISTER_P (REGNO (op1))
- && REG_P (op0) && GENERAL_REGISTER_P (REGNO (op0))
- && REG_P (op2) && (REGNO (op2) == FPUL_REG))
+ /* r, f */
+ if (REG_P (op1)
+ && (SUBREG_P (op0) && GET_MODE (SUBREG_REG (op0)) == SImode))
return true;
return false;
diff --git a/gcc/config/sh/sh.md b/gcc/config/sh/sh.md
index 6d93f5cb816b..c69eda36885f 100644
--- a/gcc/config/sh/sh.md
+++ b/gcc/config/sh/sh.md
@@ -5858,6 +5858,15 @@
[(set (match_dup 0) (match_dup 0))]
"")
+(define_split
+ [(set (match_operand:SF 0 "register_operand" "")
+ (match_operand:SF 1 "register_operand" ""))
+ (use (reg:SI FPSCR_MODES_REG))]
+ "TARGET_SH2E && sh_lra_p () && reload_completed
+ && true_regnum (operands[0]) == true_regnum (operands[1])"
+ [(set (match_dup 0) (match_dup 0))]
+ "")
+
;; fmovd substitute post-reload splits
(define_split
[(set (match_operand:DF 0 "register_operand" "")
@@ -6102,6 +6111,14 @@
prepare_move_operands (operands, DFmode);
if (TARGET_FPU_DOUBLE)
{
+ if (sh_lra_p ()
+ && (GET_CODE (operands[1]) == CONST_DOUBLE
+ && REG_P (operands[0])))
+ {
+ emit_insn (gen_movdf_i4_F_z (operands[0], operands[1]));
+ DONE;
+ }
+
emit_insn (gen_movdf_i4 (operands[0], operands[1]));
DONE;
}
@@ -6227,15 +6244,16 @@
(const_string "none")
(const_string "none")])])
-(define_insn_and_split "movsf_ie_ra"
+;; LRA will try to satisfy the constraints in match_scratch for the memory
+;; displacements and it will make issues on this target. movsf_ie is splitted
+;; into 4 patterns to avoid it when lra_in_progress is true.
+(define_insn "movsf_ie_ra"
[(set (match_operand:SF 0 "general_movdst_operand"
- "=f,r,f,f,fy,f,m, r,r,m,f,y,y,rf,r,y,<,y,y")
+ "=f,r,f,f,f,m, r,r,m,f,y,y,r,y,<,y,y")
(match_operand:SF 1 "general_movsrc_operand"
- " f,r,G,H,FQ,m,f,FQ,m,r,y,f,>,fr,y,r,y,>,y"))
- (use (reg:SI FPSCR_MODES_REG))
- (clobber (match_scratch:SF 2 "=r,r,X,X,&z,r,r, X,r,r,r,r,r, y,r,r,r,r,r"))
- (const_int 0)]
- "TARGET_SH2E
+ " f,r,G,H,m,f,FQ,m,r,y,f,>,y,r,y,>,y"))
+ (use (reg:SI FPSCR_MODES_REG))]
+ "TARGET_SH2E && sh_lra_p ()
&& (arith_reg_operand (operands[0], SFmode)
|| fpul_operand (operands[0], SFmode)
|| arith_reg_operand (operands[1], SFmode)
@@ -6245,7 +6263,6 @@
mov %1,%0
fldi0 %0
fldi1 %0
- #
fmov.s %1,%0
fmov.s %1,%0
mov.l %1,%0
@@ -6254,31 +6271,19 @@
fsts fpul,%0
flds %1,fpul
lds.l %1,%0
- #
sts %1,%0
lds %1,%0
sts.l %1,%0
lds.l %1,%0
! move optimized away"
- "reload_completed
- && sh_movsf_ie_ra_split_p (operands[0], operands[1], operands[2])"
- [(const_int 0)]
-{
- if (! rtx_equal_p (operands[0], operands[1]))
- {
- emit_insn (gen_movsf_ie (operands[2], operands[1]));
- emit_insn (gen_movsf_ie (operands[0], operands[2]));
- }
-}
- [(set_attr "type" "fmove,move,fmove,fmove,pcfload,fload,fstore,pcload,load,
- store,fmove,fmove,load,*,fpul_gp,gp_fpul,fstore,load,nil")
- (set_attr "late_fp_use" "*,*,*,*,*,*,yes,*,*,*,*,*,*,*,yes,*,yes,*,*")
+ [(set_attr "type" "fmove,move,fmove,fmove,fload,fstore,pcload,load,
+ store,fmove,fmove,load,fpul_gp,gp_fpul,fstore,load,nil")
+ (set_attr "late_fp_use" "*,*,*,*,*,yes,*,*,*,*,*,*,yes,*,yes,*,*")
(set_attr_alternative "length"
[(const_int 2)
(const_int 2)
(const_int 2)
(const_int 2)
- (const_int 4)
(if_then_else (match_operand 1 "displacement_mem_operand")
(const_int 4) (const_int 2))
(if_then_else (match_operand 0 "displacement_mem_operand")
@@ -6291,7 +6296,6 @@
(const_int 2)
(const_int 2)
(const_int 2)
- (const_int 4)
(const_int 2)
(const_int 2)
(const_int 2)
@@ -6303,7 +6307,6 @@
(const_string "none")
(const_string "single")
(const_string "single")
- (const_string "none")
(if_then_else (eq_attr "fmovd" "yes")
(const_string "single") (const_string "none"))
(if_then_else (eq_attr "fmovd" "yes")
@@ -6318,15 +6321,46 @@
(const_string "none")
(const_string "none")
(const_string "none")
- (const_string "none")
(const_string "none")])])
+(define_insn "movsf_ie_F_z"
+ [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
+ (match_operand:SF 1 "const_double_operand" "F"))
+ (use (reg:SI FPSCR_MODES_REG))
+ (clobber (reg:SI R0_REG))]
+ "TARGET_SH2E && sh_lra_p ()"
+ "#"
+ [(set_attr "type" "pcfload")
+ (set_attr "length" "4")])
+
+(define_insn "movsf_ie_Q_z"
+ [(set (match_operand:SF 0 "fpul_operand" "=y")
+ (match_operand:SF 1 "pc_relative_load_operand" "Q"))
+ (use (reg:SI FPSCR_MODES_REG))
+ (clobber (reg:SI R0_REG))]
+ "TARGET_SH2E && sh_lra_p ()"
+ "#"
+ [(set_attr "type" "pcfload")
+ (set_attr "length" "4")])
+
+(define_insn "movsf_ie_y"
+ [(set (match_operand:SF 0 "arith_reg_dest" "=fr")
+ (match_operand:SF 1 "arith_reg_operand" "rf"))
+ (use (reg:SI FPSCR_MODES_REG))
+ (clobber (reg:SI FPUL_REG))]
+ "TARGET_SH2E && sh_lra_p ()"
+ "#"
+ [(set_attr "type" "*")
+ (set_attr "length" "4")])
+
(define_split
[(set (match_operand:SF 0 "register_operand" "")
(match_operand:SF 1 "register_operand" ""))
(use (reg:SI FPSCR_MODES_REG))
(clobber (reg:SI FPUL_REG))]
- "TARGET_SH1"
+ "TARGET_SH1
+ && ! fpul_operand (operands[0], SFmode)
+ && ! fpul_operand (operands[1], SFmode)"
[(parallel [(set (reg:SF FPUL_REG) (match_dup 1))
(use (reg:SI FPSCR_MODES_REG))
(clobber (scratch:SI))])
@@ -6343,11 +6377,22 @@
prepare_move_operands (operands, SFmode);
if (TARGET_SH2E)
{
- if (lra_in_progress)
+ if (sh_lra_p ())
{
if (GET_CODE (operands[0]) == SCRATCH)
DONE;
- emit_insn (gen_movsf_ie_ra (operands[0], operands[1]));
+ if (GET_CODE (operands[1]) == CONST_DOUBLE
+ && ! satisfies_constraint_G (operands[1])
+ && ! satisfies_constraint_H (operands[1])
+ && REG_P (operands[0]))
+ emit_insn (gen_movsf_ie_F_z (operands[0], operands[1]));
+ else if ((REG_P (operands[0]) && REGNO (operands[0]) == FPUL_REG)
+ && satisfies_constraint_Q (operands[1]))
+ emit_insn (gen_movsf_ie_Q_z (operands[0], operands[1]));
+ else if (sh_movsf_ie_y_split_p (operands[0], operands[1]))
+ emit_insn (gen_movsf_ie_y (operands[0], operands[1]));
+ else
+ emit_insn (gen_movsf_ie_ra (operands[0], operands[1]));
DONE;
}
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