[gcc r15-3612] i386: Implement SAT_ADD for signed vector integers

[Uros Bizjak]

https://gcc.gnu.org/g:19d751601d012bbe31512d26f968e75873a408ab

commit r15-3612-g19d751601d012bbe31512d26f968e75873a408ab
Author: Uros Bizjak <ubizjak@gmail.com>
Date:   Thu Sep 12 20:34:28 2024 +0200

    i386: Implement SAT_ADD for signed vector integers
    
    Enable V4QI, V2QI and V2HI mode signed saturated arithmetic insn patterns
    and add a couple of testcases to test for PADDSB and PADDSW instructions.
    
            PR target/112600
    
    gcc/ChangeLog:
    
            * config/i386/mmx.md (<sat_plusminus:insn><mode>3): Rename
            from *<sat_plusminus:insn><mode>3.
    
    gcc/testsuite/ChangeLog:
    
            * gcc.target/i386/pr112600-3a.c: New test.
            * gcc.target/i386/pr112600-3b.c: New test.

Diff:
---
 gcc/config/i386/mmx.md                      |  2 +-
 gcc/testsuite/gcc.target/i386/pr112600-3a.c | 25 +++++++++++++++++++++++++
 gcc/testsuite/gcc.target/i386/pr112600-3b.c | 25 +++++++++++++++++++++++++
 3 files changed, 51 insertions(+), 1 deletion(-)

diff --git a/gcc/config/i386/mmx.md b/gcc/config/i386/mmx.md
index 2f8d958dd5f0..e88a06c441fa 100644
--- a/gcc/config/i386/mmx.md
+++ b/gcc/config/i386/mmx.md
@@ -3218,7 +3218,7 @@
    (set_attr "type" "mmxadd,sseadd,sseadd")
    (set_attr "mode" "DI,TI,TI")])
 
-(define_insn "*<insn><mode>3"
+(define_insn "<insn><mode>3"
   [(set (match_operand:VI_16_32 0 "register_operand" "=x,Yw")
         (sat_plusminus:VI_16_32
 	  (match_operand:VI_16_32 1 "register_operand" "<comm>0,Yw")
diff --git a/gcc/testsuite/gcc.target/i386/pr112600-3a.c b/gcc/testsuite/gcc.target/i386/pr112600-3a.c
new file mode 100644
index 000000000000..0c38659643da
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr112600-3a.c
@@ -0,0 +1,25 @@
+/* PR middle-end/112600 */
+/* { dg-do compile } */
+/* { dg-options "-O2 -ftree-vectorize -msse2" } */
+
+#define MIN -128
+#define MAX 127
+
+typedef char T;
+typedef unsigned char UT;
+
+void foo (T *out, T *op_1, T *op_2, int n)
+{
+  int i;
+
+  for (i = 0; i < n; i++)
+    {
+      T x = op_1[i];
+      T y = op_2[i];
+      T sum = (UT) x + (UT) y;
+
+      out[i] = (x ^ y) < 0 ? sum : (sum ^ x) >= 0 ? sum : x < 0 ? MIN : MAX;
+    }
+}
+
+/* { dg-final { scan-assembler "paddsb" } } */
diff --git a/gcc/testsuite/gcc.target/i386/pr112600-3b.c b/gcc/testsuite/gcc.target/i386/pr112600-3b.c
new file mode 100644
index 000000000000..746c422ceb94
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr112600-3b.c
@@ -0,0 +1,25 @@
+/* PR middle-end/112600 */
+/* { dg-do compile } */
+/* { dg-options "-O2 -ftree-vectorize -msse2" } */
+
+#define MIN -32768
+#define MAX 32767
+
+typedef short T;
+typedef unsigned short UT;
+
+void foo (T *out, T *op_1, T *op_2, int n)
+{
+  int i;
+
+  for (i = 0; i < n; i++)
+    {
+      T x = op_1[i];
+      T y = op_2[i];
+      T sum = (UT) x + (UT) y;
+
+      out[i] = (x ^ y) < 0 ? sum : (sum ^ x) >= 0 ? sum : x < 0 ? MIN : MAX;
+    }
+}
+
+/* { dg-final { scan-assembler "paddsw" } } */