[gcc r15-5655] nios2: Remove all support for Nios II target.
Sandra Loosemore
sandra@gcc.gnu.org
Mon Nov 25 18:08:20 GMT 2024
https://gcc.gnu.org/g:e876acab6cdd84bb2b32c98fc69fb0ba29c81153
commit r15-5655-ge876acab6cdd84bb2b32c98fc69fb0ba29c81153
Author: Sandra Loosemore <sloosemore@baylibre.com>
Date: Sat Nov 23 23:59:13 2024 +0000
nios2: Remove all support for Nios II target.
nios2 target support in GCC was deprecated in GCC 14 as the
architecture has been EOL'ed by the vendor. This patch removes the
entire port for GCC 15
There are still references to "nios2" in libffi and libgo. Since those
libraries are imported into the gcc sources from master copies maintained
by other projects, those will need to be addressed elsewhere.
ChangeLog:
* MAINTAINERS: Remove references to nios2.
* configure.ac: Likewise.
* configure: Regenerated.
config/ChangeLog:
* mt-nios2-elf: Deleted.
contrib/ChangeLog:
* config-list.mk: Remove references to Nios II.
gcc/ChangeLog:
* common/config/nios2/*: Delete entire directory.
* config/nios2/*: Delete entire directory.
* config.gcc: Remove references to nios2.
* configure.ac: Likewise.
* doc/extend.texi: Likewise.
* doc/install.texi: Likewise.
* doc/invoke.texi: Likewise.
* doc/md.texi: Likewise.
* regenerate-opt-urls.py: Likewise.
* config.in: Regenerated.
* configure: Regenerated.
gcc/testsuite/ChangeLog:
* g++.target/nios2/*: Delete entire directory.
* gcc.target/nios2/*: Delete entire directory.
* g++.dg/cpp0x/constexpr-rom.C: Remove refences to nios2.
* g++.old-deja/g++.jason/thunk3.C: Likewise.
* gcc.c-torture/execute/20101011-1.c: Likewise.
* gcc.c-torture/execute/pr47237.c: Likewise.
* gcc.dg/20020312-2.c: Likewise.
* gcc.dg/20021029-1.c: Likewise.
* gcc.dg/debug/btf/btf-datasec-1.c: Likewise.
* gcc.dg/ifcvt-4.c: Likewise.
* gcc.dg/stack-usage-1.c: Likewise.
* gcc.dg/struct-by-value-1.c: Likewise.
* gcc.dg/tree-ssa/reassoc-33.c: Likewise.
* gcc.dg/tree-ssa/reassoc-34.c: Likewise.
* gcc.dg/tree-ssa/reassoc-35.c: Likewise.
* gcc.dg/tree-ssa/reassoc-36.c: Likewise.
* lib/target-supports.exp: Likewise.
libgcc/ChangeLog:
* config/nios2/*: Delete entire directory.
* config.host: Remove refences to nios2.
* unwind-dw2-fde-dip.c: Likewise.
Diff:
---
MAINTAINERS | 2 -
config/mt-nios2-elf | 5 -
configure | 3 -
configure.ac | 3 -
contrib/config-list.mk | 2 -
gcc/common/config/nios2/nios2-common.cc | 43 -
gcc/config.gcc | 35 -
gcc/config.in | 6 -
gcc/config/nios2/constraints.md | 118 -
gcc/config/nios2/elf.h | 61 -
gcc/config/nios2/elf.opt | 38 -
gcc/config/nios2/elf.opt.urls | 14 -
gcc/config/nios2/ldstwm.md | 4190 ---------------
gcc/config/nios2/linux.h | 53 -
gcc/config/nios2/nios2-ldstwm.sml | 277 -
gcc/config/nios2/nios2-opts.h | 88 -
gcc/config/nios2/nios2-protos.h | 72 -
gcc/config/nios2/nios2.cc | 5630 --------------------
gcc/config/nios2/nios2.h | 540 --
gcc/config/nios2/nios2.md | 1311 -----
gcc/config/nios2/nios2.opt | 596 ---
gcc/config/nios2/nios2.opt.urls | 50 -
gcc/config/nios2/predicates.md | 161 -
gcc/config/nios2/rtems.h | 39 -
gcc/config/nios2/sync.md | 45 -
gcc/config/nios2/t-nios2 | 27 -
gcc/config/nios2/t-rtems | 23 -
gcc/configure | 44 +-
gcc/configure.ac | 18 +-
gcc/doc/extend.texi | 156 +-
gcc/doc/install.texi | 2 +-
gcc/doc/invoke.texi | 415 +-
gcc/doc/md.texi | 61 -
gcc/regenerate-opt-urls.py | 1 -
gcc/testsuite/g++.dg/cpp0x/constexpr-rom.C | 2 +-
gcc/testsuite/g++.old-deja/g++.jason/thunk3.C | 2 +-
gcc/testsuite/g++.target/nios2/hello-pie.C | 14 -
gcc/testsuite/g++.target/nios2/nios2.exp | 34 -
gcc/testsuite/gcc.c-torture/execute/20101011-1.c | 4 -
gcc/testsuite/gcc.c-torture/execute/pr47237.c | 2 +-
gcc/testsuite/gcc.dg/20020312-2.c | 2 -
gcc/testsuite/gcc.dg/20021029-1.c | 1 -
gcc/testsuite/gcc.dg/debug/btf/btf-datasec-1.c | 1 -
gcc/testsuite/gcc.dg/ifcvt-4.c | 2 +-
gcc/testsuite/gcc.dg/stack-usage-1.c | 2 -
gcc/testsuite/gcc.dg/struct-by-value-1.c | 1 -
gcc/testsuite/gcc.dg/tree-ssa/reassoc-33.c | 2 +-
gcc/testsuite/gcc.dg/tree-ssa/reassoc-34.c | 2 +-
gcc/testsuite/gcc.dg/tree-ssa/reassoc-35.c | 2 +-
gcc/testsuite/gcc.dg/tree-ssa/reassoc-36.c | 2 +-
gcc/testsuite/gcc.target/nios2/andci.c | 18 -
gcc/testsuite/gcc.target/nios2/biggot-1.c | 67 -
gcc/testsuite/gcc.target/nios2/biggot-2.c | 68 -
gcc/testsuite/gcc.target/nios2/bmx.c | 29 -
gcc/testsuite/gcc.target/nios2/cdx-add.c | 24 -
gcc/testsuite/gcc.target/nios2/cdx-branch.c | 44 -
gcc/testsuite/gcc.target/nios2/cdx-callret.c | 25 -
gcc/testsuite/gcc.target/nios2/cdx-ldstwm-1.c | 24 -
gcc/testsuite/gcc.target/nios2/cdx-ldstwm-2.c | 69 -
gcc/testsuite/gcc.target/nios2/cdx-loadstore.c | 61 -
gcc/testsuite/gcc.target/nios2/cdx-logical.c | 43 -
gcc/testsuite/gcc.target/nios2/cdx-mov.c | 20 -
gcc/testsuite/gcc.target/nios2/cdx-shift.c | 32 -
gcc/testsuite/gcc.target/nios2/cdx-sub.c | 23 -
gcc/testsuite/gcc.target/nios2/const-addr-1.c | 19 -
gcc/testsuite/gcc.target/nios2/const-addr-2.c | 18 -
gcc/testsuite/gcc.target/nios2/const-addr-3.c | 20 -
gcc/testsuite/gcc.target/nios2/custom-fp-1.c | 22 -
gcc/testsuite/gcc.target/nios2/custom-fp-2.c | 26 -
gcc/testsuite/gcc.target/nios2/custom-fp-2b.c | 26 -
gcc/testsuite/gcc.target/nios2/custom-fp-3.c | 26 -
gcc/testsuite/gcc.target/nios2/custom-fp-4.c | 29 -
gcc/testsuite/gcc.target/nios2/custom-fp-5.c | 26 -
gcc/testsuite/gcc.target/nios2/custom-fp-6.c | 30 -
gcc/testsuite/gcc.target/nios2/custom-fp-7.c | 33 -
gcc/testsuite/gcc.target/nios2/custom-fp-8.c | 24 -
gcc/testsuite/gcc.target/nios2/custom-fp-cmp-1.c | 53 -
.../gcc.target/nios2/custom-fp-conversion.c | 72 -
gcc/testsuite/gcc.target/nios2/custom-fp-double.c | 86 -
gcc/testsuite/gcc.target/nios2/custom-fp-float.c | 80 -
.../gcc.target/nios2/custom-fp-inline-1.c | 33 -
.../gcc.target/nios2/custom-fp-inline-2.c | 29 -
.../gcc.target/nios2/custom-fp-inline-3.c | 33 -
.../gcc.target/nios2/custom-fp-inline-4.c | 29 -
gcc/testsuite/gcc.target/nios2/custom-fp-lto.c | 28 -
gcc/testsuite/gcc.target/nios2/gpopt-all.c | 38 -
gcc/testsuite/gcc.target/nios2/gpopt-data.c | 38 -
gcc/testsuite/gcc.target/nios2/gpopt-global.c | 38 -
gcc/testsuite/gcc.target/nios2/gpopt-gprel-sec.c | 38 -
gcc/testsuite/gcc.target/nios2/gpopt-local.c | 38 -
gcc/testsuite/gcc.target/nios2/gpopt-none.c | 38 -
gcc/testsuite/gcc.target/nios2/gpopt-r0rel-sec.c | 38 -
gcc/testsuite/gcc.target/nios2/gprel-offset.c | 20 -
gcc/testsuite/gcc.target/nios2/lo-addr-bypass.c | 40 -
gcc/testsuite/gcc.target/nios2/lo-addr-char.c | 60 -
gcc/testsuite/gcc.target/nios2/lo-addr-int.c | 40 -
gcc/testsuite/gcc.target/nios2/lo-addr-pic.c | 38 -
gcc/testsuite/gcc.target/nios2/lo-addr-short.c | 51 -
gcc/testsuite/gcc.target/nios2/lo-addr-tls.c | 38 -
gcc/testsuite/gcc.target/nios2/lo-addr-uchar.c | 58 -
gcc/testsuite/gcc.target/nios2/lo-addr-ushort.c | 49 -
gcc/testsuite/gcc.target/nios2/lo-addr-volatile.c | 41 -
.../gcc.target/nios2/nios2-ashlsi3-one_shift.c | 10 -
.../gcc.target/nios2/nios2-builtin-custom.c | 9 -
gcc/testsuite/gcc.target/nios2/nios2-builtin-io.c | 26 -
gcc/testsuite/gcc.target/nios2/nios2-cache-1.c | 21 -
gcc/testsuite/gcc.target/nios2/nios2-cache-2.c | 21 -
gcc/testsuite/gcc.target/nios2/nios2-custom-1.c | 64 -
gcc/testsuite/gcc.target/nios2/nios2-custom-2.c | 7 -
gcc/testsuite/gcc.target/nios2/nios2-flushd.c | 22 -
gcc/testsuite/gcc.target/nios2/nios2-int-types.c | 34 -
gcc/testsuite/gcc.target/nios2/nios2-ldxio.c | 52 -
.../gcc.target/nios2/nios2-mul-options-1.c | 11 -
.../gcc.target/nios2/nios2-mul-options-2.c | 11 -
.../gcc.target/nios2/nios2-mul-options-3.c | 11 -
.../gcc.target/nios2/nios2-mul-options-4.c | 11 -
gcc/testsuite/gcc.target/nios2/nios2-nor.c | 8 -
gcc/testsuite/gcc.target/nios2/nios2-rdctl.c | 8 -
gcc/testsuite/gcc.target/nios2/nios2-rdprs.c | 8 -
gcc/testsuite/gcc.target/nios2/nios2-rdwrctl-1.c | 14 -
.../gcc.target/nios2/nios2-stack-check-1.c | 10 -
.../gcc.target/nios2/nios2-stack-check-2.c | 9 -
.../gcc.target/nios2/nios2-stack-check-3.c | 12 -
gcc/testsuite/gcc.target/nios2/nios2-stxio.c | 33 -
gcc/testsuite/gcc.target/nios2/nios2-trap-insn.c | 7 -
.../gcc.target/nios2/nios2-wrctl-not-zero.c | 7 -
gcc/testsuite/gcc.target/nios2/nios2-wrctl-zero.c | 7 -
gcc/testsuite/gcc.target/nios2/nios2-wrctl.c | 7 -
gcc/testsuite/gcc.target/nios2/nios2.exp | 41 -
gcc/testsuite/gcc.target/nios2/pr87079-1.c | 34 -
gcc/testsuite/gcc.target/nios2/pr87079-2.c | 34 -
gcc/testsuite/gcc.target/nios2/pr92499-1.c | 48 -
gcc/testsuite/gcc.target/nios2/pr92499-2.c | 45 -
gcc/testsuite/gcc.target/nios2/pr92499-3.c | 23 -
gcc/testsuite/gcc.target/nios2/r2-atomic.c | 49 -
gcc/testsuite/gcc.target/nios2/r2-eni.c | 10 -
gcc/testsuite/gcc.target/nios2/r2-io-range.c | 18 -
gcc/testsuite/gcc.target/nios2/r2-stio-1.c | 19 -
gcc/testsuite/gcc.target/nios2/r2-stio-2.c | 19 -
gcc/testsuite/gcc.target/nios2/r2-wrpie.c | 14 -
gcc/testsuite/lib/target-supports.exp | 1 -
libgcc/config.host | 12 -
libgcc/config/nios2/crti.S | 85 -
libgcc/config/nios2/crtn.S | 56 -
libgcc/config/nios2/elf-lib.h | 24 -
libgcc/config/nios2/lib2-divmod-hi.c | 117 -
libgcc/config/nios2/lib2-divmod.c | 117 -
libgcc/config/nios2/lib2-divtable.c | 60 -
libgcc/config/nios2/lib2-mul.c | 42 -
libgcc/config/nios2/lib2-nios2.h | 49 -
libgcc/config/nios2/linux-atomic.c | 279 -
libgcc/config/nios2/linux-unwind.h | 105 -
libgcc/config/nios2/sfp-machine.h | 81 -
libgcc/config/nios2/t-linux | 7 -
libgcc/config/nios2/t-nios2 | 8 -
libgcc/config/nios2/tramp.c | 75 -
libgcc/unwind-dw2-fde-dip.c | 7 +-
157 files changed, 18 insertions(+), 18095 deletions(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index e432b2a4da9c..26455d1cabfa 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -102,8 +102,6 @@ moxie port Anthony Green <green@moxielogic.com>
msp430 port Nick Clifton <nickc@redhat.com>
nds32 port Chung-Ju Wu <jasonwucj@gmail.com>
nds32 port Shiva Chen <shiva0217@gmail.com>
-nios2 port Chung-Lin Tang <cltang@baylibre.com>
-nios2 port Sandra Loosemore <sloosemore@baylibre.com>
nvptx port Tom de Vries <tdevries@suse.de>
nvptx port Thomas Schwinge <tschwinge@baylibre.com>
or1k port Stafford Horne <shorne@gmail.com>
diff --git a/config/mt-nios2-elf b/config/mt-nios2-elf
deleted file mode 100644
index 1dee7c6439ee..000000000000
--- a/config/mt-nios2-elf
+++ /dev/null
@@ -1,5 +0,0 @@
-# We build library code with -mno-gpopt so that it can be linked with
-# larger executables with small-data sections that exceed the 16-bit
-# offset range for GP-relative addressing.
-CFLAGS_FOR_TARGET += -mno-gpopt
-CXXFLAGS_FOR_TARGET += -mno-gpopt
diff --git a/configure b/configure
index c6796040fd8a..52578050d61d 100755
--- a/configure
+++ b/configure
@@ -10742,9 +10742,6 @@ case "${target}" in
mips*-*-*linux* | mips*-*-gnu*)
target_makefile_frag="config/mt-mips-gnu"
;;
- nios2-*-elf*)
- target_makefile_frag="config/mt-nios2-elf"
- ;;
*-*-linux-android*)
target_makefile_frag="config/mt-android"
;;
diff --git a/configure.ac b/configure.ac
index a8d13b31ee2e..088ceaac0d41 100644
--- a/configure.ac
+++ b/configure.ac
@@ -2978,9 +2978,6 @@ case "${target}" in
mips*-*-*linux* | mips*-*-gnu*)
target_makefile_frag="config/mt-mips-gnu"
;;
- nios2-*-elf*)
- target_makefile_frag="config/mt-nios2-elf"
- ;;
*-*-linux-android*)
target_makefile_frag="config/mt-android"
;;
diff --git a/contrib/config-list.mk b/contrib/config-list.mk
index 4ddb3eeab124..fc9fc9902bff 100644
--- a/contrib/config-list.mk
+++ b/contrib/config-list.mk
@@ -78,8 +78,6 @@ LIST = \
moxie-uclinux moxie-rtems \
msp430-elf msp430-elfbare \
nds32le-elf nds32be-elf \
- nios2-elfOPT-enable-obsolete nios2-linux-gnuOPT-enable-obsolete \
- nios2-rtemsOPT-enable-obsolete \
nvptx-none \
or1k-elf or1k-linux-uclibc or1k-linux-musl or1k-rtems \
pdp11-aout \
diff --git a/gcc/common/config/nios2/nios2-common.cc b/gcc/common/config/nios2/nios2-common.cc
deleted file mode 100644
index dc0335aa5cd4..000000000000
--- a/gcc/common/config/nios2/nios2-common.cc
+++ /dev/null
@@ -1,43 +0,0 @@
-/* Common hooks for Altera Nios II.
- Copyright (C) 2012-2024 Free Software Foundation, Inc.
-
-This file is part of GCC.
-
-GCC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 3, or (at your option)
-any later version.
-
-GCC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GCC; see the file COPYING3. If not see
-<http://www.gnu.org/licenses/>. */
-
-#include "config.h"
-#include "system.h"
-#include "coretypes.h"
-#include "diagnostic-core.h"
-#include "tm.h"
-#include "common/common-target.h"
-#include "common/common-target-def.h"
-#include "opts.h"
-#include "flags.h"
-
-/* Implement TARGET_OPTION_OPTIMIZATION_TABLE. */
-static const struct default_options nios2_option_optimization_table[] =
- {
- { OPT_LEVELS_3_PLUS, OPT_mfast_sw_div, NULL, 1 },
- { OPT_LEVELS_NONE, 0, NULL, 0 }
- };
-
-#undef TARGET_DEFAULT_TARGET_FLAGS
-#define TARGET_DEFAULT_TARGET_FLAGS TARGET_DEFAULT
-
-#undef TARGET_OPTION_OPTIMIZATION_TABLE
-#define TARGET_OPTION_OPTIMIZATION_TABLE nios2_option_optimization_table
-
-struct gcc_targetm_common targetm_common = TARGETM_COMMON_INITIALIZER;
diff --git a/gcc/config.gcc b/gcc/config.gcc
index c20817487457..12018d2193ca 100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -273,7 +273,6 @@ esac
# Obsolete configurations.
case ${target} in
ia64*-*-hpux* | ia64*-*-*vms* | ia64*-*-elf* \
- | nios2*-*-* \
)
if test "x$enable_obsolete" != xyes; then
echo "*** Configuration ${target} is obsolete." >&2
@@ -514,10 +513,6 @@ nds32*)
esac
extra_objs="nds32-cost.o nds32-intrinsic.o nds32-isr.o nds32-md-auxiliary.o nds32-pipelines-auxiliary.o nds32-predicates.o nds32-memory-manipulation.o nds32-fp-as-gp.o nds32-relax-opt.o nds32-utils.o"
;;
-nios2-*-*)
- cpu_type=nios2
- extra_options="${extra_options} g.opt"
- ;;
nvptx-*-*)
cpu_type=nvptx
c_target_objs="nvptx-c.o"
@@ -2913,23 +2908,6 @@ nds32*-*-*)
tm_defines="${tm_defines} TARGET_DEFAULT_EXT_DSP=1"
fi
;;
-nios2-*-*)
- tm_file="elfos.h ${tm_file}"
- tmake_file="${tmake_file} nios2/t-nios2"
- case ${target} in
- nios2-*-linux*)
- tm_file="${tm_file} gnu-user.h linux.h glibc-stdint.h nios2/linux.h "
- ;;
- nios2-*-elf*)
- tm_file="${tm_file} newlib-stdint.h nios2/elf.h"
- extra_options="${extra_options} nios2/elf.opt"
- ;;
- nios2-*-rtems*)
- tm_file="${tm_file} newlib-stdint.h nios2/rtems.h rtems.h"
- tmake_file="${tmake_file} t-rtems nios2/t-rtems"
- ;;
- esac
- ;;
nvptx-*)
tm_file="${tm_file} newlib-stdint.h"
use_gcc_stdint=wrap
@@ -5596,19 +5574,6 @@ case "${target}" in
;;
- nios2*-*-*)
- supported_defaults="arch"
- case "$with_arch" in
- "" | r1 | r2)
- # OK
- ;;
- *)
- echo "Unknown arch used in --with-arch=$with_arch" 1>&2
- exit 1
- ;;
- esac
- ;;
-
nvptx-*)
supported_defaults=arch
TM_MULTILIB_CONFIG=$with_arch
diff --git a/gcc/config.in b/gcc/config.in
index 0a506d1783a4..972c0c2034dc 100644
--- a/gcc/config.in
+++ b/gcc/config.in
@@ -689,12 +689,6 @@
#endif
-/* Define if your assembler supports %gotoff relocation syntax. */
-#ifndef USED_FOR_TARGET
-#undef HAVE_AS_NIOS2_GOTOFF_RELOCATION
-#endif
-
-
/* Define if your assembler supports the -no-mul-bug-abort option. */
#ifndef USED_FOR_TARGET
#undef HAVE_AS_NO_MUL_BUG_ABORT_OPTION
diff --git a/gcc/config/nios2/constraints.md b/gcc/config/nios2/constraints.md
deleted file mode 100644
index edabb46d3058..000000000000
--- a/gcc/config/nios2/constraints.md
+++ /dev/null
@@ -1,118 +0,0 @@
-;; Constraint definitions for Altera Nios II.
-;; Copyright (C) 2012-2024 Free Software Foundation, Inc.
-;; Contributed by Chung-Lin Tang <cltang@codesourcery.com>
-;;
-;; This file is part of GCC.
-;;
-;; GCC is free software; you can redistribute it and/or modify
-;; it under the terms of the GNU General Public License as published by
-;; the Free Software Foundation; either version 3, or (at your option)
-;; any later version.
-;;
-;; GCC is distributed in the hope that it will be useful,
-;; but WITHOUT ANY WARRANTY; without even the implied warranty of
-;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-;; GNU General Public License for more details.
-;;
-;; You should have received a copy of the GNU General Public License
-;; along with GCC; see the file COPYING3. If not see
-;; <http://www.gnu.org/licenses/>.
-
-;; We use the following constraint letters for constants
-;;
-;; I: -32768 to 32767
-;; J: 0 to 65535
-;; K: $nnnn0000 for some nnnn
-;; P: Under R2, $nnnnffff or $ffffnnnn for some nnnn
-;; L: 0 to 31 (for shift counts)
-;; M: 0
-;; N: 0 to 255 (for custom instruction numbers)
-;; O: 0 to 31 (for control register numbers)
-;; U: -32768 to 32767 under R1, -2048 to 2047 under R2
-;;
-;; We use the following constraint letters for memory constraints
-;;
-;; v: memory operands for R2 load/store exclusive instructions
-;; w: memory operands for load/store IO and cache instructions
-;;
-;; We use the following built-in register classes:
-;;
-;; r: general purpose register (r0..r31)
-;; m: memory operand
-;;
-;; Plus, we define the following constraint strings:
-;;
-;; S: symbol that is in the "small data" area
-
-;; Register constraints
-
-(define_register_constraint "c" "IJMP_REGS"
- "A register suitable for an indirect jump.")
-
-(define_register_constraint "j" "SIB_REGS"
- "A register suitable for an indirect sibcall.")
-
-;; Integer constraints
-
-(define_constraint "I"
- "A signed 16-bit constant (for arithmetic instructions)."
- (and (match_code "const_int")
- (match_test "SMALL_INT (ival)")))
-
-(define_constraint "J"
- "An unsigned 16-bit constant (for logical instructions)."
- (and (match_code "const_int")
- (match_test "SMALL_INT_UNSIGNED (ival)")))
-
-(define_constraint "K"
- "An unsigned 16-bit high constant (for logical instructions)."
- (and (match_code "const_int")
- (match_test "UPPER16_INT (ival)")))
-
-(define_constraint "L"
- "An unsigned 5-bit constant (for shift counts)."
- (and (match_code "const_int")
- (match_test "ival >= 0 && ival <= 31")))
-
-(define_constraint "M"
- "Integer zero."
- (and (match_code "const_int")
- (match_test "ival == 0")))
-
-(define_constraint "N"
- "An unsigned 8-bit constant (for custom instruction codes)."
- (and (match_code "const_int")
- (match_test "ival >= 0 && ival <= 255")))
-
-(define_constraint "O"
- "An unsigned 5-bit constant (for control register numbers)."
- (and (match_code "const_int")
- (match_test "ival >= 0 && ival <= 31")))
-
-(define_constraint "P"
- "An immediate operand for R2 andchi/andci instructions."
- (and (match_code "const_int")
- (match_test "TARGET_ARCH_R2 && ANDCLEAR_INT (ival)")))
-
-(define_constraint "S"
- "An immediate stored in small data, accessible by GP, or by offset from r0."
- (match_test "gprel_constant_p (op) || r0rel_constant_p (op)"))
-
-(define_constraint "T"
- "A constant unspec offset representing a relocation."
- (match_test "nios2_unspec_reloc_p (op)"))
-
-(define_constraint "U"
- "A 12-bit or 16-bit constant (for RDPRS and DCACHE)."
- (and (match_code "const_int")
- (if_then_else (match_test "TARGET_ARCH_R2")
- (match_test "SMALL_INT12 (ival)")
- (match_test "SMALL_INT (ival)"))))
-
-(define_memory_constraint "v"
- "A memory operand suitable for R2 load/store exclusive instructions."
- (match_operand 0 "ldstex_memory_operand"))
-
-(define_memory_constraint "w"
- "A memory operand suitable for load/store IO and cache instructions."
- (match_operand 0 "ldstio_memory_operand"))
diff --git a/gcc/config/nios2/elf.h b/gcc/config/nios2/elf.h
deleted file mode 100644
index 3efcdcf36525..000000000000
--- a/gcc/config/nios2/elf.h
+++ /dev/null
@@ -1,61 +0,0 @@
-/* Definitions of ELF target support for Altera Nios II.
- Copyright (C) 2012-2024 Free Software Foundation, Inc.
- Contributed by Jonah Graham (jgraham@altera.com),
- Will Reece (wreece@altera.com), and Jeff DaSilva (jdasilva@altera.com).
- Contributed by Mentor Graphics, Inc.
-
- This file is part of GCC.
-
- GCC is free software; you can redistribute it and/or modify it
- under the terms of the GNU General Public License as published
- by the Free Software Foundation; either version 3, or (at your
- option) any later version.
-
- GCC is distributed in the hope that it will be useful, but WITHOUT
- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
- License for more details.
-
- You should have received a copy of the GNU General Public License
- along with GCC; see the file COPYING3. If not see
- <http://www.gnu.org/licenses/>. */
-
-
-/* Specs to support the additional command-line options for Nios II ELF
- toolchains. */
-
-/* -msmallc chooses an alternate C library.
- -msys-lib= specifies an additional low-level system/hosting library and
- is typically used to suck in a library provided by a HAL BSP. */
-#undef LIB_SPEC
-#define LIB_SPEC \
-"--start-group %{msmallc: -lsmallc} %{!msmallc: -lc} -lgcc \
- %{msys-lib=*: -l%*} \
- --end-group \
-"
-
-/* Linking with -mhal suppresses inclusion of the GCC-provided crt* begin/end
- code. Normally in this case you also link with -msys-crt0= to specify
- the startup code provided by the HAL BSP instead. */
-#undef STARTFILE_SPEC
-#define STARTFILE_SPEC \
- "%{mhal:" \
- "%{msys-crt0=*:%*} %{!msys-crt0=*:crt0%O%s} " \
- "%{msys-crt0=:%eYou need a C startup file for -msys-crt0=};" \
- ":crti%O%s crtbegin%O%s}"
-
-#undef ENDFILE_SPEC
-#define ENDFILE_SPEC "%{!mhal:crtend%O%s crtn%O%s}"
-
-/* The ELF target doesn't support the Nios II Linux ABI. */
-#define TARGET_LINUX_ABI 0
-
-/* Default -fdelete-null-pointer-checks to off, to prevent the compiler
- from treating accesses to address zero as traps. On bare-metal Nios II
- targets address zero may legitimately be mapped to memory (e.g., the
- hardware description may specify this as the address of the interrupt
- vector). Users can override this on the command line to get the
- additional optimizations it enables. */
-#define SUBTARGET_OVERRIDE_OPTIONS \
- if (flag_delete_null_pointer_checks < 0) \
- flag_delete_null_pointer_checks = 0
diff --git a/gcc/config/nios2/elf.opt b/gcc/config/nios2/elf.opt
deleted file mode 100644
index 91af4fa3a699..000000000000
--- a/gcc/config/nios2/elf.opt
+++ /dev/null
@@ -1,38 +0,0 @@
-; Options for the Altera Nios II port of the compiler.
-; Copyright (C) 2012-2024 Free Software Foundation, Inc.
-; Contributed by Altera and Mentor Graphics, Inc.
-;
-; This file is part of GCC.
-;
-; GCC is free software; you can redistribute it and/or modify
-; it under the terms of the GNU General Public License as published by
-; the Free Software Foundation; either version 3, or (at your option)
-; any later version.
-;
-; GCC is distributed in the hope that it will be useful,
-; but WITHOUT ANY WARRANTY; without even the implied warranty of
-; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-; GNU General Public License for more details.
-;
-; You should have received a copy of the GNU General Public License
-; along with GCC; see the file COPYING3. If not see
-; <http://www.gnu.org/licenses/>.
-
-; These additional options are supported for ELF (bare-metal) Nios II
-; toolchains.
-
-msmallc
-Target RejectNegative
-Link with a limited version of the C library.
-
-msys-lib=
-Target RejectNegative Joined Var(nios2_sys_lib_string)
-Name of system library to link against.
-
-msys-crt0=
-Target RejectNegative Joined Var(nios2_sys_crt0_string)
-Name of the startfile.
-
-mhal
-Target RejectNegative
-Link with HAL BSP.
diff --git a/gcc/config/nios2/elf.opt.urls b/gcc/config/nios2/elf.opt.urls
deleted file mode 100644
index 1367c6ba50cf..000000000000
--- a/gcc/config/nios2/elf.opt.urls
+++ /dev/null
@@ -1,14 +0,0 @@
-; Autogenerated by regenerate-opt-urls.py from gcc/config/nios2/elf.opt and generated HTML
-
-msmallc
-UrlSuffix(gcc/Nios-II-Options.html#index-msmallc)
-
-msys-lib=
-UrlSuffix(gcc/Nios-II-Options.html#index-msys-lib)
-
-msys-crt0=
-UrlSuffix(gcc/Nios-II-Options.html#index-msys-crt0)
-
-mhal
-UrlSuffix(gcc/Nios-II-Options.html#index-mhal)
-
diff --git a/gcc/config/nios2/ldstwm.md b/gcc/config/nios2/ldstwm.md
deleted file mode 100644
index 1aeea6b86f85..000000000000
--- a/gcc/config/nios2/ldstwm.md
+++ /dev/null
@@ -1,4190 +0,0 @@
-/* Nios II R2 CDX ldwm/stwm/push.h/pop.n instruction patterns.
- This file was automatically generated using nios2-ldstwm.sml.
- Please do not edit manually.
-
- Copyright (C) 2014-2024 Free Software Foundation, Inc.
- Contributed by Mentor Graphics.
-
- This file is part of GCC.
-
- GCC is free software; you can redistribute it and/or modify it
- under the terms of the GNU General Public License as published
- by the Free Software Foundation; either version 3, or (at your
- option) any later version.
-
- GCC is distributed in the hope that it will be useful, but WITHOUT
- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
- License for more details.
-
- You should have received a copy of the GNU General Public License and
- a copy of the GCC Runtime Library Exception along with this program;
- see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
- <http://www.gnu.org/licenses/>. */
-
-(define_insn "*cdx_push_ra_fp"
- [(match_parallel 0 ""
- [(set (reg:SI SP_REGNO)
- (plus:SI (reg:SI SP_REGNO) (match_operand 1 "const_int_operand" "")))
- (set (mem:SI (plus:SI (reg:SI SP_REGNO) (const_int -4))) (reg:SI RA_REGNO))
- (set (mem:SI (plus:SI (reg:SI SP_REGNO) (const_int -8))) (reg:SI FP_REGNO))])]
- "TARGET_HAS_CDX && XVECLEN (operands[0], 0) == 3
- && (-INTVAL (operands[1]) & 3) == 0
- && (-INTVAL (operands[1]) - 8) <= 60"
-{
- operands[2] = GEN_INT (-INTVAL (operands[1]) - 8);
- return "push.n\\t{ra, fp}, %2";
-}
- [(set_attr "type" "push")])
-
-(define_insn "*cdx_push_ra"
- [(match_parallel 0 ""
- [(set (reg:SI SP_REGNO)
- (plus:SI (reg:SI SP_REGNO) (match_operand 1 "const_int_operand" "")))
- (set (mem:SI (plus:SI (reg:SI SP_REGNO) (const_int -4))) (reg:SI RA_REGNO))])]
- "TARGET_HAS_CDX && XVECLEN (operands[0], 0) == 2
- && (-INTVAL (operands[1]) & 3) == 0
- && (-INTVAL (operands[1]) - 4) <= 60"
-{
- operands[2] = GEN_INT (-INTVAL (operands[1]) - 4);
- return "push.n\\t{ra}, %2";
-}
- [(set_attr "type" "push")])
-
-(define_insn "*cdx_pop_fp_ra"
- [(match_parallel 0 "pop_operation"
- [(return)
- (set (reg:SI SP_REGNO)
- (plus:SI (reg:SI SP_REGNO) (match_operand 1 "const_int_operand" "")))
- (set (reg:SI RA_REGNO) (match_operand:SI 2 "stack_memory_operand" ""))
- (set (reg:SI FP_REGNO) (match_operand:SI 3 "stack_memory_operand" ""))])]
- "TARGET_HAS_CDX && XVECLEN (operands[0], 0) == 4"
-{
- rtx x = XEXP (operands[3], 0);
- operands[3] = REG_P (x) ? const0_rtx : XEXP (x, 1);
- return "pop.n\\t{fp, ra}, %3";
-}
- [(set_attr "type" "pop")])
-
-(define_insn "*cdx_pop_ra"
- [(match_parallel 0 "pop_operation"
- [(return)
- (set (reg:SI SP_REGNO)
- (plus:SI (reg:SI SP_REGNO) (match_operand 1 "const_int_operand" "")))
- (set (reg:SI RA_REGNO) (match_operand:SI 2 "stack_memory_operand" ""))])]
- "TARGET_HAS_CDX && XVECLEN (operands[0], 0) == 3"
-{
- rtx x = XEXP (operands[2], 0);
- operands[2] = REG_P (x) ? const0_rtx : XEXP (x, 1);
- return "pop.n\\t{ra}, %2";
-}
- [(set_attr "type" "pop")])
-
-(define_insn "*cdx_push_ra_fp_r16"
- [(match_parallel 0 ""
- [(set (reg:SI SP_REGNO)
- (plus:SI (reg:SI SP_REGNO) (match_operand 1 "const_int_operand" "")))
- (set (mem:SI (plus:SI (reg:SI SP_REGNO) (const_int -4))) (reg:SI RA_REGNO))
- (set (mem:SI (plus:SI (reg:SI SP_REGNO) (const_int -8))) (reg:SI FP_REGNO))
- (set (mem:SI (plus:SI (reg:SI SP_REGNO) (const_int -12))) (reg:SI 16))])]
- "TARGET_HAS_CDX && XVECLEN (operands[0], 0) == 4
- && (-INTVAL (operands[1]) & 3) == 0
- && (-INTVAL (operands[1]) - 12) <= 60"
-{
- operands[2] = GEN_INT (-INTVAL (operands[1]) - 12);
- return "push.n\\t{ra, fp, r16}, %2";
-}
- [(set_attr "type" "push")])
-
-(define_insn "*cdx_push_ra_r16"
- [(match_parallel 0 ""
- [(set (reg:SI SP_REGNO)
- (plus:SI (reg:SI SP_REGNO) (match_operand 1 "const_int_operand" "")))
- (set (mem:SI (plus:SI (reg:SI SP_REGNO) (const_int -4))) (reg:SI RA_REGNO))
- (set (mem:SI (plus:SI (reg:SI SP_REGNO) (const_int -8))) (reg:SI 16))])]
- "TARGET_HAS_CDX && XVECLEN (operands[0], 0) == 3
- && (-INTVAL (operands[1]) & 3) == 0
- && (-INTVAL (operands[1]) - 8) <= 60"
-{
- operands[2] = GEN_INT (-INTVAL (operands[1]) - 8);
- return "push.n\\t{ra, r16}, %2";
-}
- [(set_attr "type" "push")])
-
-(define_insn "*cdx_pop_r16_fp_ra"
- [(match_parallel 0 "pop_operation"
- [(return)
- (set (reg:SI SP_REGNO)
- (plus:SI (reg:SI SP_REGNO) (match_operand 1 "const_int_operand" "")))
- (set (reg:SI RA_REGNO) (match_operand:SI 2 "stack_memory_operand" ""))
- (set (reg:SI FP_REGNO) (match_operand:SI 3 "stack_memory_operand" ""))
- (set (reg:SI 16) (match_operand:SI 4 "stack_memory_operand" ""))])]
- "TARGET_HAS_CDX && XVECLEN (operands[0], 0) == 5"
-{
- rtx x = XEXP (operands[4], 0);
- operands[4] = REG_P (x) ? const0_rtx : XEXP (x, 1);
- return "pop.n\\t{r16, fp, ra}, %4";
-}
- [(set_attr "type" "pop")])
-
-(define_insn "*cdx_pop_r16_ra"
- [(match_parallel 0 "pop_operation"
- [(return)
- (set (reg:SI SP_REGNO)
- (plus:SI (reg:SI SP_REGNO) (match_operand 1 "const_int_operand" "")))
- (set (reg:SI RA_REGNO) (match_operand:SI 2 "stack_memory_operand" ""))
- (set (reg:SI 16) (match_operand:SI 3 "stack_memory_operand" ""))])]
- "TARGET_HAS_CDX && XVECLEN (operands[0], 0) == 4"
-{
- rtx x = XEXP (operands[3], 0);
- operands[3] = REG_P (x) ? const0_rtx : XEXP (x, 1);
- return "pop.n\\t{r16, ra}, %3";
-}
- [(set_attr "type" "pop")])
-
-(define_insn "*cdx_push_ra_fp_r17_r16"
- [(match_parallel 0 ""
- [(set (reg:SI SP_REGNO)
- (plus:SI (reg:SI SP_REGNO) (match_operand 1 "const_int_operand" "")))
- (set (mem:SI (plus:SI (reg:SI SP_REGNO) (const_int -4))) (reg:SI RA_REGNO))
- (set (mem:SI (plus:SI (reg:SI SP_REGNO) (const_int -8))) (reg:SI FP_REGNO))
- (set (mem:SI (plus:SI (reg:SI SP_REGNO) (const_int -12))) (reg:SI 17))
- (set (mem:SI (plus:SI (reg:SI SP_REGNO) (const_int -16))) (reg:SI 16))])]
- "TARGET_HAS_CDX && XVECLEN (operands[0], 0) == 5
- && (-INTVAL (operands[1]) & 3) == 0
- && (-INTVAL (operands[1]) - 16) <= 60"
-{
- operands[2] = GEN_INT (-INTVAL (operands[1]) - 16);
- return "push.n\\t{ra, fp, r17, r16}, %2";
-}
- [(set_attr "type" "push")])
-
-(define_insn "*cdx_push_ra_r17_r16"
- [(match_parallel 0 ""
- [(set (reg:SI SP_REGNO)
- (plus:SI (reg:SI SP_REGNO) (match_operand 1 "const_int_operand" "")))
- (set (mem:SI (plus:SI (reg:SI SP_REGNO) (const_int -4))) (reg:SI RA_REGNO))
- (set (mem:SI (plus:SI (reg:SI SP_REGNO) (const_int -8))) (reg:SI 17))
- (set (mem:SI (plus:SI (reg:SI SP_REGNO) (const_int -12))) (reg:SI 16))])]
- "TARGET_HAS_CDX && XVECLEN (operands[0], 0) == 4
- && (-INTVAL (operands[1]) & 3) == 0
- && (-INTVAL (operands[1]) - 12) <= 60"
-{
- operands[2] = GEN_INT (-INTVAL (operands[1]) - 12);
- return "push.n\\t{ra, r17, r16}, %2";
-}
- [(set_attr "type" "push")])
-
-(define_insn "*cdx_pop_r16_r17_fp_ra"
- [(match_parallel 0 "pop_operation"
- [(return)
- (set (reg:SI SP_REGNO)
- (plus:SI (reg:SI SP_REGNO) (match_operand 1 "const_int_operand" "")))
- (set (reg:SI RA_REGNO) (match_operand:SI 2 "stack_memory_operand" ""))
- (set (reg:SI FP_REGNO) (match_operand:SI 3 "stack_memory_operand" ""))
- (set (reg:SI 17) (match_operand:SI 4 "stack_memory_operand" ""))
- (set (reg:SI 16) (match_operand:SI 5 "stack_memory_operand" ""))])]
- "TARGET_HAS_CDX && XVECLEN (operands[0], 0) == 6"
-{
- rtx x = XEXP (operands[5], 0);
- operands[5] = REG_P (x) ? const0_rtx : XEXP (x, 1);
- return "pop.n\\t{r16, r17, fp, ra}, %5";
-}
- [(set_attr "type" "pop")])
-
-(define_insn "*cdx_pop_r16_r17_ra"
- [(match_parallel 0 "pop_operation"
- [(return)
- (set (reg:SI SP_REGNO)
- (plus:SI (reg:SI SP_REGNO) (match_operand 1 "const_int_operand" "")))
- (set (reg:SI RA_REGNO) (match_operand:SI 2 "stack_memory_operand" ""))
- (set (reg:SI 17) (match_operand:SI 3 "stack_memory_operand" ""))
- (set (reg:SI 16) (match_operand:SI 4 "stack_memory_operand" ""))])]
- "TARGET_HAS_CDX && XVECLEN (operands[0], 0) == 5"
-{
- rtx x = XEXP (operands[4], 0);
- operands[4] = REG_P (x) ? const0_rtx : XEXP (x, 1);
- return "pop.n\\t{r16, r17, ra}, %4";
-}
- [(set_attr "type" "pop")])
-
-(define_insn "*cdx_push_ra_fp_r18_r17_r16"
- [(match_parallel 0 ""
- [(set (reg:SI SP_REGNO)
- (plus:SI (reg:SI SP_REGNO) (match_operand 1 "const_int_operand" "")))
- (set (mem:SI (plus:SI (reg:SI SP_REGNO) (const_int -4))) (reg:SI RA_REGNO))
- (set (mem:SI (plus:SI (reg:SI SP_REGNO) (const_int -8))) (reg:SI FP_REGNO))
- (set (mem:SI (plus:SI (reg:SI SP_REGNO) (const_int -12))) (reg:SI 18))
- (set (mem:SI (plus:SI (reg:SI SP_REGNO) (const_int -16))) (reg:SI 17))
- (set (mem:SI (plus:SI (reg:SI SP_REGNO) (const_int -20))) (reg:SI 16))])]
- "TARGET_HAS_CDX && XVECLEN (operands[0], 0) == 6
- && (-INTVAL (operands[1]) & 3) == 0
- && (-INTVAL (operands[1]) - 20) <= 60"
-{
- operands[2] = GEN_INT (-INTVAL (operands[1]) - 20);
- return "push.n\\t{ra, fp, r18, r17, r16}, %2";
-}
- [(set_attr "type" "push")])
-
-(define_insn "*cdx_push_ra_r18_r17_r16"
- [(match_parallel 0 ""
- [(set (reg:SI SP_REGNO)
- (plus:SI (reg:SI SP_REGNO) (match_operand 1 "const_int_operand" "")))
- (set (mem:SI (plus:SI (reg:SI SP_REGNO) (const_int -4))) (reg:SI RA_REGNO))
- (set (mem:SI (plus:SI (reg:SI SP_REGNO) (const_int -8))) (reg:SI 18))
- (set (mem:SI (plus:SI (reg:SI SP_REGNO) (const_int -12))) (reg:SI 17))
- (set (mem:SI (plus:SI (reg:SI SP_REGNO) (const_int -16))) (reg:SI 16))])]
- "TARGET_HAS_CDX && XVECLEN (operands[0], 0) == 5
- && (-INTVAL (operands[1]) & 3) == 0
- && (-INTVAL (operands[1]) - 16) <= 60"
-{
- operands[2] = GEN_INT (-INTVAL (operands[1]) - 16);
- return "push.n\\t{ra, r18, r17, r16}, %2";
-}
- [(set_attr "type" "push")])
-
-(define_insn "*cdx_pop_r16_r17_r18_fp_ra"
- [(match_parallel 0 "pop_operation"
- [(return)
- (set (reg:SI SP_REGNO)
- (plus:SI (reg:SI SP_REGNO) (match_operand 1 "const_int_operand" "")))
- (set (reg:SI RA_REGNO) (match_operand:SI 2 "stack_memory_operand" ""))
- (set (reg:SI FP_REGNO) (match_operand:SI 3 "stack_memory_operand" ""))
- (set (reg:SI 18) (match_operand:SI 4 "stack_memory_operand" ""))
- (set (reg:SI 17) (match_operand:SI 5 "stack_memory_operand" ""))
- (set (reg:SI 16) (match_operand:SI 6 "stack_memory_operand" ""))])]
- "TARGET_HAS_CDX && XVECLEN (operands[0], 0) == 7"
-{
- rtx x = XEXP (operands[6], 0);
- operands[6] = REG_P (x) ? const0_rtx : XEXP (x, 1);
- return "pop.n\\t{r16, r17, r18, fp, ra}, %6";
-}
- [(set_attr "type" "pop")])
-
-(define_insn "*cdx_pop_r16_r17_r18_ra"
- [(match_parallel 0 "pop_operation"
- [(return)
- (set (reg:SI SP_REGNO)
- (plus:SI (reg:SI SP_REGNO) (match_operand 1 "const_int_operand" "")))
- (set (reg:SI RA_REGNO) (match_operand:SI 2 "stack_memory_operand" ""))
- (set (reg:SI 18) (match_operand:SI 3 "stack_memory_operand" ""))
- (set (reg:SI 17) (match_operand:SI 4 "stack_memory_operand" ""))
- (set (reg:SI 16) (match_operand:SI 5 "stack_memory_operand" ""))])]
- "TARGET_HAS_CDX && XVECLEN (operands[0], 0) == 6"
-{
- rtx x = XEXP (operands[5], 0);
- operands[5] = REG_P (x) ? const0_rtx : XEXP (x, 1);
- return "pop.n\\t{r16, r17, r18, ra}, %5";
-}
- [(set_attr "type" "pop")])
-
-(define_insn "*cdx_push_ra_fp_r19_r18_r17_r16"
- [(match_parallel 0 ""
- [(set (reg:SI SP_REGNO)
- (plus:SI (reg:SI SP_REGNO) (match_operand 1 "const_int_operand" "")))
- (set (mem:SI (plus:SI (reg:SI SP_REGNO) (const_int -4))) (reg:SI RA_REGNO))
- (set (mem:SI (plus:SI (reg:SI SP_REGNO) (const_int -8))) (reg:SI FP_REGNO))
- (set (mem:SI (plus:SI (reg:SI SP_REGNO) (const_int -12))) (reg:SI 19))
- (set (mem:SI (plus:SI (reg:SI SP_REGNO) (const_int -16))) (reg:SI 18))
- (set (mem:SI (plus:SI (reg:SI SP_REGNO) (const_int -20))) (reg:SI 17))
- (set (mem:SI (plus:SI (reg:SI SP_REGNO) (const_int -24))) (reg:SI 16))])]
- "TARGET_HAS_CDX && XVECLEN (operands[0], 0) == 7
- && (-INTVAL (operands[1]) & 3) == 0
- && (-INTVAL (operands[1]) - 24) <= 60"
-{
- operands[2] = GEN_INT (-INTVAL (operands[1]) - 24);
- return "push.n\\t{ra, fp, r19, r18, r17, r16}, %2";
-}
- [(set_attr "type" "push")])
-
-(define_insn "*cdx_push_ra_r19_r18_r17_r16"
- [(match_parallel 0 ""
- [(set (reg:SI SP_REGNO)
- (plus:SI (reg:SI SP_REGNO) (match_operand 1 "const_int_operand" "")))
- (set (mem:SI (plus:SI (reg:SI SP_REGNO) (const_int -4))) (reg:SI RA_REGNO))
- (set (mem:SI (plus:SI (reg:SI SP_REGNO) (const_int -8))) (reg:SI 19))
- (set (mem:SI (plus:SI (reg:SI SP_REGNO) (const_int -12))) (reg:SI 18))
- (set (mem:SI (plus:SI (reg:SI SP_REGNO) (const_int -16))) (reg:SI 17))
- (set (mem:SI (plus:SI (reg:SI SP_REGNO) (const_int -20))) (reg:SI 16))])]
- "TARGET_HAS_CDX && XVECLEN (operands[0], 0) == 6
- && (-INTVAL (operands[1]) & 3) == 0
- && (-INTVAL (operands[1]) - 20) <= 60"
-{
- operands[2] = GEN_INT (-INTVAL (operands[1]) - 20);
- return "push.n\\t{ra, r19, r18, r17, r16}, %2";
-}
- [(set_attr "type" "push")])
-
-(define_insn "*cdx_pop_r16_r17_r18_r19_fp_ra"
- [(match_parallel 0 "pop_operation"
- [(return)
- (set (reg:SI SP_REGNO)
- (plus:SI (reg:SI SP_REGNO) (match_operand 1 "const_int_operand" "")))
- (set (reg:SI RA_REGNO) (match_operand:SI 2 "stack_memory_operand" ""))
- (set (reg:SI FP_REGNO) (match_operand:SI 3 "stack_memory_operand" ""))
- (set (reg:SI 19) (match_operand:SI 4 "stack_memory_operand" ""))
- (set (reg:SI 18) (match_operand:SI 5 "stack_memory_operand" ""))
- (set (reg:SI 17) (match_operand:SI 6 "stack_memory_operand" ""))
- (set (reg:SI 16) (match_operand:SI 7 "stack_memory_operand" ""))])]
- "TARGET_HAS_CDX && XVECLEN (operands[0], 0) == 8"
-{
- rtx x = XEXP (operands[7], 0);
- operands[7] = REG_P (x) ? const0_rtx : XEXP (x, 1);
- return "pop.n\\t{r16, r17, r18, r19, fp, ra}, %7";
-}
- [(set_attr "type" "pop")])
-
-(define_insn "*cdx_pop_r16_r17_r18_r19_ra"
- [(match_parallel 0 "pop_operation"
- [(return)
- (set (reg:SI SP_REGNO)
- (plus:SI (reg:SI SP_REGNO) (match_operand 1 "const_int_operand" "")))
- (set (reg:SI RA_REGNO) (match_operand:SI 2 "stack_memory_operand" ""))
- (set (reg:SI 19) (match_operand:SI 3 "stack_memory_operand" ""))
- (set (reg:SI 18) (match_operand:SI 4 "stack_memory_operand" ""))
- (set (reg:SI 17) (match_operand:SI 5 "stack_memory_operand" ""))
- (set (reg:SI 16) (match_operand:SI 6 "stack_memory_operand" ""))])]
- "TARGET_HAS_CDX && XVECLEN (operands[0], 0) == 7"
-{
- rtx x = XEXP (operands[6], 0);
- operands[6] = REG_P (x) ? const0_rtx : XEXP (x, 1);
- return "pop.n\\t{r16, r17, r18, r19, ra}, %6";
-}
- [(set_attr "type" "pop")])
-
-(define_insn "*cdx_push_ra_fp_r20_r19_r18_r17_r16"
- [(match_parallel 0 ""
- [(set (reg:SI SP_REGNO)
- (plus:SI (reg:SI SP_REGNO) (match_operand 1 "const_int_operand" "")))
- (set (mem:SI (plus:SI (reg:SI SP_REGNO) (const_int -4))) (reg:SI RA_REGNO))
- (set (mem:SI (plus:SI (reg:SI SP_REGNO) (const_int -8))) (reg:SI FP_REGNO))
- (set (mem:SI (plus:SI (reg:SI SP_REGNO) (const_int -12))) (reg:SI 20))
- (set (mem:SI (plus:SI (reg:SI SP_REGNO) (const_int -16))) (reg:SI 19))
- (set (mem:SI (plus:SI (reg:SI SP_REGNO) (const_int -20))) (reg:SI 18))
- (set (mem:SI (plus:SI (reg:SI SP_REGNO) (const_int -24))) (reg:SI 17))
- (set (mem:SI (plus:SI (reg:SI SP_REGNO) (const_int -28))) (reg:SI 16))])]
- "TARGET_HAS_CDX && XVECLEN (operands[0], 0) == 8
- && (-INTVAL (operands[1]) & 3) == 0
- && (-INTVAL (operands[1]) - 28) <= 60"
-{
- operands[2] = GEN_INT (-INTVAL (operands[1]) - 28);
- return "push.n\\t{ra, fp, r20, r19, r18, r17, r16}, %2";
-}
- [(set_attr "type" "push")])
-
-(define_insn "*cdx_push_ra_r20_r19_r18_r17_r16"
- [(match_parallel 0 ""
- [(set (reg:SI SP_REGNO)
- (plus:SI (reg:SI SP_REGNO) (match_operand 1 "const_int_operand" "")))
- (set (mem:SI (plus:SI (reg:SI SP_REGNO) (const_int -4))) (reg:SI RA_REGNO))
- (set (mem:SI (plus:SI (reg:SI SP_REGNO) (const_int -8))) (reg:SI 20))
- (set (mem:SI (plus:SI (reg:SI SP_REGNO) (const_int -12))) (reg:SI 19))
- (set (mem:SI (plus:SI (reg:SI SP_REGNO) (const_int -16))) (reg:SI 18))
- (set (mem:SI (plus:SI (reg:SI SP_REGNO) (const_int -20))) (reg:SI 17))
- (set (mem:SI (plus:SI (reg:SI SP_REGNO) (const_int -24))) (reg:SI 16))])]
- "TARGET_HAS_CDX && XVECLEN (operands[0], 0) == 7
- && (-INTVAL (operands[1]) & 3) == 0
- && (-INTVAL (operands[1]) - 24) <= 60"
-{
- operands[2] = GEN_INT (-INTVAL (operands[1]) - 24);
- return "push.n\\t{ra, r20, r19, r18, r17, r16}, %2";
-}
- [(set_attr "type" "push")])
-
-(define_insn "*cdx_pop_r16_r17_r18_r19_r20_fp_ra"
- [(match_parallel 0 "pop_operation"
- [(return)
- (set (reg:SI SP_REGNO)
- (plus:SI (reg:SI SP_REGNO) (match_operand 1 "const_int_operand" "")))
- (set (reg:SI RA_REGNO) (match_operand:SI 2 "stack_memory_operand" ""))
- (set (reg:SI FP_REGNO) (match_operand:SI 3 "stack_memory_operand" ""))
- (set (reg:SI 20) (match_operand:SI 4 "stack_memory_operand" ""))
- (set (reg:SI 19) (match_operand:SI 5 "stack_memory_operand" ""))
- (set (reg:SI 18) (match_operand:SI 6 "stack_memory_operand" ""))
- (set (reg:SI 17) (match_operand:SI 7 "stack_memory_operand" ""))
- (set (reg:SI 16) (match_operand:SI 8 "stack_memory_operand" ""))])]
- "TARGET_HAS_CDX && XVECLEN (operands[0], 0) == 9"
-{
- rtx x = XEXP (operands[8], 0);
- operands[8] = REG_P (x) ? const0_rtx : XEXP (x, 1);
- return "pop.n\\t{r16, r17, r18, r19, r20, fp, ra}, %8";
-}
- [(set_attr "type" "pop")])
-
-(define_insn "*cdx_pop_r16_r17_r18_r19_r20_ra"
- [(match_parallel 0 "pop_operation"
- [(return)
- (set (reg:SI SP_REGNO)
- (plus:SI (reg:SI SP_REGNO) (match_operand 1 "const_int_operand" "")))
- (set (reg:SI RA_REGNO) (match_operand:SI 2 "stack_memory_operand" ""))
- (set (reg:SI 20) (match_operand:SI 3 "stack_memory_operand" ""))
- (set (reg:SI 19) (match_operand:SI 4 "stack_memory_operand" ""))
- (set (reg:SI 18) (match_operand:SI 5 "stack_memory_operand" ""))
- (set (reg:SI 17) (match_operand:SI 6 "stack_memory_operand" ""))
- (set (reg:SI 16) (match_operand:SI 7 "stack_memory_operand" ""))])]
- "TARGET_HAS_CDX && XVECLEN (operands[0], 0) == 8"
-{
- rtx x = XEXP (operands[7], 0);
- operands[7] = REG_P (x) ? const0_rtx : XEXP (x, 1);
- return "pop.n\\t{r16, r17, r18, r19, r20, ra}, %7";
-}
- [(set_attr "type" "pop")])
-
-(define_insn "*cdx_push_ra_fp_r21_r20_r19_r18_r17_r16"
- [(match_parallel 0 ""
- [(set (reg:SI SP_REGNO)
- (plus:SI (reg:SI SP_REGNO) (match_operand 1 "const_int_operand" "")))
- (set (mem:SI (plus:SI (reg:SI SP_REGNO) (const_int -4))) (reg:SI RA_REGNO))
- (set (mem:SI (plus:SI (reg:SI SP_REGNO) (const_int -8))) (reg:SI FP_REGNO))
- (set (mem:SI (plus:SI (reg:SI SP_REGNO) (const_int -12))) (reg:SI 21))
- (set (mem:SI (plus:SI (reg:SI SP_REGNO) (const_int -16))) (reg:SI 20))
- (set (mem:SI (plus:SI (reg:SI SP_REGNO) (const_int -20))) (reg:SI 19))
- (set (mem:SI (plus:SI (reg:SI SP_REGNO) (const_int -24))) (reg:SI 18))
- (set (mem:SI (plus:SI (reg:SI SP_REGNO) (const_int -28))) (reg:SI 17))
- (set (mem:SI (plus:SI (reg:SI SP_REGNO) (const_int -32))) (reg:SI 16))])]
- "TARGET_HAS_CDX && XVECLEN (operands[0], 0) == 9
- && (-INTVAL (operands[1]) & 3) == 0
- && (-INTVAL (operands[1]) - 32) <= 60"
-{
- operands[2] = GEN_INT (-INTVAL (operands[1]) - 32);
- return "push.n\\t{ra, fp, r21, r20, r19, r18, r17, r16}, %2";
-}
- [(set_attr "type" "push")])
-
-(define_insn "*cdx_push_ra_r21_r20_r19_r18_r17_r16"
- [(match_parallel 0 ""
- [(set (reg:SI SP_REGNO)
- (plus:SI (reg:SI SP_REGNO) (match_operand 1 "const_int_operand" "")))
- (set (mem:SI (plus:SI (reg:SI SP_REGNO) (const_int -4))) (reg:SI RA_REGNO))
- (set (mem:SI (plus:SI (reg:SI SP_REGNO) (const_int -8))) (reg:SI 21))
- (set (mem:SI (plus:SI (reg:SI SP_REGNO) (const_int -12))) (reg:SI 20))
- (set (mem:SI (plus:SI (reg:SI SP_REGNO) (const_int -16))) (reg:SI 19))
- (set (mem:SI (plus:SI (reg:SI SP_REGNO) (const_int -20))) (reg:SI 18))
- (set (mem:SI (plus:SI (reg:SI SP_REGNO) (const_int -24))) (reg:SI 17))
- (set (mem:SI (plus:SI (reg:SI SP_REGNO) (const_int -28))) (reg:SI 16))])]
- "TARGET_HAS_CDX && XVECLEN (operands[0], 0) == 8
- && (-INTVAL (operands[1]) & 3) == 0
- && (-INTVAL (operands[1]) - 28) <= 60"
-{
- operands[2] = GEN_INT (-INTVAL (operands[1]) - 28);
- return "push.n\\t{ra, r21, r20, r19, r18, r17, r16}, %2";
-}
- [(set_attr "type" "push")])
-
-(define_insn "*cdx_pop_r16_r17_r18_r19_r20_r21_fp_ra"
- [(match_parallel 0 "pop_operation"
- [(return)
- (set (reg:SI SP_REGNO)
- (plus:SI (reg:SI SP_REGNO) (match_operand 1 "const_int_operand" "")))
- (set (reg:SI RA_REGNO) (match_operand:SI 2 "stack_memory_operand" ""))
- (set (reg:SI FP_REGNO) (match_operand:SI 3 "stack_memory_operand" ""))
- (set (reg:SI 21) (match_operand:SI 4 "stack_memory_operand" ""))
- (set (reg:SI 20) (match_operand:SI 5 "stack_memory_operand" ""))
- (set (reg:SI 19) (match_operand:SI 6 "stack_memory_operand" ""))
- (set (reg:SI 18) (match_operand:SI 7 "stack_memory_operand" ""))
- (set (reg:SI 17) (match_operand:SI 8 "stack_memory_operand" ""))
- (set (reg:SI 16) (match_operand:SI 9 "stack_memory_operand" ""))])]
- "TARGET_HAS_CDX && XVECLEN (operands[0], 0) == 10"
-{
- rtx x = XEXP (operands[9], 0);
- operands[9] = REG_P (x) ? const0_rtx : XEXP (x, 1);
- return "pop.n\\t{r16, r17, r18, r19, r20, r21, fp, ra}, %9";
-}
- [(set_attr "type" "pop")])
-
-(define_insn "*cdx_pop_r16_r17_r18_r19_r20_r21_ra"
- [(match_parallel 0 "pop_operation"
- [(return)
- (set (reg:SI SP_REGNO)
- (plus:SI (reg:SI SP_REGNO) (match_operand 1 "const_int_operand" "")))
- (set (reg:SI RA_REGNO) (match_operand:SI 2 "stack_memory_operand" ""))
- (set (reg:SI 21) (match_operand:SI 3 "stack_memory_operand" ""))
- (set (reg:SI 20) (match_operand:SI 4 "stack_memory_operand" ""))
- (set (reg:SI 19) (match_operand:SI 5 "stack_memory_operand" ""))
- (set (reg:SI 18) (match_operand:SI 6 "stack_memory_operand" ""))
- (set (reg:SI 17) (match_operand:SI 7 "stack_memory_operand" ""))
- (set (reg:SI 16) (match_operand:SI 8 "stack_memory_operand" ""))])]
- "TARGET_HAS_CDX && XVECLEN (operands[0], 0) == 9"
-{
- rtx x = XEXP (operands[8], 0);
- operands[8] = REG_P (x) ? const0_rtx : XEXP (x, 1);
- return "pop.n\\t{r16, r17, r18, r19, r20, r21, ra}, %8";
-}
- [(set_attr "type" "pop")])
-
-(define_insn "*cdx_push_ra_fp_r22_r21_r20_r19_r18_r17_r16"
- [(match_parallel 0 ""
- [(set (reg:SI SP_REGNO)
- (plus:SI (reg:SI SP_REGNO) (match_operand 1 "const_int_operand" "")))
- (set (mem:SI (plus:SI (reg:SI SP_REGNO) (const_int -4))) (reg:SI RA_REGNO))
- (set (mem:SI (plus:SI (reg:SI SP_REGNO) (const_int -8))) (reg:SI FP_REGNO))
- (set (mem:SI (plus:SI (reg:SI SP_REGNO) (const_int -12))) (reg:SI 22))
- (set (mem:SI (plus:SI (reg:SI SP_REGNO) (const_int -16))) (reg:SI 21))
- (set (mem:SI (plus:SI (reg:SI SP_REGNO) (const_int -20))) (reg:SI 20))
- (set (mem:SI (plus:SI (reg:SI SP_REGNO) (const_int -24))) (reg:SI 19))
- (set (mem:SI (plus:SI (reg:SI SP_REGNO) (const_int -28))) (reg:SI 18))
- (set (mem:SI (plus:SI (reg:SI SP_REGNO) (const_int -32))) (reg:SI 17))
- (set (mem:SI (plus:SI (reg:SI SP_REGNO) (const_int -36))) (reg:SI 16))])]
- "TARGET_HAS_CDX && XVECLEN (operands[0], 0) == 10
- && (-INTVAL (operands[1]) & 3) == 0
- && (-INTVAL (operands[1]) - 36) <= 60"
-{
- operands[2] = GEN_INT (-INTVAL (operands[1]) - 36);
- return "push.n\\t{ra, fp, r22, r21, r20, r19, r18, r17, r16}, %2";
-}
- [(set_attr "type" "push")])
-
-(define_insn "*cdx_push_ra_r22_r21_r20_r19_r18_r17_r16"
- [(match_parallel 0 ""
- [(set (reg:SI SP_REGNO)
- (plus:SI (reg:SI SP_REGNO) (match_operand 1 "const_int_operand" "")))
- (set (mem:SI (plus:SI (reg:SI SP_REGNO) (const_int -4))) (reg:SI RA_REGNO))
- (set (mem:SI (plus:SI (reg:SI SP_REGNO) (const_int -8))) (reg:SI 22))
- (set (mem:SI (plus:SI (reg:SI SP_REGNO) (const_int -12))) (reg:SI 21))
- (set (mem:SI (plus:SI (reg:SI SP_REGNO) (const_int -16))) (reg:SI 20))
- (set (mem:SI (plus:SI (reg:SI SP_REGNO) (const_int -20))) (reg:SI 19))
- (set (mem:SI (plus:SI (reg:SI SP_REGNO) (const_int -24))) (reg:SI 18))
- (set (mem:SI (plus:SI (reg:SI SP_REGNO) (const_int -28))) (reg:SI 17))
- (set (mem:SI (plus:SI (reg:SI SP_REGNO) (const_int -32))) (reg:SI 16))])]
- "TARGET_HAS_CDX && XVECLEN (operands[0], 0) == 9
- && (-INTVAL (operands[1]) & 3) == 0
- && (-INTVAL (operands[1]) - 32) <= 60"
-{
- operands[2] = GEN_INT (-INTVAL (operands[1]) - 32);
- return "push.n\\t{ra, r22, r21, r20, r19, r18, r17, r16}, %2";
-}
- [(set_attr "type" "push")])
-
-(define_insn "*cdx_pop_r16_r17_r18_r19_r20_r21_r22_fp_ra"
- [(match_parallel 0 "pop_operation"
- [(return)
- (set (reg:SI SP_REGNO)
- (plus:SI (reg:SI SP_REGNO) (match_operand 1 "const_int_operand" "")))
- (set (reg:SI RA_REGNO) (match_operand:SI 2 "stack_memory_operand" ""))
- (set (reg:SI FP_REGNO) (match_operand:SI 3 "stack_memory_operand" ""))
- (set (reg:SI 22) (match_operand:SI 4 "stack_memory_operand" ""))
- (set (reg:SI 21) (match_operand:SI 5 "stack_memory_operand" ""))
- (set (reg:SI 20) (match_operand:SI 6 "stack_memory_operand" ""))
- (set (reg:SI 19) (match_operand:SI 7 "stack_memory_operand" ""))
- (set (reg:SI 18) (match_operand:SI 8 "stack_memory_operand" ""))
- (set (reg:SI 17) (match_operand:SI 9 "stack_memory_operand" ""))
- (set (reg:SI 16) (match_operand:SI 10 "stack_memory_operand" ""))])]
- "TARGET_HAS_CDX && XVECLEN (operands[0], 0) == 11"
-{
- rtx x = XEXP (operands[10], 0);
- operands[10] = REG_P (x) ? const0_rtx : XEXP (x, 1);
- return "pop.n\\t{r16, r17, r18, r19, r20, r21, r22, fp, ra}, %10";
-}
- [(set_attr "type" "pop")])
-
-(define_insn "*cdx_pop_r16_r17_r18_r19_r20_r21_r22_ra"
- [(match_parallel 0 "pop_operation"
- [(return)
- (set (reg:SI SP_REGNO)
- (plus:SI (reg:SI SP_REGNO) (match_operand 1 "const_int_operand" "")))
- (set (reg:SI RA_REGNO) (match_operand:SI 2 "stack_memory_operand" ""))
- (set (reg:SI 22) (match_operand:SI 3 "stack_memory_operand" ""))
- (set (reg:SI 21) (match_operand:SI 4 "stack_memory_operand" ""))
- (set (reg:SI 20) (match_operand:SI 5 "stack_memory_operand" ""))
- (set (reg:SI 19) (match_operand:SI 6 "stack_memory_operand" ""))
- (set (reg:SI 18) (match_operand:SI 7 "stack_memory_operand" ""))
- (set (reg:SI 17) (match_operand:SI 8 "stack_memory_operand" ""))
- (set (reg:SI 16) (match_operand:SI 9 "stack_memory_operand" ""))])]
- "TARGET_HAS_CDX && XVECLEN (operands[0], 0) == 10"
-{
- rtx x = XEXP (operands[9], 0);
- operands[9] = REG_P (x) ? const0_rtx : XEXP (x, 1);
- return "pop.n\\t{r16, r17, r18, r19, r20, r21, r22, ra}, %9";
-}
- [(set_attr "type" "pop")])
-
-(define_insn "*cdx_push_ra_fp_r23_r22_r21_r20_r19_r18_r17_r16"
- [(match_parallel 0 ""
- [(set (reg:SI SP_REGNO)
- (plus:SI (reg:SI SP_REGNO) (match_operand 1 "const_int_operand" "")))
- (set (mem:SI (plus:SI (reg:SI SP_REGNO) (const_int -4))) (reg:SI RA_REGNO))
- (set (mem:SI (plus:SI (reg:SI SP_REGNO) (const_int -8))) (reg:SI FP_REGNO))
- (set (mem:SI (plus:SI (reg:SI SP_REGNO) (const_int -12))) (reg:SI 23))
- (set (mem:SI (plus:SI (reg:SI SP_REGNO) (const_int -16))) (reg:SI 22))
- (set (mem:SI (plus:SI (reg:SI SP_REGNO) (const_int -20))) (reg:SI 21))
- (set (mem:SI (plus:SI (reg:SI SP_REGNO) (const_int -24))) (reg:SI 20))
- (set (mem:SI (plus:SI (reg:SI SP_REGNO) (const_int -28))) (reg:SI 19))
- (set (mem:SI (plus:SI (reg:SI SP_REGNO) (const_int -32))) (reg:SI 18))
- (set (mem:SI (plus:SI (reg:SI SP_REGNO) (const_int -36))) (reg:SI 17))
- (set (mem:SI (plus:SI (reg:SI SP_REGNO) (const_int -40))) (reg:SI 16))])]
- "TARGET_HAS_CDX && XVECLEN (operands[0], 0) == 11
- && (-INTVAL (operands[1]) & 3) == 0
- && (-INTVAL (operands[1]) - 40) <= 60"
-{
- operands[2] = GEN_INT (-INTVAL (operands[1]) - 40);
- return "push.n\\t{ra, fp, r23, r22, r21, r20, r19, r18, r17, r16}, %2";
-}
- [(set_attr "type" "push")])
-
-(define_insn "*cdx_push_ra_r23_r22_r21_r20_r19_r18_r17_r16"
- [(match_parallel 0 ""
- [(set (reg:SI SP_REGNO)
- (plus:SI (reg:SI SP_REGNO) (match_operand 1 "const_int_operand" "")))
- (set (mem:SI (plus:SI (reg:SI SP_REGNO) (const_int -4))) (reg:SI RA_REGNO))
- (set (mem:SI (plus:SI (reg:SI SP_REGNO) (const_int -8))) (reg:SI 23))
- (set (mem:SI (plus:SI (reg:SI SP_REGNO) (const_int -12))) (reg:SI 22))
- (set (mem:SI (plus:SI (reg:SI SP_REGNO) (const_int -16))) (reg:SI 21))
- (set (mem:SI (plus:SI (reg:SI SP_REGNO) (const_int -20))) (reg:SI 20))
- (set (mem:SI (plus:SI (reg:SI SP_REGNO) (const_int -24))) (reg:SI 19))
- (set (mem:SI (plus:SI (reg:SI SP_REGNO) (const_int -28))) (reg:SI 18))
- (set (mem:SI (plus:SI (reg:SI SP_REGNO) (const_int -32))) (reg:SI 17))
- (set (mem:SI (plus:SI (reg:SI SP_REGNO) (const_int -36))) (reg:SI 16))])]
- "TARGET_HAS_CDX && XVECLEN (operands[0], 0) == 10
- && (-INTVAL (operands[1]) & 3) == 0
- && (-INTVAL (operands[1]) - 36) <= 60"
-{
- operands[2] = GEN_INT (-INTVAL (operands[1]) - 36);
- return "push.n\\t{ra, r23, r22, r21, r20, r19, r18, r17, r16}, %2";
-}
- [(set_attr "type" "push")])
-
-(define_insn "*cdx_pop_r16_r17_r18_r19_r20_r21_r22_r23_fp_ra"
- [(match_parallel 0 "pop_operation"
- [(return)
- (set (reg:SI SP_REGNO)
- (plus:SI (reg:SI SP_REGNO) (match_operand 1 "const_int_operand" "")))
- (set (reg:SI RA_REGNO) (match_operand:SI 2 "stack_memory_operand" ""))
- (set (reg:SI FP_REGNO) (match_operand:SI 3 "stack_memory_operand" ""))
- (set (reg:SI 23) (match_operand:SI 4 "stack_memory_operand" ""))
- (set (reg:SI 22) (match_operand:SI 5 "stack_memory_operand" ""))
- (set (reg:SI 21) (match_operand:SI 6 "stack_memory_operand" ""))
- (set (reg:SI 20) (match_operand:SI 7 "stack_memory_operand" ""))
- (set (reg:SI 19) (match_operand:SI 8 "stack_memory_operand" ""))
- (set (reg:SI 18) (match_operand:SI 9 "stack_memory_operand" ""))
- (set (reg:SI 17) (match_operand:SI 10 "stack_memory_operand" ""))
- (set (reg:SI 16) (match_operand:SI 11 "stack_memory_operand" ""))])]
- "TARGET_HAS_CDX && XVECLEN (operands[0], 0) == 12"
-{
- rtx x = XEXP (operands[11], 0);
- operands[11] = REG_P (x) ? const0_rtx : XEXP (x, 1);
- return "pop.n\\t{r16, r17, r18, r19, r20, r21, r22, r23, fp, ra}, %11";
-}
- [(set_attr "type" "pop")])
-
-(define_insn "*cdx_pop_r16_r17_r18_r19_r20_r21_r22_r23_ra"
- [(match_parallel 0 "pop_operation"
- [(return)
- (set (reg:SI SP_REGNO)
- (plus:SI (reg:SI SP_REGNO) (match_operand 1 "const_int_operand" "")))
- (set (reg:SI RA_REGNO) (match_operand:SI 2 "stack_memory_operand" ""))
- (set (reg:SI 23) (match_operand:SI 3 "stack_memory_operand" ""))
- (set (reg:SI 22) (match_operand:SI 4 "stack_memory_operand" ""))
- (set (reg:SI 21) (match_operand:SI 5 "stack_memory_operand" ""))
- (set (reg:SI 20) (match_operand:SI 6 "stack_memory_operand" ""))
- (set (reg:SI 19) (match_operand:SI 7 "stack_memory_operand" ""))
- (set (reg:SI 18) (match_operand:SI 8 "stack_memory_operand" ""))
- (set (reg:SI 17) (match_operand:SI 9 "stack_memory_operand" ""))
- (set (reg:SI 16) (match_operand:SI 10 "stack_memory_operand" ""))])]
- "TARGET_HAS_CDX && XVECLEN (operands[0], 0) == 11"
-{
- rtx x = XEXP (operands[10], 0);
- operands[10] = REG_P (x) ? const0_rtx : XEXP (x, 1);
- return "pop.n\\t{r16, r17, r18, r19, r20, r21, r22, r23, ra}, %10";
-}
- [(set_attr "type" "pop")])
-
-(define_insn "*cdx_ldwm1_inc_wb_ret"
- [(match_parallel 0 "ldwm_operation"
- [(return)
- (set (match_operand:SI 2 "register_operand" "+&r")
- (plus:SI (match_dup 2) (const_int 4)))
- (set (match_operand:SI 1 "nios2_hard_register_operand" "")
- (mem:SI (match_dup 2)))])]
- "TARGET_HAS_CDX && XVECLEN (operands[0], 0) == 3"
- "ldwm\\t{%1}, (%2)++, writeback, ret"
- [(set_attr "type" "ldwm")])
-
-(define_insn "*cdx_ldwm1_inc_wb"
- [(match_parallel 0 "ldwm_operation"
- [(set (match_operand:SI 2 "register_operand" "+&r")
- (plus:SI (match_dup 2) (const_int 4)))
- (set (match_operand:SI 1 "nios2_hard_register_operand" "")
- (mem:SI (match_dup 2)))])]
- "TARGET_HAS_CDX && XVECLEN (operands[0], 0) == 2"
- "ldwm\\t{%1}, (%2)++, writeback"
- [(set_attr "type" "ldwm")])
-
-(define_insn "*cdx_ldwm1_inc_ret"
- [(match_parallel 0 "ldwm_operation"
- [(return)
- (set (match_operand:SI 1 "nios2_hard_register_operand" "")
- (mem:SI (match_operand:SI 2 "register_operand" "r")))])]
- "TARGET_HAS_CDX && XVECLEN (operands[0], 0) == 2"
- "ldwm\\t{%1}, (%2)++, ret"
- [(set_attr "type" "ldwm")])
-
-(define_insn "*cdx_ldwm1_inc"
- [(match_parallel 0 "ldwm_operation"
- [(set (match_operand:SI 1 "nios2_hard_register_operand" "")
- (mem:SI (match_operand:SI 2 "register_operand" "r")))])]
- "TARGET_HAS_CDX && XVECLEN (operands[0], 0) == 1"
- "ldwm\\t{%1}, (%2)++"
- [(set_attr "type" "ldwm")])
-
-(define_insn "*cdx_ldwm1_dec_wb_ret"
- [(match_parallel 0 "ldwm_operation"
- [(return)
- (set (match_operand:SI 2 "register_operand" "+&r")
- (plus:SI (match_dup 2) (const_int -4)))
- (set (match_operand:SI 1 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 2) (const_int -4))))])]
- "TARGET_HAS_CDX && XVECLEN (operands[0], 0) == 3"
- "ldwm\\t{%1}, --(%2), writeback, ret"
- [(set_attr "type" "ldwm")])
-
-(define_insn "*cdx_ldwm1_dec_wb"
- [(match_parallel 0 "ldwm_operation"
- [(set (match_operand:SI 2 "register_operand" "+&r")
- (plus:SI (match_dup 2) (const_int -4)))
- (set (match_operand:SI 1 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 2) (const_int -4))))])]
- "TARGET_HAS_CDX && XVECLEN (operands[0], 0) == 2"
- "ldwm\\t{%1}, --(%2), writeback"
- [(set_attr "type" "ldwm")])
-
-(define_insn "*cdx_ldwm1_dec_ret"
- [(match_parallel 0 "ldwm_operation"
- [(return)
- (set (match_operand:SI 1 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_operand:SI 2 "register_operand" "r") (const_int -4))))])]
- "TARGET_HAS_CDX && XVECLEN (operands[0], 0) == 2"
- "ldwm\\t{%1}, --(%2), ret"
- [(set_attr "type" "ldwm")])
-
-(define_insn "*cdx_ldwm1_dec"
- [(match_parallel 0 "ldwm_operation"
- [(set (match_operand:SI 1 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_operand:SI 2 "register_operand" "r") (const_int -4))))])]
- "TARGET_HAS_CDX && XVECLEN (operands[0], 0) == 1"
- "ldwm\\t{%1}, --(%2)"
- [(set_attr "type" "ldwm")])
-
-(define_insn "*cdx_ldwm2_inc_wb_ret"
- [(match_parallel 0 "ldwm_operation"
- [(return)
- (set (match_operand:SI 3 "register_operand" "+&r")
- (plus:SI (match_dup 3) (const_int 8)))
- (set (match_operand:SI 1 "nios2_hard_register_operand" "")
- (mem:SI (match_dup 3)))
- (set (match_operand:SI 2 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 3) (const_int 4))))])]
- "TARGET_HAS_CDX && XVECLEN (operands[0], 0) == 4"
- "ldwm\\t{%1, %2}, (%3)++, writeback, ret"
- [(set_attr "type" "ldwm")])
-
-(define_insn "*cdx_ldwm2_inc_wb"
- [(match_parallel 0 "ldwm_operation"
- [(set (match_operand:SI 3 "register_operand" "+&r")
- (plus:SI (match_dup 3) (const_int 8)))
- (set (match_operand:SI 1 "nios2_hard_register_operand" "")
- (mem:SI (match_dup 3)))
- (set (match_operand:SI 2 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 3) (const_int 4))))])]
- "TARGET_HAS_CDX && XVECLEN (operands[0], 0) == 3"
- "ldwm\\t{%1, %2}, (%3)++, writeback"
- [(set_attr "type" "ldwm")])
-
-(define_insn "*cdx_ldwm2_inc_ret"
- [(match_parallel 0 "ldwm_operation"
- [(return)
- (set (match_operand:SI 1 "nios2_hard_register_operand" "")
- (mem:SI (match_operand:SI 3 "register_operand" "r")))
- (set (match_operand:SI 2 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 3) (const_int 4))))])]
- "TARGET_HAS_CDX && XVECLEN (operands[0], 0) == 3"
- "ldwm\\t{%1, %2}, (%3)++, ret"
- [(set_attr "type" "ldwm")])
-
-(define_insn "*cdx_ldwm2_inc"
- [(match_parallel 0 "ldwm_operation"
- [(set (match_operand:SI 1 "nios2_hard_register_operand" "")
- (mem:SI (match_operand:SI 3 "register_operand" "r")))
- (set (match_operand:SI 2 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 3) (const_int 4))))])]
- "TARGET_HAS_CDX && XVECLEN (operands[0], 0) == 2"
- "ldwm\\t{%1, %2}, (%3)++"
- [(set_attr "type" "ldwm")])
-
-(define_insn "*cdx_ldwm2_dec_wb_ret"
- [(match_parallel 0 "ldwm_operation"
- [(return)
- (set (match_operand:SI 3 "register_operand" "+&r")
- (plus:SI (match_dup 3) (const_int -8)))
- (set (match_operand:SI 1 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 3) (const_int -4))))
- (set (match_operand:SI 2 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 3) (const_int -8))))])]
- "TARGET_HAS_CDX && XVECLEN (operands[0], 0) == 4"
- "ldwm\\t{%1, %2}, --(%3), writeback, ret"
- [(set_attr "type" "ldwm")])
-
-(define_insn "*cdx_ldwm2_dec_wb"
- [(match_parallel 0 "ldwm_operation"
- [(set (match_operand:SI 3 "register_operand" "+&r")
- (plus:SI (match_dup 3) (const_int -8)))
- (set (match_operand:SI 1 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 3) (const_int -4))))
- (set (match_operand:SI 2 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 3) (const_int -8))))])]
- "TARGET_HAS_CDX && XVECLEN (operands[0], 0) == 3"
- "ldwm\\t{%1, %2}, --(%3), writeback"
- [(set_attr "type" "ldwm")])
-
-(define_insn "*cdx_ldwm2_dec_ret"
- [(match_parallel 0 "ldwm_operation"
- [(return)
- (set (match_operand:SI 1 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_operand:SI 3 "register_operand" "r") (const_int -4))))
- (set (match_operand:SI 2 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 3) (const_int -8))))])]
- "TARGET_HAS_CDX && XVECLEN (operands[0], 0) == 3"
- "ldwm\\t{%1, %2}, --(%3), ret"
- [(set_attr "type" "ldwm")])
-
-(define_insn "*cdx_ldwm2_dec"
- [(match_parallel 0 "ldwm_operation"
- [(set (match_operand:SI 1 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_operand:SI 3 "register_operand" "r") (const_int -4))))
- (set (match_operand:SI 2 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 3) (const_int -8))))])]
- "TARGET_HAS_CDX && XVECLEN (operands[0], 0) == 2"
- "ldwm\\t{%1, %2}, --(%3)"
- [(set_attr "type" "ldwm")])
-
-(define_insn "*cdx_ldwm3_inc_wb_ret"
- [(match_parallel 0 "ldwm_operation"
- [(return)
- (set (match_operand:SI 4 "register_operand" "+&r")
- (plus:SI (match_dup 4) (const_int 12)))
- (set (match_operand:SI 1 "nios2_hard_register_operand" "")
- (mem:SI (match_dup 4)))
- (set (match_operand:SI 2 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 4) (const_int 4))))
- (set (match_operand:SI 3 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 4) (const_int 8))))])]
- "TARGET_HAS_CDX && XVECLEN (operands[0], 0) == 5"
- "ldwm\\t{%1, %2, %3}, (%4)++, writeback, ret"
- [(set_attr "type" "ldwm")])
-
-(define_insn "*cdx_ldwm3_inc_wb"
- [(match_parallel 0 "ldwm_operation"
- [(set (match_operand:SI 4 "register_operand" "+&r")
- (plus:SI (match_dup 4) (const_int 12)))
- (set (match_operand:SI 1 "nios2_hard_register_operand" "")
- (mem:SI (match_dup 4)))
- (set (match_operand:SI 2 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 4) (const_int 4))))
- (set (match_operand:SI 3 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 4) (const_int 8))))])]
- "TARGET_HAS_CDX && XVECLEN (operands[0], 0) == 4"
- "ldwm\\t{%1, %2, %3}, (%4)++, writeback"
- [(set_attr "type" "ldwm")])
-
-(define_insn "*cdx_ldwm3_inc_ret"
- [(match_parallel 0 "ldwm_operation"
- [(return)
- (set (match_operand:SI 1 "nios2_hard_register_operand" "")
- (mem:SI (match_operand:SI 4 "register_operand" "r")))
- (set (match_operand:SI 2 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 4) (const_int 4))))
- (set (match_operand:SI 3 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 4) (const_int 8))))])]
- "TARGET_HAS_CDX && XVECLEN (operands[0], 0) == 4"
- "ldwm\\t{%1, %2, %3}, (%4)++, ret"
- [(set_attr "type" "ldwm")])
-
-(define_insn "*cdx_ldwm3_inc"
- [(match_parallel 0 "ldwm_operation"
- [(set (match_operand:SI 1 "nios2_hard_register_operand" "")
- (mem:SI (match_operand:SI 4 "register_operand" "r")))
- (set (match_operand:SI 2 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 4) (const_int 4))))
- (set (match_operand:SI 3 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 4) (const_int 8))))])]
- "TARGET_HAS_CDX && XVECLEN (operands[0], 0) == 3"
- "ldwm\\t{%1, %2, %3}, (%4)++"
- [(set_attr "type" "ldwm")])
-
-(define_insn "*cdx_ldwm3_dec_wb_ret"
- [(match_parallel 0 "ldwm_operation"
- [(return)
- (set (match_operand:SI 4 "register_operand" "+&r")
- (plus:SI (match_dup 4) (const_int -12)))
- (set (match_operand:SI 1 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 4) (const_int -4))))
- (set (match_operand:SI 2 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 4) (const_int -8))))
- (set (match_operand:SI 3 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 4) (const_int -12))))])]
- "TARGET_HAS_CDX && XVECLEN (operands[0], 0) == 5"
- "ldwm\\t{%1, %2, %3}, --(%4), writeback, ret"
- [(set_attr "type" "ldwm")])
-
-(define_insn "*cdx_ldwm3_dec_wb"
- [(match_parallel 0 "ldwm_operation"
- [(set (match_operand:SI 4 "register_operand" "+&r")
- (plus:SI (match_dup 4) (const_int -12)))
- (set (match_operand:SI 1 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 4) (const_int -4))))
- (set (match_operand:SI 2 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 4) (const_int -8))))
- (set (match_operand:SI 3 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 4) (const_int -12))))])]
- "TARGET_HAS_CDX && XVECLEN (operands[0], 0) == 4"
- "ldwm\\t{%1, %2, %3}, --(%4), writeback"
- [(set_attr "type" "ldwm")])
-
-(define_insn "*cdx_ldwm3_dec_ret"
- [(match_parallel 0 "ldwm_operation"
- [(return)
- (set (match_operand:SI 1 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_operand:SI 4 "register_operand" "r") (const_int -4))))
- (set (match_operand:SI 2 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 4) (const_int -8))))
- (set (match_operand:SI 3 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 4) (const_int -12))))])]
- "TARGET_HAS_CDX && XVECLEN (operands[0], 0) == 4"
- "ldwm\\t{%1, %2, %3}, --(%4), ret"
- [(set_attr "type" "ldwm")])
-
-(define_insn "*cdx_ldwm3_dec"
- [(match_parallel 0 "ldwm_operation"
- [(set (match_operand:SI 1 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_operand:SI 4 "register_operand" "r") (const_int -4))))
- (set (match_operand:SI 2 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 4) (const_int -8))))
- (set (match_operand:SI 3 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 4) (const_int -12))))])]
- "TARGET_HAS_CDX && XVECLEN (operands[0], 0) == 3"
- "ldwm\\t{%1, %2, %3}, --(%4)"
- [(set_attr "type" "ldwm")])
-
-(define_insn "*cdx_ldwm4_inc_wb_ret"
- [(match_parallel 0 "ldwm_operation"
- [(return)
- (set (match_operand:SI 5 "register_operand" "+&r")
- (plus:SI (match_dup 5) (const_int 16)))
- (set (match_operand:SI 1 "nios2_hard_register_operand" "")
- (mem:SI (match_dup 5)))
- (set (match_operand:SI 2 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 5) (const_int 4))))
- (set (match_operand:SI 3 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 5) (const_int 8))))
- (set (match_operand:SI 4 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 5) (const_int 12))))])]
- "TARGET_HAS_CDX && XVECLEN (operands[0], 0) == 6"
- "ldwm\\t{%1, %2, %3, %4}, (%5)++, writeback, ret"
- [(set_attr "type" "ldwm")])
-
-(define_insn "*cdx_ldwm4_inc_wb"
- [(match_parallel 0 "ldwm_operation"
- [(set (match_operand:SI 5 "register_operand" "+&r")
- (plus:SI (match_dup 5) (const_int 16)))
- (set (match_operand:SI 1 "nios2_hard_register_operand" "")
- (mem:SI (match_dup 5)))
- (set (match_operand:SI 2 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 5) (const_int 4))))
- (set (match_operand:SI 3 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 5) (const_int 8))))
- (set (match_operand:SI 4 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 5) (const_int 12))))])]
- "TARGET_HAS_CDX && XVECLEN (operands[0], 0) == 5"
- "ldwm\\t{%1, %2, %3, %4}, (%5)++, writeback"
- [(set_attr "type" "ldwm")])
-
-(define_insn "*cdx_ldwm4_inc_ret"
- [(match_parallel 0 "ldwm_operation"
- [(return)
- (set (match_operand:SI 1 "nios2_hard_register_operand" "")
- (mem:SI (match_operand:SI 5 "register_operand" "r")))
- (set (match_operand:SI 2 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 5) (const_int 4))))
- (set (match_operand:SI 3 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 5) (const_int 8))))
- (set (match_operand:SI 4 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 5) (const_int 12))))])]
- "TARGET_HAS_CDX && XVECLEN (operands[0], 0) == 5"
- "ldwm\\t{%1, %2, %3, %4}, (%5)++, ret"
- [(set_attr "type" "ldwm")])
-
-(define_insn "*cdx_ldwm4_inc"
- [(match_parallel 0 "ldwm_operation"
- [(set (match_operand:SI 1 "nios2_hard_register_operand" "")
- (mem:SI (match_operand:SI 5 "register_operand" "r")))
- (set (match_operand:SI 2 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 5) (const_int 4))))
- (set (match_operand:SI 3 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 5) (const_int 8))))
- (set (match_operand:SI 4 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 5) (const_int 12))))])]
- "TARGET_HAS_CDX && XVECLEN (operands[0], 0) == 4"
- "ldwm\\t{%1, %2, %3, %4}, (%5)++"
- [(set_attr "type" "ldwm")])
-
-(define_insn "*cdx_ldwm4_dec_wb_ret"
- [(match_parallel 0 "ldwm_operation"
- [(return)
- (set (match_operand:SI 5 "register_operand" "+&r")
- (plus:SI (match_dup 5) (const_int -16)))
- (set (match_operand:SI 1 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 5) (const_int -4))))
- (set (match_operand:SI 2 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 5) (const_int -8))))
- (set (match_operand:SI 3 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 5) (const_int -12))))
- (set (match_operand:SI 4 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 5) (const_int -16))))])]
- "TARGET_HAS_CDX && XVECLEN (operands[0], 0) == 6"
- "ldwm\\t{%1, %2, %3, %4}, --(%5), writeback, ret"
- [(set_attr "type" "ldwm")])
-
-(define_insn "*cdx_ldwm4_dec_wb"
- [(match_parallel 0 "ldwm_operation"
- [(set (match_operand:SI 5 "register_operand" "+&r")
- (plus:SI (match_dup 5) (const_int -16)))
- (set (match_operand:SI 1 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 5) (const_int -4))))
- (set (match_operand:SI 2 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 5) (const_int -8))))
- (set (match_operand:SI 3 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 5) (const_int -12))))
- (set (match_operand:SI 4 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 5) (const_int -16))))])]
- "TARGET_HAS_CDX && XVECLEN (operands[0], 0) == 5"
- "ldwm\\t{%1, %2, %3, %4}, --(%5), writeback"
- [(set_attr "type" "ldwm")])
-
-(define_insn "*cdx_ldwm4_dec_ret"
- [(match_parallel 0 "ldwm_operation"
- [(return)
- (set (match_operand:SI 1 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_operand:SI 5 "register_operand" "r") (const_int -4))))
- (set (match_operand:SI 2 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 5) (const_int -8))))
- (set (match_operand:SI 3 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 5) (const_int -12))))
- (set (match_operand:SI 4 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 5) (const_int -16))))])]
- "TARGET_HAS_CDX && XVECLEN (operands[0], 0) == 5"
- "ldwm\\t{%1, %2, %3, %4}, --(%5), ret"
- [(set_attr "type" "ldwm")])
-
-(define_insn "*cdx_ldwm4_dec"
- [(match_parallel 0 "ldwm_operation"
- [(set (match_operand:SI 1 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_operand:SI 5 "register_operand" "r") (const_int -4))))
- (set (match_operand:SI 2 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 5) (const_int -8))))
- (set (match_operand:SI 3 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 5) (const_int -12))))
- (set (match_operand:SI 4 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 5) (const_int -16))))])]
- "TARGET_HAS_CDX && XVECLEN (operands[0], 0) == 4"
- "ldwm\\t{%1, %2, %3, %4}, --(%5)"
- [(set_attr "type" "ldwm")])
-
-(define_insn "*cdx_ldwm5_inc_wb_ret"
- [(match_parallel 0 "ldwm_operation"
- [(return)
- (set (match_operand:SI 6 "register_operand" "+&r")
- (plus:SI (match_dup 6) (const_int 20)))
- (set (match_operand:SI 1 "nios2_hard_register_operand" "")
- (mem:SI (match_dup 6)))
- (set (match_operand:SI 2 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 6) (const_int 4))))
- (set (match_operand:SI 3 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 6) (const_int 8))))
- (set (match_operand:SI 4 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 6) (const_int 12))))
- (set (match_operand:SI 5 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 6) (const_int 16))))])]
- "TARGET_HAS_CDX && XVECLEN (operands[0], 0) == 7"
- "ldwm\\t{%1, %2, %3, %4, %5}, (%6)++, writeback, ret"
- [(set_attr "type" "ldwm")])
-
-(define_insn "*cdx_ldwm5_inc_wb"
- [(match_parallel 0 "ldwm_operation"
- [(set (match_operand:SI 6 "register_operand" "+&r")
- (plus:SI (match_dup 6) (const_int 20)))
- (set (match_operand:SI 1 "nios2_hard_register_operand" "")
- (mem:SI (match_dup 6)))
- (set (match_operand:SI 2 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 6) (const_int 4))))
- (set (match_operand:SI 3 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 6) (const_int 8))))
- (set (match_operand:SI 4 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 6) (const_int 12))))
- (set (match_operand:SI 5 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 6) (const_int 16))))])]
- "TARGET_HAS_CDX && XVECLEN (operands[0], 0) == 6"
- "ldwm\\t{%1, %2, %3, %4, %5}, (%6)++, writeback"
- [(set_attr "type" "ldwm")])
-
-(define_insn "*cdx_ldwm5_inc_ret"
- [(match_parallel 0 "ldwm_operation"
- [(return)
- (set (match_operand:SI 1 "nios2_hard_register_operand" "")
- (mem:SI (match_operand:SI 6 "register_operand" "r")))
- (set (match_operand:SI 2 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 6) (const_int 4))))
- (set (match_operand:SI 3 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 6) (const_int 8))))
- (set (match_operand:SI 4 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 6) (const_int 12))))
- (set (match_operand:SI 5 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 6) (const_int 16))))])]
- "TARGET_HAS_CDX && XVECLEN (operands[0], 0) == 6"
- "ldwm\\t{%1, %2, %3, %4, %5}, (%6)++, ret"
- [(set_attr "type" "ldwm")])
-
-(define_insn "*cdx_ldwm5_inc"
- [(match_parallel 0 "ldwm_operation"
- [(set (match_operand:SI 1 "nios2_hard_register_operand" "")
- (mem:SI (match_operand:SI 6 "register_operand" "r")))
- (set (match_operand:SI 2 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 6) (const_int 4))))
- (set (match_operand:SI 3 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 6) (const_int 8))))
- (set (match_operand:SI 4 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 6) (const_int 12))))
- (set (match_operand:SI 5 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 6) (const_int 16))))])]
- "TARGET_HAS_CDX && XVECLEN (operands[0], 0) == 5"
- "ldwm\\t{%1, %2, %3, %4, %5}, (%6)++"
- [(set_attr "type" "ldwm")])
-
-(define_insn "*cdx_ldwm5_dec_wb_ret"
- [(match_parallel 0 "ldwm_operation"
- [(return)
- (set (match_operand:SI 6 "register_operand" "+&r")
- (plus:SI (match_dup 6) (const_int -20)))
- (set (match_operand:SI 1 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 6) (const_int -4))))
- (set (match_operand:SI 2 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 6) (const_int -8))))
- (set (match_operand:SI 3 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 6) (const_int -12))))
- (set (match_operand:SI 4 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 6) (const_int -16))))
- (set (match_operand:SI 5 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 6) (const_int -20))))])]
- "TARGET_HAS_CDX && XVECLEN (operands[0], 0) == 7"
- "ldwm\\t{%1, %2, %3, %4, %5}, --(%6), writeback, ret"
- [(set_attr "type" "ldwm")])
-
-(define_insn "*cdx_ldwm5_dec_wb"
- [(match_parallel 0 "ldwm_operation"
- [(set (match_operand:SI 6 "register_operand" "+&r")
- (plus:SI (match_dup 6) (const_int -20)))
- (set (match_operand:SI 1 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 6) (const_int -4))))
- (set (match_operand:SI 2 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 6) (const_int -8))))
- (set (match_operand:SI 3 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 6) (const_int -12))))
- (set (match_operand:SI 4 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 6) (const_int -16))))
- (set (match_operand:SI 5 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 6) (const_int -20))))])]
- "TARGET_HAS_CDX && XVECLEN (operands[0], 0) == 6"
- "ldwm\\t{%1, %2, %3, %4, %5}, --(%6), writeback"
- [(set_attr "type" "ldwm")])
-
-(define_insn "*cdx_ldwm5_dec_ret"
- [(match_parallel 0 "ldwm_operation"
- [(return)
- (set (match_operand:SI 1 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_operand:SI 6 "register_operand" "r") (const_int -4))))
- (set (match_operand:SI 2 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 6) (const_int -8))))
- (set (match_operand:SI 3 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 6) (const_int -12))))
- (set (match_operand:SI 4 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 6) (const_int -16))))
- (set (match_operand:SI 5 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 6) (const_int -20))))])]
- "TARGET_HAS_CDX && XVECLEN (operands[0], 0) == 6"
- "ldwm\\t{%1, %2, %3, %4, %5}, --(%6), ret"
- [(set_attr "type" "ldwm")])
-
-(define_insn "*cdx_ldwm5_dec"
- [(match_parallel 0 "ldwm_operation"
- [(set (match_operand:SI 1 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_operand:SI 6 "register_operand" "r") (const_int -4))))
- (set (match_operand:SI 2 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 6) (const_int -8))))
- (set (match_operand:SI 3 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 6) (const_int -12))))
- (set (match_operand:SI 4 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 6) (const_int -16))))
- (set (match_operand:SI 5 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 6) (const_int -20))))])]
- "TARGET_HAS_CDX && XVECLEN (operands[0], 0) == 5"
- "ldwm\\t{%1, %2, %3, %4, %5}, --(%6)"
- [(set_attr "type" "ldwm")])
-
-(define_insn "*cdx_ldwm6_inc_wb_ret"
- [(match_parallel 0 "ldwm_operation"
- [(return)
- (set (match_operand:SI 7 "register_operand" "+&r")
- (plus:SI (match_dup 7) (const_int 24)))
- (set (match_operand:SI 1 "nios2_hard_register_operand" "")
- (mem:SI (match_dup 7)))
- (set (match_operand:SI 2 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 7) (const_int 4))))
- (set (match_operand:SI 3 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 7) (const_int 8))))
- (set (match_operand:SI 4 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 7) (const_int 12))))
- (set (match_operand:SI 5 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 7) (const_int 16))))
- (set (match_operand:SI 6 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 7) (const_int 20))))])]
- "TARGET_HAS_CDX && XVECLEN (operands[0], 0) == 8"
- "ldwm\\t{%1, %2, %3, %4, %5, %6}, (%7)++, writeback, ret"
- [(set_attr "type" "ldwm")])
-
-(define_insn "*cdx_ldwm6_inc_wb"
- [(match_parallel 0 "ldwm_operation"
- [(set (match_operand:SI 7 "register_operand" "+&r")
- (plus:SI (match_dup 7) (const_int 24)))
- (set (match_operand:SI 1 "nios2_hard_register_operand" "")
- (mem:SI (match_dup 7)))
- (set (match_operand:SI 2 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 7) (const_int 4))))
- (set (match_operand:SI 3 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 7) (const_int 8))))
- (set (match_operand:SI 4 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 7) (const_int 12))))
- (set (match_operand:SI 5 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 7) (const_int 16))))
- (set (match_operand:SI 6 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 7) (const_int 20))))])]
- "TARGET_HAS_CDX && XVECLEN (operands[0], 0) == 7"
- "ldwm\\t{%1, %2, %3, %4, %5, %6}, (%7)++, writeback"
- [(set_attr "type" "ldwm")])
-
-(define_insn "*cdx_ldwm6_inc_ret"
- [(match_parallel 0 "ldwm_operation"
- [(return)
- (set (match_operand:SI 1 "nios2_hard_register_operand" "")
- (mem:SI (match_operand:SI 7 "register_operand" "r")))
- (set (match_operand:SI 2 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 7) (const_int 4))))
- (set (match_operand:SI 3 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 7) (const_int 8))))
- (set (match_operand:SI 4 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 7) (const_int 12))))
- (set (match_operand:SI 5 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 7) (const_int 16))))
- (set (match_operand:SI 6 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 7) (const_int 20))))])]
- "TARGET_HAS_CDX && XVECLEN (operands[0], 0) == 7"
- "ldwm\\t{%1, %2, %3, %4, %5, %6}, (%7)++, ret"
- [(set_attr "type" "ldwm")])
-
-(define_insn "*cdx_ldwm6_inc"
- [(match_parallel 0 "ldwm_operation"
- [(set (match_operand:SI 1 "nios2_hard_register_operand" "")
- (mem:SI (match_operand:SI 7 "register_operand" "r")))
- (set (match_operand:SI 2 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 7) (const_int 4))))
- (set (match_operand:SI 3 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 7) (const_int 8))))
- (set (match_operand:SI 4 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 7) (const_int 12))))
- (set (match_operand:SI 5 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 7) (const_int 16))))
- (set (match_operand:SI 6 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 7) (const_int 20))))])]
- "TARGET_HAS_CDX && XVECLEN (operands[0], 0) == 6"
- "ldwm\\t{%1, %2, %3, %4, %5, %6}, (%7)++"
- [(set_attr "type" "ldwm")])
-
-(define_insn "*cdx_ldwm6_dec_wb_ret"
- [(match_parallel 0 "ldwm_operation"
- [(return)
- (set (match_operand:SI 7 "register_operand" "+&r")
- (plus:SI (match_dup 7) (const_int -24)))
- (set (match_operand:SI 1 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 7) (const_int -4))))
- (set (match_operand:SI 2 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 7) (const_int -8))))
- (set (match_operand:SI 3 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 7) (const_int -12))))
- (set (match_operand:SI 4 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 7) (const_int -16))))
- (set (match_operand:SI 5 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 7) (const_int -20))))
- (set (match_operand:SI 6 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 7) (const_int -24))))])]
- "TARGET_HAS_CDX && XVECLEN (operands[0], 0) == 8"
- "ldwm\\t{%1, %2, %3, %4, %5, %6}, --(%7), writeback, ret"
- [(set_attr "type" "ldwm")])
-
-(define_insn "*cdx_ldwm6_dec_wb"
- [(match_parallel 0 "ldwm_operation"
- [(set (match_operand:SI 7 "register_operand" "+&r")
- (plus:SI (match_dup 7) (const_int -24)))
- (set (match_operand:SI 1 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 7) (const_int -4))))
- (set (match_operand:SI 2 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 7) (const_int -8))))
- (set (match_operand:SI 3 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 7) (const_int -12))))
- (set (match_operand:SI 4 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 7) (const_int -16))))
- (set (match_operand:SI 5 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 7) (const_int -20))))
- (set (match_operand:SI 6 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 7) (const_int -24))))])]
- "TARGET_HAS_CDX && XVECLEN (operands[0], 0) == 7"
- "ldwm\\t{%1, %2, %3, %4, %5, %6}, --(%7), writeback"
- [(set_attr "type" "ldwm")])
-
-(define_insn "*cdx_ldwm6_dec_ret"
- [(match_parallel 0 "ldwm_operation"
- [(return)
- (set (match_operand:SI 1 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_operand:SI 7 "register_operand" "r") (const_int -4))))
- (set (match_operand:SI 2 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 7) (const_int -8))))
- (set (match_operand:SI 3 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 7) (const_int -12))))
- (set (match_operand:SI 4 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 7) (const_int -16))))
- (set (match_operand:SI 5 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 7) (const_int -20))))
- (set (match_operand:SI 6 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 7) (const_int -24))))])]
- "TARGET_HAS_CDX && XVECLEN (operands[0], 0) == 7"
- "ldwm\\t{%1, %2, %3, %4, %5, %6}, --(%7), ret"
- [(set_attr "type" "ldwm")])
-
-(define_insn "*cdx_ldwm6_dec"
- [(match_parallel 0 "ldwm_operation"
- [(set (match_operand:SI 1 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_operand:SI 7 "register_operand" "r") (const_int -4))))
- (set (match_operand:SI 2 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 7) (const_int -8))))
- (set (match_operand:SI 3 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 7) (const_int -12))))
- (set (match_operand:SI 4 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 7) (const_int -16))))
- (set (match_operand:SI 5 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 7) (const_int -20))))
- (set (match_operand:SI 6 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 7) (const_int -24))))])]
- "TARGET_HAS_CDX && XVECLEN (operands[0], 0) == 6"
- "ldwm\\t{%1, %2, %3, %4, %5, %6}, --(%7)"
- [(set_attr "type" "ldwm")])
-
-(define_insn "*cdx_ldwm7_inc_wb_ret"
- [(match_parallel 0 "ldwm_operation"
- [(return)
- (set (match_operand:SI 8 "register_operand" "+&r")
- (plus:SI (match_dup 8) (const_int 28)))
- (set (match_operand:SI 1 "nios2_hard_register_operand" "")
- (mem:SI (match_dup 8)))
- (set (match_operand:SI 2 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 8) (const_int 4))))
- (set (match_operand:SI 3 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 8) (const_int 8))))
- (set (match_operand:SI 4 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 8) (const_int 12))))
- (set (match_operand:SI 5 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 8) (const_int 16))))
- (set (match_operand:SI 6 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 8) (const_int 20))))
- (set (match_operand:SI 7 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 8) (const_int 24))))])]
- "TARGET_HAS_CDX && XVECLEN (operands[0], 0) == 9"
- "ldwm\\t{%1, %2, %3, %4, %5, %6, %7}, (%8)++, writeback, ret"
- [(set_attr "type" "ldwm")])
-
-(define_insn "*cdx_ldwm7_inc_wb"
- [(match_parallel 0 "ldwm_operation"
- [(set (match_operand:SI 8 "register_operand" "+&r")
- (plus:SI (match_dup 8) (const_int 28)))
- (set (match_operand:SI 1 "nios2_hard_register_operand" "")
- (mem:SI (match_dup 8)))
- (set (match_operand:SI 2 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 8) (const_int 4))))
- (set (match_operand:SI 3 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 8) (const_int 8))))
- (set (match_operand:SI 4 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 8) (const_int 12))))
- (set (match_operand:SI 5 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 8) (const_int 16))))
- (set (match_operand:SI 6 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 8) (const_int 20))))
- (set (match_operand:SI 7 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 8) (const_int 24))))])]
- "TARGET_HAS_CDX && XVECLEN (operands[0], 0) == 8"
- "ldwm\\t{%1, %2, %3, %4, %5, %6, %7}, (%8)++, writeback"
- [(set_attr "type" "ldwm")])
-
-(define_insn "*cdx_ldwm7_inc_ret"
- [(match_parallel 0 "ldwm_operation"
- [(return)
- (set (match_operand:SI 1 "nios2_hard_register_operand" "")
- (mem:SI (match_operand:SI 8 "register_operand" "r")))
- (set (match_operand:SI 2 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 8) (const_int 4))))
- (set (match_operand:SI 3 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 8) (const_int 8))))
- (set (match_operand:SI 4 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 8) (const_int 12))))
- (set (match_operand:SI 5 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 8) (const_int 16))))
- (set (match_operand:SI 6 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 8) (const_int 20))))
- (set (match_operand:SI 7 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 8) (const_int 24))))])]
- "TARGET_HAS_CDX && XVECLEN (operands[0], 0) == 8"
- "ldwm\\t{%1, %2, %3, %4, %5, %6, %7}, (%8)++, ret"
- [(set_attr "type" "ldwm")])
-
-(define_insn "*cdx_ldwm7_inc"
- [(match_parallel 0 "ldwm_operation"
- [(set (match_operand:SI 1 "nios2_hard_register_operand" "")
- (mem:SI (match_operand:SI 8 "register_operand" "r")))
- (set (match_operand:SI 2 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 8) (const_int 4))))
- (set (match_operand:SI 3 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 8) (const_int 8))))
- (set (match_operand:SI 4 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 8) (const_int 12))))
- (set (match_operand:SI 5 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 8) (const_int 16))))
- (set (match_operand:SI 6 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 8) (const_int 20))))
- (set (match_operand:SI 7 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 8) (const_int 24))))])]
- "TARGET_HAS_CDX && XVECLEN (operands[0], 0) == 7"
- "ldwm\\t{%1, %2, %3, %4, %5, %6, %7}, (%8)++"
- [(set_attr "type" "ldwm")])
-
-(define_insn "*cdx_ldwm7_dec_wb_ret"
- [(match_parallel 0 "ldwm_operation"
- [(return)
- (set (match_operand:SI 8 "register_operand" "+&r")
- (plus:SI (match_dup 8) (const_int -28)))
- (set (match_operand:SI 1 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 8) (const_int -4))))
- (set (match_operand:SI 2 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 8) (const_int -8))))
- (set (match_operand:SI 3 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 8) (const_int -12))))
- (set (match_operand:SI 4 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 8) (const_int -16))))
- (set (match_operand:SI 5 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 8) (const_int -20))))
- (set (match_operand:SI 6 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 8) (const_int -24))))
- (set (match_operand:SI 7 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 8) (const_int -28))))])]
- "TARGET_HAS_CDX && XVECLEN (operands[0], 0) == 9"
- "ldwm\\t{%1, %2, %3, %4, %5, %6, %7}, --(%8), writeback, ret"
- [(set_attr "type" "ldwm")])
-
-(define_insn "*cdx_ldwm7_dec_wb"
- [(match_parallel 0 "ldwm_operation"
- [(set (match_operand:SI 8 "register_operand" "+&r")
- (plus:SI (match_dup 8) (const_int -28)))
- (set (match_operand:SI 1 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 8) (const_int -4))))
- (set (match_operand:SI 2 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 8) (const_int -8))))
- (set (match_operand:SI 3 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 8) (const_int -12))))
- (set (match_operand:SI 4 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 8) (const_int -16))))
- (set (match_operand:SI 5 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 8) (const_int -20))))
- (set (match_operand:SI 6 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 8) (const_int -24))))
- (set (match_operand:SI 7 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 8) (const_int -28))))])]
- "TARGET_HAS_CDX && XVECLEN (operands[0], 0) == 8"
- "ldwm\\t{%1, %2, %3, %4, %5, %6, %7}, --(%8), writeback"
- [(set_attr "type" "ldwm")])
-
-(define_insn "*cdx_ldwm7_dec_ret"
- [(match_parallel 0 "ldwm_operation"
- [(return)
- (set (match_operand:SI 1 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_operand:SI 8 "register_operand" "r") (const_int -4))))
- (set (match_operand:SI 2 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 8) (const_int -8))))
- (set (match_operand:SI 3 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 8) (const_int -12))))
- (set (match_operand:SI 4 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 8) (const_int -16))))
- (set (match_operand:SI 5 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 8) (const_int -20))))
- (set (match_operand:SI 6 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 8) (const_int -24))))
- (set (match_operand:SI 7 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 8) (const_int -28))))])]
- "TARGET_HAS_CDX && XVECLEN (operands[0], 0) == 8"
- "ldwm\\t{%1, %2, %3, %4, %5, %6, %7}, --(%8), ret"
- [(set_attr "type" "ldwm")])
-
-(define_insn "*cdx_ldwm7_dec"
- [(match_parallel 0 "ldwm_operation"
- [(set (match_operand:SI 1 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_operand:SI 8 "register_operand" "r") (const_int -4))))
- (set (match_operand:SI 2 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 8) (const_int -8))))
- (set (match_operand:SI 3 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 8) (const_int -12))))
- (set (match_operand:SI 4 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 8) (const_int -16))))
- (set (match_operand:SI 5 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 8) (const_int -20))))
- (set (match_operand:SI 6 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 8) (const_int -24))))
- (set (match_operand:SI 7 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 8) (const_int -28))))])]
- "TARGET_HAS_CDX && XVECLEN (operands[0], 0) == 7"
- "ldwm\\t{%1, %2, %3, %4, %5, %6, %7}, --(%8)"
- [(set_attr "type" "ldwm")])
-
-(define_insn "*cdx_ldwm8_inc_wb_ret"
- [(match_parallel 0 "ldwm_operation"
- [(return)
- (set (match_operand:SI 9 "register_operand" "+&r")
- (plus:SI (match_dup 9) (const_int 32)))
- (set (match_operand:SI 1 "nios2_hard_register_operand" "")
- (mem:SI (match_dup 9)))
- (set (match_operand:SI 2 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 9) (const_int 4))))
- (set (match_operand:SI 3 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 9) (const_int 8))))
- (set (match_operand:SI 4 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 9) (const_int 12))))
- (set (match_operand:SI 5 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 9) (const_int 16))))
- (set (match_operand:SI 6 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 9) (const_int 20))))
- (set (match_operand:SI 7 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 9) (const_int 24))))
- (set (match_operand:SI 8 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 9) (const_int 28))))])]
- "TARGET_HAS_CDX && XVECLEN (operands[0], 0) == 10"
- "ldwm\\t{%1, %2, %3, %4, %5, %6, %7, %8}, (%9)++, writeback, ret"
- [(set_attr "type" "ldwm")])
-
-(define_insn "*cdx_ldwm8_inc_wb"
- [(match_parallel 0 "ldwm_operation"
- [(set (match_operand:SI 9 "register_operand" "+&r")
- (plus:SI (match_dup 9) (const_int 32)))
- (set (match_operand:SI 1 "nios2_hard_register_operand" "")
- (mem:SI (match_dup 9)))
- (set (match_operand:SI 2 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 9) (const_int 4))))
- (set (match_operand:SI 3 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 9) (const_int 8))))
- (set (match_operand:SI 4 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 9) (const_int 12))))
- (set (match_operand:SI 5 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 9) (const_int 16))))
- (set (match_operand:SI 6 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 9) (const_int 20))))
- (set (match_operand:SI 7 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 9) (const_int 24))))
- (set (match_operand:SI 8 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 9) (const_int 28))))])]
- "TARGET_HAS_CDX && XVECLEN (operands[0], 0) == 9"
- "ldwm\\t{%1, %2, %3, %4, %5, %6, %7, %8}, (%9)++, writeback"
- [(set_attr "type" "ldwm")])
-
-(define_insn "*cdx_ldwm8_inc_ret"
- [(match_parallel 0 "ldwm_operation"
- [(return)
- (set (match_operand:SI 1 "nios2_hard_register_operand" "")
- (mem:SI (match_operand:SI 9 "register_operand" "r")))
- (set (match_operand:SI 2 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 9) (const_int 4))))
- (set (match_operand:SI 3 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 9) (const_int 8))))
- (set (match_operand:SI 4 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 9) (const_int 12))))
- (set (match_operand:SI 5 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 9) (const_int 16))))
- (set (match_operand:SI 6 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 9) (const_int 20))))
- (set (match_operand:SI 7 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 9) (const_int 24))))
- (set (match_operand:SI 8 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 9) (const_int 28))))])]
- "TARGET_HAS_CDX && XVECLEN (operands[0], 0) == 9"
- "ldwm\\t{%1, %2, %3, %4, %5, %6, %7, %8}, (%9)++, ret"
- [(set_attr "type" "ldwm")])
-
-(define_insn "*cdx_ldwm8_inc"
- [(match_parallel 0 "ldwm_operation"
- [(set (match_operand:SI 1 "nios2_hard_register_operand" "")
- (mem:SI (match_operand:SI 9 "register_operand" "r")))
- (set (match_operand:SI 2 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 9) (const_int 4))))
- (set (match_operand:SI 3 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 9) (const_int 8))))
- (set (match_operand:SI 4 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 9) (const_int 12))))
- (set (match_operand:SI 5 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 9) (const_int 16))))
- (set (match_operand:SI 6 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 9) (const_int 20))))
- (set (match_operand:SI 7 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 9) (const_int 24))))
- (set (match_operand:SI 8 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 9) (const_int 28))))])]
- "TARGET_HAS_CDX && XVECLEN (operands[0], 0) == 8"
- "ldwm\\t{%1, %2, %3, %4, %5, %6, %7, %8}, (%9)++"
- [(set_attr "type" "ldwm")])
-
-(define_insn "*cdx_ldwm8_dec_wb_ret"
- [(match_parallel 0 "ldwm_operation"
- [(return)
- (set (match_operand:SI 9 "register_operand" "+&r")
- (plus:SI (match_dup 9) (const_int -32)))
- (set (match_operand:SI 1 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 9) (const_int -4))))
- (set (match_operand:SI 2 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 9) (const_int -8))))
- (set (match_operand:SI 3 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 9) (const_int -12))))
- (set (match_operand:SI 4 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 9) (const_int -16))))
- (set (match_operand:SI 5 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 9) (const_int -20))))
- (set (match_operand:SI 6 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 9) (const_int -24))))
- (set (match_operand:SI 7 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 9) (const_int -28))))
- (set (match_operand:SI 8 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 9) (const_int -32))))])]
- "TARGET_HAS_CDX && XVECLEN (operands[0], 0) == 10"
- "ldwm\\t{%1, %2, %3, %4, %5, %6, %7, %8}, --(%9), writeback, ret"
- [(set_attr "type" "ldwm")])
-
-(define_insn "*cdx_ldwm8_dec_wb"
- [(match_parallel 0 "ldwm_operation"
- [(set (match_operand:SI 9 "register_operand" "+&r")
- (plus:SI (match_dup 9) (const_int -32)))
- (set (match_operand:SI 1 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 9) (const_int -4))))
- (set (match_operand:SI 2 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 9) (const_int -8))))
- (set (match_operand:SI 3 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 9) (const_int -12))))
- (set (match_operand:SI 4 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 9) (const_int -16))))
- (set (match_operand:SI 5 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 9) (const_int -20))))
- (set (match_operand:SI 6 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 9) (const_int -24))))
- (set (match_operand:SI 7 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 9) (const_int -28))))
- (set (match_operand:SI 8 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 9) (const_int -32))))])]
- "TARGET_HAS_CDX && XVECLEN (operands[0], 0) == 9"
- "ldwm\\t{%1, %2, %3, %4, %5, %6, %7, %8}, --(%9), writeback"
- [(set_attr "type" "ldwm")])
-
-(define_insn "*cdx_ldwm8_dec_ret"
- [(match_parallel 0 "ldwm_operation"
- [(return)
- (set (match_operand:SI 1 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_operand:SI 9 "register_operand" "r") (const_int -4))))
- (set (match_operand:SI 2 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 9) (const_int -8))))
- (set (match_operand:SI 3 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 9) (const_int -12))))
- (set (match_operand:SI 4 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 9) (const_int -16))))
- (set (match_operand:SI 5 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 9) (const_int -20))))
- (set (match_operand:SI 6 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 9) (const_int -24))))
- (set (match_operand:SI 7 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 9) (const_int -28))))
- (set (match_operand:SI 8 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 9) (const_int -32))))])]
- "TARGET_HAS_CDX && XVECLEN (operands[0], 0) == 9"
- "ldwm\\t{%1, %2, %3, %4, %5, %6, %7, %8}, --(%9), ret"
- [(set_attr "type" "ldwm")])
-
-(define_insn "*cdx_ldwm8_dec"
- [(match_parallel 0 "ldwm_operation"
- [(set (match_operand:SI 1 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_operand:SI 9 "register_operand" "r") (const_int -4))))
- (set (match_operand:SI 2 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 9) (const_int -8))))
- (set (match_operand:SI 3 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 9) (const_int -12))))
- (set (match_operand:SI 4 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 9) (const_int -16))))
- (set (match_operand:SI 5 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 9) (const_int -20))))
- (set (match_operand:SI 6 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 9) (const_int -24))))
- (set (match_operand:SI 7 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 9) (const_int -28))))
- (set (match_operand:SI 8 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 9) (const_int -32))))])]
- "TARGET_HAS_CDX && XVECLEN (operands[0], 0) == 8"
- "ldwm\\t{%1, %2, %3, %4, %5, %6, %7, %8}, --(%9)"
- [(set_attr "type" "ldwm")])
-
-(define_insn "*cdx_ldwm9_inc_wb_ret"
- [(match_parallel 0 "ldwm_operation"
- [(return)
- (set (match_operand:SI 10 "register_operand" "+&r")
- (plus:SI (match_dup 10) (const_int 36)))
- (set (match_operand:SI 1 "nios2_hard_register_operand" "")
- (mem:SI (match_dup 10)))
- (set (match_operand:SI 2 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 10) (const_int 4))))
- (set (match_operand:SI 3 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 10) (const_int 8))))
- (set (match_operand:SI 4 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 10) (const_int 12))))
- (set (match_operand:SI 5 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 10) (const_int 16))))
- (set (match_operand:SI 6 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 10) (const_int 20))))
- (set (match_operand:SI 7 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 10) (const_int 24))))
- (set (match_operand:SI 8 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 10) (const_int 28))))
- (set (match_operand:SI 9 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 10) (const_int 32))))])]
- "TARGET_HAS_CDX && XVECLEN (operands[0], 0) == 11"
- "ldwm\\t{%1, %2, %3, %4, %5, %6, %7, %8, %9}, (%10)++, writeback, ret"
- [(set_attr "type" "ldwm")])
-
-(define_insn "*cdx_ldwm9_inc_wb"
- [(match_parallel 0 "ldwm_operation"
- [(set (match_operand:SI 10 "register_operand" "+&r")
- (plus:SI (match_dup 10) (const_int 36)))
- (set (match_operand:SI 1 "nios2_hard_register_operand" "")
- (mem:SI (match_dup 10)))
- (set (match_operand:SI 2 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 10) (const_int 4))))
- (set (match_operand:SI 3 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 10) (const_int 8))))
- (set (match_operand:SI 4 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 10) (const_int 12))))
- (set (match_operand:SI 5 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 10) (const_int 16))))
- (set (match_operand:SI 6 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 10) (const_int 20))))
- (set (match_operand:SI 7 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 10) (const_int 24))))
- (set (match_operand:SI 8 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 10) (const_int 28))))
- (set (match_operand:SI 9 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 10) (const_int 32))))])]
- "TARGET_HAS_CDX && XVECLEN (operands[0], 0) == 10"
- "ldwm\\t{%1, %2, %3, %4, %5, %6, %7, %8, %9}, (%10)++, writeback"
- [(set_attr "type" "ldwm")])
-
-(define_insn "*cdx_ldwm9_inc_ret"
- [(match_parallel 0 "ldwm_operation"
- [(return)
- (set (match_operand:SI 1 "nios2_hard_register_operand" "")
- (mem:SI (match_operand:SI 10 "register_operand" "r")))
- (set (match_operand:SI 2 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 10) (const_int 4))))
- (set (match_operand:SI 3 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 10) (const_int 8))))
- (set (match_operand:SI 4 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 10) (const_int 12))))
- (set (match_operand:SI 5 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 10) (const_int 16))))
- (set (match_operand:SI 6 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 10) (const_int 20))))
- (set (match_operand:SI 7 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 10) (const_int 24))))
- (set (match_operand:SI 8 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 10) (const_int 28))))
- (set (match_operand:SI 9 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 10) (const_int 32))))])]
- "TARGET_HAS_CDX && XVECLEN (operands[0], 0) == 10"
- "ldwm\\t{%1, %2, %3, %4, %5, %6, %7, %8, %9}, (%10)++, ret"
- [(set_attr "type" "ldwm")])
-
-(define_insn "*cdx_ldwm9_inc"
- [(match_parallel 0 "ldwm_operation"
- [(set (match_operand:SI 1 "nios2_hard_register_operand" "")
- (mem:SI (match_operand:SI 10 "register_operand" "r")))
- (set (match_operand:SI 2 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 10) (const_int 4))))
- (set (match_operand:SI 3 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 10) (const_int 8))))
- (set (match_operand:SI 4 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 10) (const_int 12))))
- (set (match_operand:SI 5 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 10) (const_int 16))))
- (set (match_operand:SI 6 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 10) (const_int 20))))
- (set (match_operand:SI 7 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 10) (const_int 24))))
- (set (match_operand:SI 8 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 10) (const_int 28))))
- (set (match_operand:SI 9 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 10) (const_int 32))))])]
- "TARGET_HAS_CDX && XVECLEN (operands[0], 0) == 9"
- "ldwm\\t{%1, %2, %3, %4, %5, %6, %7, %8, %9}, (%10)++"
- [(set_attr "type" "ldwm")])
-
-(define_insn "*cdx_ldwm9_dec_wb_ret"
- [(match_parallel 0 "ldwm_operation"
- [(return)
- (set (match_operand:SI 10 "register_operand" "+&r")
- (plus:SI (match_dup 10) (const_int -36)))
- (set (match_operand:SI 1 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 10) (const_int -4))))
- (set (match_operand:SI 2 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 10) (const_int -8))))
- (set (match_operand:SI 3 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 10) (const_int -12))))
- (set (match_operand:SI 4 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 10) (const_int -16))))
- (set (match_operand:SI 5 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 10) (const_int -20))))
- (set (match_operand:SI 6 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 10) (const_int -24))))
- (set (match_operand:SI 7 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 10) (const_int -28))))
- (set (match_operand:SI 8 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 10) (const_int -32))))
- (set (match_operand:SI 9 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 10) (const_int -36))))])]
- "TARGET_HAS_CDX && XVECLEN (operands[0], 0) == 11"
- "ldwm\\t{%1, %2, %3, %4, %5, %6, %7, %8, %9}, --(%10), writeback, ret"
- [(set_attr "type" "ldwm")])
-
-(define_insn "*cdx_ldwm9_dec_wb"
- [(match_parallel 0 "ldwm_operation"
- [(set (match_operand:SI 10 "register_operand" "+&r")
- (plus:SI (match_dup 10) (const_int -36)))
- (set (match_operand:SI 1 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 10) (const_int -4))))
- (set (match_operand:SI 2 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 10) (const_int -8))))
- (set (match_operand:SI 3 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 10) (const_int -12))))
- (set (match_operand:SI 4 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 10) (const_int -16))))
- (set (match_operand:SI 5 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 10) (const_int -20))))
- (set (match_operand:SI 6 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 10) (const_int -24))))
- (set (match_operand:SI 7 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 10) (const_int -28))))
- (set (match_operand:SI 8 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 10) (const_int -32))))
- (set (match_operand:SI 9 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 10) (const_int -36))))])]
- "TARGET_HAS_CDX && XVECLEN (operands[0], 0) == 10"
- "ldwm\\t{%1, %2, %3, %4, %5, %6, %7, %8, %9}, --(%10), writeback"
- [(set_attr "type" "ldwm")])
-
-(define_insn "*cdx_ldwm9_dec_ret"
- [(match_parallel 0 "ldwm_operation"
- [(return)
- (set (match_operand:SI 1 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_operand:SI 10 "register_operand" "r") (const_int -4))))
- (set (match_operand:SI 2 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 10) (const_int -8))))
- (set (match_operand:SI 3 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 10) (const_int -12))))
- (set (match_operand:SI 4 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 10) (const_int -16))))
- (set (match_operand:SI 5 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 10) (const_int -20))))
- (set (match_operand:SI 6 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 10) (const_int -24))))
- (set (match_operand:SI 7 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 10) (const_int -28))))
- (set (match_operand:SI 8 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 10) (const_int -32))))
- (set (match_operand:SI 9 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 10) (const_int -36))))])]
- "TARGET_HAS_CDX && XVECLEN (operands[0], 0) == 10"
- "ldwm\\t{%1, %2, %3, %4, %5, %6, %7, %8, %9}, --(%10), ret"
- [(set_attr "type" "ldwm")])
-
-(define_insn "*cdx_ldwm9_dec"
- [(match_parallel 0 "ldwm_operation"
- [(set (match_operand:SI 1 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_operand:SI 10 "register_operand" "r") (const_int -4))))
- (set (match_operand:SI 2 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 10) (const_int -8))))
- (set (match_operand:SI 3 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 10) (const_int -12))))
- (set (match_operand:SI 4 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 10) (const_int -16))))
- (set (match_operand:SI 5 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 10) (const_int -20))))
- (set (match_operand:SI 6 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 10) (const_int -24))))
- (set (match_operand:SI 7 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 10) (const_int -28))))
- (set (match_operand:SI 8 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 10) (const_int -32))))
- (set (match_operand:SI 9 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 10) (const_int -36))))])]
- "TARGET_HAS_CDX && XVECLEN (operands[0], 0) == 9"
- "ldwm\\t{%1, %2, %3, %4, %5, %6, %7, %8, %9}, --(%10)"
- [(set_attr "type" "ldwm")])
-
-(define_insn "*cdx_ldwm10_inc_wb_ret"
- [(match_parallel 0 "ldwm_operation"
- [(return)
- (set (match_operand:SI 11 "register_operand" "+&r")
- (plus:SI (match_dup 11) (const_int 40)))
- (set (match_operand:SI 1 "nios2_hard_register_operand" "")
- (mem:SI (match_dup 11)))
- (set (match_operand:SI 2 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 11) (const_int 4))))
- (set (match_operand:SI 3 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 11) (const_int 8))))
- (set (match_operand:SI 4 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 11) (const_int 12))))
- (set (match_operand:SI 5 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 11) (const_int 16))))
- (set (match_operand:SI 6 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 11) (const_int 20))))
- (set (match_operand:SI 7 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 11) (const_int 24))))
- (set (match_operand:SI 8 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 11) (const_int 28))))
- (set (match_operand:SI 9 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 11) (const_int 32))))
- (set (match_operand:SI 10 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 11) (const_int 36))))])]
- "TARGET_HAS_CDX && XVECLEN (operands[0], 0) == 12"
- "ldwm\\t{%1, %2, %3, %4, %5, %6, %7, %8, %9, %10}, (%11)++, writeback, ret"
- [(set_attr "type" "ldwm")])
-
-(define_insn "*cdx_ldwm10_inc_wb"
- [(match_parallel 0 "ldwm_operation"
- [(set (match_operand:SI 11 "register_operand" "+&r")
- (plus:SI (match_dup 11) (const_int 40)))
- (set (match_operand:SI 1 "nios2_hard_register_operand" "")
- (mem:SI (match_dup 11)))
- (set (match_operand:SI 2 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 11) (const_int 4))))
- (set (match_operand:SI 3 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 11) (const_int 8))))
- (set (match_operand:SI 4 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 11) (const_int 12))))
- (set (match_operand:SI 5 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 11) (const_int 16))))
- (set (match_operand:SI 6 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 11) (const_int 20))))
- (set (match_operand:SI 7 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 11) (const_int 24))))
- (set (match_operand:SI 8 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 11) (const_int 28))))
- (set (match_operand:SI 9 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 11) (const_int 32))))
- (set (match_operand:SI 10 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 11) (const_int 36))))])]
- "TARGET_HAS_CDX && XVECLEN (operands[0], 0) == 11"
- "ldwm\\t{%1, %2, %3, %4, %5, %6, %7, %8, %9, %10}, (%11)++, writeback"
- [(set_attr "type" "ldwm")])
-
-(define_insn "*cdx_ldwm10_inc_ret"
- [(match_parallel 0 "ldwm_operation"
- [(return)
- (set (match_operand:SI 1 "nios2_hard_register_operand" "")
- (mem:SI (match_operand:SI 11 "register_operand" "r")))
- (set (match_operand:SI 2 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 11) (const_int 4))))
- (set (match_operand:SI 3 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 11) (const_int 8))))
- (set (match_operand:SI 4 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 11) (const_int 12))))
- (set (match_operand:SI 5 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 11) (const_int 16))))
- (set (match_operand:SI 6 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 11) (const_int 20))))
- (set (match_operand:SI 7 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 11) (const_int 24))))
- (set (match_operand:SI 8 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 11) (const_int 28))))
- (set (match_operand:SI 9 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 11) (const_int 32))))
- (set (match_operand:SI 10 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 11) (const_int 36))))])]
- "TARGET_HAS_CDX && XVECLEN (operands[0], 0) == 11"
- "ldwm\\t{%1, %2, %3, %4, %5, %6, %7, %8, %9, %10}, (%11)++, ret"
- [(set_attr "type" "ldwm")])
-
-(define_insn "*cdx_ldwm10_inc"
- [(match_parallel 0 "ldwm_operation"
- [(set (match_operand:SI 1 "nios2_hard_register_operand" "")
- (mem:SI (match_operand:SI 11 "register_operand" "r")))
- (set (match_operand:SI 2 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 11) (const_int 4))))
- (set (match_operand:SI 3 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 11) (const_int 8))))
- (set (match_operand:SI 4 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 11) (const_int 12))))
- (set (match_operand:SI 5 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 11) (const_int 16))))
- (set (match_operand:SI 6 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 11) (const_int 20))))
- (set (match_operand:SI 7 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 11) (const_int 24))))
- (set (match_operand:SI 8 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 11) (const_int 28))))
- (set (match_operand:SI 9 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 11) (const_int 32))))
- (set (match_operand:SI 10 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 11) (const_int 36))))])]
- "TARGET_HAS_CDX && XVECLEN (operands[0], 0) == 10"
- "ldwm\\t{%1, %2, %3, %4, %5, %6, %7, %8, %9, %10}, (%11)++"
- [(set_attr "type" "ldwm")])
-
-(define_insn "*cdx_ldwm10_dec_wb_ret"
- [(match_parallel 0 "ldwm_operation"
- [(return)
- (set (match_operand:SI 11 "register_operand" "+&r")
- (plus:SI (match_dup 11) (const_int -40)))
- (set (match_operand:SI 1 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 11) (const_int -4))))
- (set (match_operand:SI 2 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 11) (const_int -8))))
- (set (match_operand:SI 3 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 11) (const_int -12))))
- (set (match_operand:SI 4 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 11) (const_int -16))))
- (set (match_operand:SI 5 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 11) (const_int -20))))
- (set (match_operand:SI 6 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 11) (const_int -24))))
- (set (match_operand:SI 7 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 11) (const_int -28))))
- (set (match_operand:SI 8 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 11) (const_int -32))))
- (set (match_operand:SI 9 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 11) (const_int -36))))
- (set (match_operand:SI 10 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 11) (const_int -40))))])]
- "TARGET_HAS_CDX && XVECLEN (operands[0], 0) == 12"
- "ldwm\\t{%1, %2, %3, %4, %5, %6, %7, %8, %9, %10}, --(%11), writeback, ret"
- [(set_attr "type" "ldwm")])
-
-(define_insn "*cdx_ldwm10_dec_wb"
- [(match_parallel 0 "ldwm_operation"
- [(set (match_operand:SI 11 "register_operand" "+&r")
- (plus:SI (match_dup 11) (const_int -40)))
- (set (match_operand:SI 1 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 11) (const_int -4))))
- (set (match_operand:SI 2 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 11) (const_int -8))))
- (set (match_operand:SI 3 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 11) (const_int -12))))
- (set (match_operand:SI 4 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 11) (const_int -16))))
- (set (match_operand:SI 5 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 11) (const_int -20))))
- (set (match_operand:SI 6 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 11) (const_int -24))))
- (set (match_operand:SI 7 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 11) (const_int -28))))
- (set (match_operand:SI 8 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 11) (const_int -32))))
- (set (match_operand:SI 9 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 11) (const_int -36))))
- (set (match_operand:SI 10 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 11) (const_int -40))))])]
- "TARGET_HAS_CDX && XVECLEN (operands[0], 0) == 11"
- "ldwm\\t{%1, %2, %3, %4, %5, %6, %7, %8, %9, %10}, --(%11), writeback"
- [(set_attr "type" "ldwm")])
-
-(define_insn "*cdx_ldwm10_dec_ret"
- [(match_parallel 0 "ldwm_operation"
- [(return)
- (set (match_operand:SI 1 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_operand:SI 11 "register_operand" "r") (const_int -4))))
- (set (match_operand:SI 2 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 11) (const_int -8))))
- (set (match_operand:SI 3 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 11) (const_int -12))))
- (set (match_operand:SI 4 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 11) (const_int -16))))
- (set (match_operand:SI 5 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 11) (const_int -20))))
- (set (match_operand:SI 6 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 11) (const_int -24))))
- (set (match_operand:SI 7 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 11) (const_int -28))))
- (set (match_operand:SI 8 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 11) (const_int -32))))
- (set (match_operand:SI 9 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 11) (const_int -36))))
- (set (match_operand:SI 10 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 11) (const_int -40))))])]
- "TARGET_HAS_CDX && XVECLEN (operands[0], 0) == 11"
- "ldwm\\t{%1, %2, %3, %4, %5, %6, %7, %8, %9, %10}, --(%11), ret"
- [(set_attr "type" "ldwm")])
-
-(define_insn "*cdx_ldwm10_dec"
- [(match_parallel 0 "ldwm_operation"
- [(set (match_operand:SI 1 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_operand:SI 11 "register_operand" "r") (const_int -4))))
- (set (match_operand:SI 2 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 11) (const_int -8))))
- (set (match_operand:SI 3 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 11) (const_int -12))))
- (set (match_operand:SI 4 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 11) (const_int -16))))
- (set (match_operand:SI 5 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 11) (const_int -20))))
- (set (match_operand:SI 6 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 11) (const_int -24))))
- (set (match_operand:SI 7 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 11) (const_int -28))))
- (set (match_operand:SI 8 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 11) (const_int -32))))
- (set (match_operand:SI 9 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 11) (const_int -36))))
- (set (match_operand:SI 10 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 11) (const_int -40))))])]
- "TARGET_HAS_CDX && XVECLEN (operands[0], 0) == 10"
- "ldwm\\t{%1, %2, %3, %4, %5, %6, %7, %8, %9, %10}, --(%11)"
- [(set_attr "type" "ldwm")])
-
-(define_insn "*cdx_ldwm11_inc_wb_ret"
- [(match_parallel 0 "ldwm_operation"
- [(return)
- (set (match_operand:SI 12 "register_operand" "+&r")
- (plus:SI (match_dup 12) (const_int 44)))
- (set (match_operand:SI 1 "nios2_hard_register_operand" "")
- (mem:SI (match_dup 12)))
- (set (match_operand:SI 2 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 12) (const_int 4))))
- (set (match_operand:SI 3 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 12) (const_int 8))))
- (set (match_operand:SI 4 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 12) (const_int 12))))
- (set (match_operand:SI 5 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 12) (const_int 16))))
- (set (match_operand:SI 6 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 12) (const_int 20))))
- (set (match_operand:SI 7 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 12) (const_int 24))))
- (set (match_operand:SI 8 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 12) (const_int 28))))
- (set (match_operand:SI 9 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 12) (const_int 32))))
- (set (match_operand:SI 10 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 12) (const_int 36))))
- (set (match_operand:SI 11 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 12) (const_int 40))))])]
- "TARGET_HAS_CDX && XVECLEN (operands[0], 0) == 13"
- "ldwm\\t{%1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11}, (%12)++, writeback, ret"
- [(set_attr "type" "ldwm")])
-
-(define_insn "*cdx_ldwm11_inc_wb"
- [(match_parallel 0 "ldwm_operation"
- [(set (match_operand:SI 12 "register_operand" "+&r")
- (plus:SI (match_dup 12) (const_int 44)))
- (set (match_operand:SI 1 "nios2_hard_register_operand" "")
- (mem:SI (match_dup 12)))
- (set (match_operand:SI 2 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 12) (const_int 4))))
- (set (match_operand:SI 3 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 12) (const_int 8))))
- (set (match_operand:SI 4 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 12) (const_int 12))))
- (set (match_operand:SI 5 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 12) (const_int 16))))
- (set (match_operand:SI 6 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 12) (const_int 20))))
- (set (match_operand:SI 7 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 12) (const_int 24))))
- (set (match_operand:SI 8 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 12) (const_int 28))))
- (set (match_operand:SI 9 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 12) (const_int 32))))
- (set (match_operand:SI 10 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 12) (const_int 36))))
- (set (match_operand:SI 11 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 12) (const_int 40))))])]
- "TARGET_HAS_CDX && XVECLEN (operands[0], 0) == 12"
- "ldwm\\t{%1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11}, (%12)++, writeback"
- [(set_attr "type" "ldwm")])
-
-(define_insn "*cdx_ldwm11_inc_ret"
- [(match_parallel 0 "ldwm_operation"
- [(return)
- (set (match_operand:SI 1 "nios2_hard_register_operand" "")
- (mem:SI (match_operand:SI 12 "register_operand" "r")))
- (set (match_operand:SI 2 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 12) (const_int 4))))
- (set (match_operand:SI 3 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 12) (const_int 8))))
- (set (match_operand:SI 4 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 12) (const_int 12))))
- (set (match_operand:SI 5 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 12) (const_int 16))))
- (set (match_operand:SI 6 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 12) (const_int 20))))
- (set (match_operand:SI 7 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 12) (const_int 24))))
- (set (match_operand:SI 8 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 12) (const_int 28))))
- (set (match_operand:SI 9 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 12) (const_int 32))))
- (set (match_operand:SI 10 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 12) (const_int 36))))
- (set (match_operand:SI 11 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 12) (const_int 40))))])]
- "TARGET_HAS_CDX && XVECLEN (operands[0], 0) == 12"
- "ldwm\\t{%1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11}, (%12)++, ret"
- [(set_attr "type" "ldwm")])
-
-(define_insn "*cdx_ldwm11_inc"
- [(match_parallel 0 "ldwm_operation"
- [(set (match_operand:SI 1 "nios2_hard_register_operand" "")
- (mem:SI (match_operand:SI 12 "register_operand" "r")))
- (set (match_operand:SI 2 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 12) (const_int 4))))
- (set (match_operand:SI 3 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 12) (const_int 8))))
- (set (match_operand:SI 4 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 12) (const_int 12))))
- (set (match_operand:SI 5 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 12) (const_int 16))))
- (set (match_operand:SI 6 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 12) (const_int 20))))
- (set (match_operand:SI 7 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 12) (const_int 24))))
- (set (match_operand:SI 8 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 12) (const_int 28))))
- (set (match_operand:SI 9 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 12) (const_int 32))))
- (set (match_operand:SI 10 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 12) (const_int 36))))
- (set (match_operand:SI 11 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 12) (const_int 40))))])]
- "TARGET_HAS_CDX && XVECLEN (operands[0], 0) == 11"
- "ldwm\\t{%1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11}, (%12)++"
- [(set_attr "type" "ldwm")])
-
-(define_insn "*cdx_ldwm11_dec_wb_ret"
- [(match_parallel 0 "ldwm_operation"
- [(return)
- (set (match_operand:SI 12 "register_operand" "+&r")
- (plus:SI (match_dup 12) (const_int -44)))
- (set (match_operand:SI 1 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 12) (const_int -4))))
- (set (match_operand:SI 2 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 12) (const_int -8))))
- (set (match_operand:SI 3 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 12) (const_int -12))))
- (set (match_operand:SI 4 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 12) (const_int -16))))
- (set (match_operand:SI 5 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 12) (const_int -20))))
- (set (match_operand:SI 6 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 12) (const_int -24))))
- (set (match_operand:SI 7 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 12) (const_int -28))))
- (set (match_operand:SI 8 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 12) (const_int -32))))
- (set (match_operand:SI 9 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 12) (const_int -36))))
- (set (match_operand:SI 10 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 12) (const_int -40))))
- (set (match_operand:SI 11 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 12) (const_int -44))))])]
- "TARGET_HAS_CDX && XVECLEN (operands[0], 0) == 13"
- "ldwm\\t{%1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11}, --(%12), writeback, ret"
- [(set_attr "type" "ldwm")])
-
-(define_insn "*cdx_ldwm11_dec_wb"
- [(match_parallel 0 "ldwm_operation"
- [(set (match_operand:SI 12 "register_operand" "+&r")
- (plus:SI (match_dup 12) (const_int -44)))
- (set (match_operand:SI 1 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 12) (const_int -4))))
- (set (match_operand:SI 2 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 12) (const_int -8))))
- (set (match_operand:SI 3 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 12) (const_int -12))))
- (set (match_operand:SI 4 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 12) (const_int -16))))
- (set (match_operand:SI 5 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 12) (const_int -20))))
- (set (match_operand:SI 6 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 12) (const_int -24))))
- (set (match_operand:SI 7 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 12) (const_int -28))))
- (set (match_operand:SI 8 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 12) (const_int -32))))
- (set (match_operand:SI 9 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 12) (const_int -36))))
- (set (match_operand:SI 10 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 12) (const_int -40))))
- (set (match_operand:SI 11 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 12) (const_int -44))))])]
- "TARGET_HAS_CDX && XVECLEN (operands[0], 0) == 12"
- "ldwm\\t{%1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11}, --(%12), writeback"
- [(set_attr "type" "ldwm")])
-
-(define_insn "*cdx_ldwm11_dec_ret"
- [(match_parallel 0 "ldwm_operation"
- [(return)
- (set (match_operand:SI 1 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_operand:SI 12 "register_operand" "r") (const_int -4))))
- (set (match_operand:SI 2 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 12) (const_int -8))))
- (set (match_operand:SI 3 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 12) (const_int -12))))
- (set (match_operand:SI 4 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 12) (const_int -16))))
- (set (match_operand:SI 5 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 12) (const_int -20))))
- (set (match_operand:SI 6 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 12) (const_int -24))))
- (set (match_operand:SI 7 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 12) (const_int -28))))
- (set (match_operand:SI 8 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 12) (const_int -32))))
- (set (match_operand:SI 9 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 12) (const_int -36))))
- (set (match_operand:SI 10 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 12) (const_int -40))))
- (set (match_operand:SI 11 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 12) (const_int -44))))])]
- "TARGET_HAS_CDX && XVECLEN (operands[0], 0) == 12"
- "ldwm\\t{%1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11}, --(%12), ret"
- [(set_attr "type" "ldwm")])
-
-(define_insn "*cdx_ldwm11_dec"
- [(match_parallel 0 "ldwm_operation"
- [(set (match_operand:SI 1 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_operand:SI 12 "register_operand" "r") (const_int -4))))
- (set (match_operand:SI 2 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 12) (const_int -8))))
- (set (match_operand:SI 3 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 12) (const_int -12))))
- (set (match_operand:SI 4 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 12) (const_int -16))))
- (set (match_operand:SI 5 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 12) (const_int -20))))
- (set (match_operand:SI 6 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 12) (const_int -24))))
- (set (match_operand:SI 7 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 12) (const_int -28))))
- (set (match_operand:SI 8 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 12) (const_int -32))))
- (set (match_operand:SI 9 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 12) (const_int -36))))
- (set (match_operand:SI 10 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 12) (const_int -40))))
- (set (match_operand:SI 11 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 12) (const_int -44))))])]
- "TARGET_HAS_CDX && XVECLEN (operands[0], 0) == 11"
- "ldwm\\t{%1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11}, --(%12)"
- [(set_attr "type" "ldwm")])
-
-(define_insn "*cdx_ldwm12_inc_wb_ret"
- [(match_parallel 0 "ldwm_operation"
- [(return)
- (set (match_operand:SI 13 "register_operand" "+&r")
- (plus:SI (match_dup 13) (const_int 48)))
- (set (match_operand:SI 1 "nios2_hard_register_operand" "")
- (mem:SI (match_dup 13)))
- (set (match_operand:SI 2 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 13) (const_int 4))))
- (set (match_operand:SI 3 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 13) (const_int 8))))
- (set (match_operand:SI 4 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 13) (const_int 12))))
- (set (match_operand:SI 5 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 13) (const_int 16))))
- (set (match_operand:SI 6 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 13) (const_int 20))))
- (set (match_operand:SI 7 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 13) (const_int 24))))
- (set (match_operand:SI 8 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 13) (const_int 28))))
- (set (match_operand:SI 9 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 13) (const_int 32))))
- (set (match_operand:SI 10 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 13) (const_int 36))))
- (set (match_operand:SI 11 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 13) (const_int 40))))
- (set (match_operand:SI 12 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 13) (const_int 44))))])]
- "TARGET_HAS_CDX && XVECLEN (operands[0], 0) == 14"
- "ldwm\\t{%1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12}, (%13)++, writeback, ret"
- [(set_attr "type" "ldwm")])
-
-(define_insn "*cdx_ldwm12_inc_wb"
- [(match_parallel 0 "ldwm_operation"
- [(set (match_operand:SI 13 "register_operand" "+&r")
- (plus:SI (match_dup 13) (const_int 48)))
- (set (match_operand:SI 1 "nios2_hard_register_operand" "")
- (mem:SI (match_dup 13)))
- (set (match_operand:SI 2 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 13) (const_int 4))))
- (set (match_operand:SI 3 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 13) (const_int 8))))
- (set (match_operand:SI 4 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 13) (const_int 12))))
- (set (match_operand:SI 5 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 13) (const_int 16))))
- (set (match_operand:SI 6 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 13) (const_int 20))))
- (set (match_operand:SI 7 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 13) (const_int 24))))
- (set (match_operand:SI 8 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 13) (const_int 28))))
- (set (match_operand:SI 9 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 13) (const_int 32))))
- (set (match_operand:SI 10 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 13) (const_int 36))))
- (set (match_operand:SI 11 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 13) (const_int 40))))
- (set (match_operand:SI 12 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 13) (const_int 44))))])]
- "TARGET_HAS_CDX && XVECLEN (operands[0], 0) == 13"
- "ldwm\\t{%1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12}, (%13)++, writeback"
- [(set_attr "type" "ldwm")])
-
-(define_insn "*cdx_ldwm12_inc_ret"
- [(match_parallel 0 "ldwm_operation"
- [(return)
- (set (match_operand:SI 1 "nios2_hard_register_operand" "")
- (mem:SI (match_operand:SI 13 "register_operand" "r")))
- (set (match_operand:SI 2 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 13) (const_int 4))))
- (set (match_operand:SI 3 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 13) (const_int 8))))
- (set (match_operand:SI 4 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 13) (const_int 12))))
- (set (match_operand:SI 5 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 13) (const_int 16))))
- (set (match_operand:SI 6 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 13) (const_int 20))))
- (set (match_operand:SI 7 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 13) (const_int 24))))
- (set (match_operand:SI 8 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 13) (const_int 28))))
- (set (match_operand:SI 9 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 13) (const_int 32))))
- (set (match_operand:SI 10 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 13) (const_int 36))))
- (set (match_operand:SI 11 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 13) (const_int 40))))
- (set (match_operand:SI 12 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 13) (const_int 44))))])]
- "TARGET_HAS_CDX && XVECLEN (operands[0], 0) == 13"
- "ldwm\\t{%1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12}, (%13)++, ret"
- [(set_attr "type" "ldwm")])
-
-(define_insn "*cdx_ldwm12_inc"
- [(match_parallel 0 "ldwm_operation"
- [(set (match_operand:SI 1 "nios2_hard_register_operand" "")
- (mem:SI (match_operand:SI 13 "register_operand" "r")))
- (set (match_operand:SI 2 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 13) (const_int 4))))
- (set (match_operand:SI 3 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 13) (const_int 8))))
- (set (match_operand:SI 4 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 13) (const_int 12))))
- (set (match_operand:SI 5 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 13) (const_int 16))))
- (set (match_operand:SI 6 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 13) (const_int 20))))
- (set (match_operand:SI 7 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 13) (const_int 24))))
- (set (match_operand:SI 8 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 13) (const_int 28))))
- (set (match_operand:SI 9 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 13) (const_int 32))))
- (set (match_operand:SI 10 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 13) (const_int 36))))
- (set (match_operand:SI 11 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 13) (const_int 40))))
- (set (match_operand:SI 12 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 13) (const_int 44))))])]
- "TARGET_HAS_CDX && XVECLEN (operands[0], 0) == 12"
- "ldwm\\t{%1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12}, (%13)++"
- [(set_attr "type" "ldwm")])
-
-(define_insn "*cdx_ldwm12_dec_wb_ret"
- [(match_parallel 0 "ldwm_operation"
- [(return)
- (set (match_operand:SI 13 "register_operand" "+&r")
- (plus:SI (match_dup 13) (const_int -48)))
- (set (match_operand:SI 1 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 13) (const_int -4))))
- (set (match_operand:SI 2 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 13) (const_int -8))))
- (set (match_operand:SI 3 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 13) (const_int -12))))
- (set (match_operand:SI 4 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 13) (const_int -16))))
- (set (match_operand:SI 5 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 13) (const_int -20))))
- (set (match_operand:SI 6 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 13) (const_int -24))))
- (set (match_operand:SI 7 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 13) (const_int -28))))
- (set (match_operand:SI 8 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 13) (const_int -32))))
- (set (match_operand:SI 9 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 13) (const_int -36))))
- (set (match_operand:SI 10 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 13) (const_int -40))))
- (set (match_operand:SI 11 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 13) (const_int -44))))
- (set (match_operand:SI 12 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 13) (const_int -48))))])]
- "TARGET_HAS_CDX && XVECLEN (operands[0], 0) == 14"
- "ldwm\\t{%1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12}, --(%13), writeback, ret"
- [(set_attr "type" "ldwm")])
-
-(define_insn "*cdx_ldwm12_dec_wb"
- [(match_parallel 0 "ldwm_operation"
- [(set (match_operand:SI 13 "register_operand" "+&r")
- (plus:SI (match_dup 13) (const_int -48)))
- (set (match_operand:SI 1 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 13) (const_int -4))))
- (set (match_operand:SI 2 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 13) (const_int -8))))
- (set (match_operand:SI 3 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 13) (const_int -12))))
- (set (match_operand:SI 4 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 13) (const_int -16))))
- (set (match_operand:SI 5 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 13) (const_int -20))))
- (set (match_operand:SI 6 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 13) (const_int -24))))
- (set (match_operand:SI 7 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 13) (const_int -28))))
- (set (match_operand:SI 8 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 13) (const_int -32))))
- (set (match_operand:SI 9 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 13) (const_int -36))))
- (set (match_operand:SI 10 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 13) (const_int -40))))
- (set (match_operand:SI 11 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 13) (const_int -44))))
- (set (match_operand:SI 12 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 13) (const_int -48))))])]
- "TARGET_HAS_CDX && XVECLEN (operands[0], 0) == 13"
- "ldwm\\t{%1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12}, --(%13), writeback"
- [(set_attr "type" "ldwm")])
-
-(define_insn "*cdx_ldwm12_dec_ret"
- [(match_parallel 0 "ldwm_operation"
- [(return)
- (set (match_operand:SI 1 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_operand:SI 13 "register_operand" "r") (const_int -4))))
- (set (match_operand:SI 2 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 13) (const_int -8))))
- (set (match_operand:SI 3 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 13) (const_int -12))))
- (set (match_operand:SI 4 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 13) (const_int -16))))
- (set (match_operand:SI 5 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 13) (const_int -20))))
- (set (match_operand:SI 6 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 13) (const_int -24))))
- (set (match_operand:SI 7 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 13) (const_int -28))))
- (set (match_operand:SI 8 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 13) (const_int -32))))
- (set (match_operand:SI 9 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 13) (const_int -36))))
- (set (match_operand:SI 10 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 13) (const_int -40))))
- (set (match_operand:SI 11 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 13) (const_int -44))))
- (set (match_operand:SI 12 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 13) (const_int -48))))])]
- "TARGET_HAS_CDX && XVECLEN (operands[0], 0) == 13"
- "ldwm\\t{%1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12}, --(%13), ret"
- [(set_attr "type" "ldwm")])
-
-(define_insn "*cdx_ldwm12_dec"
- [(match_parallel 0 "ldwm_operation"
- [(set (match_operand:SI 1 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_operand:SI 13 "register_operand" "r") (const_int -4))))
- (set (match_operand:SI 2 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 13) (const_int -8))))
- (set (match_operand:SI 3 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 13) (const_int -12))))
- (set (match_operand:SI 4 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 13) (const_int -16))))
- (set (match_operand:SI 5 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 13) (const_int -20))))
- (set (match_operand:SI 6 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 13) (const_int -24))))
- (set (match_operand:SI 7 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 13) (const_int -28))))
- (set (match_operand:SI 8 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 13) (const_int -32))))
- (set (match_operand:SI 9 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 13) (const_int -36))))
- (set (match_operand:SI 10 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 13) (const_int -40))))
- (set (match_operand:SI 11 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 13) (const_int -44))))
- (set (match_operand:SI 12 "nios2_hard_register_operand" "")
- (mem:SI (plus:SI (match_dup 13) (const_int -48))))])]
- "TARGET_HAS_CDX && XVECLEN (operands[0], 0) == 12"
- "ldwm\\t{%1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12}, --(%13)"
- [(set_attr "type" "ldwm")])
-
-(define_insn "*cdx_stwm1_inc_wb"
- [(match_parallel 0 "stwm_operation"
- [(set (match_operand:SI 2 "register_operand" "+&r")
- (plus:SI (match_dup 2) (const_int 4)))
- (set (mem:SI (match_dup 2))
- (match_operand:SI 1 "nios2_hard_register_operand" ""))])]
- "TARGET_HAS_CDX && XVECLEN (operands[0], 0) == 2"
- "stwm\\t{%1}, (%2)++, writeback"
- [(set_attr "type" "stwm")])
-
-(define_insn "*cdx_stwm1_inc"
- [(match_parallel 0 "stwm_operation"
- [(set (mem:SI (match_operand:SI 2 "register_operand" "r"))
- (match_operand:SI 1 "nios2_hard_register_operand" ""))])]
- "TARGET_HAS_CDX && XVECLEN (operands[0], 0) == 1"
- "stwm\\t{%1}, (%2)++"
- [(set_attr "type" "stwm")])
-
-(define_insn "*cdx_stwm1_dec_wb"
- [(match_parallel 0 "stwm_operation"
- [(set (match_operand:SI 2 "register_operand" "+&r")
- (plus:SI (match_dup 2) (const_int -4)))
- (set (mem:SI (plus:SI (match_dup 2) (const_int -4)))
- (match_operand:SI 1 "nios2_hard_register_operand" ""))])]
- "TARGET_HAS_CDX && XVECLEN (operands[0], 0) == 2"
- "stwm\\t{%1}, --(%2), writeback"
- [(set_attr "type" "stwm")])
-
-(define_insn "*cdx_stwm1_dec"
- [(match_parallel 0 "stwm_operation"
- [(set (mem:SI (plus:SI (match_operand:SI 2 "register_operand" "r") (const_int -4)))
- (match_operand:SI 1 "nios2_hard_register_operand" ""))])]
- "TARGET_HAS_CDX && XVECLEN (operands[0], 0) == 1"
- "stwm\\t{%1}, --(%2)"
- [(set_attr "type" "stwm")])
-
-(define_insn "*cdx_stwm2_inc_wb"
- [(match_parallel 0 "stwm_operation"
- [(set (match_operand:SI 3 "register_operand" "+&r")
- (plus:SI (match_dup 3) (const_int 8)))
- (set (mem:SI (match_dup 3))
- (match_operand:SI 1 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 3) (const_int 4)))
- (match_operand:SI 2 "nios2_hard_register_operand" ""))])]
- "TARGET_HAS_CDX && XVECLEN (operands[0], 0) == 3"
- "stwm\\t{%1, %2}, (%3)++, writeback"
- [(set_attr "type" "stwm")])
-
-(define_insn "*cdx_stwm2_inc"
- [(match_parallel 0 "stwm_operation"
- [(set (mem:SI (match_operand:SI 3 "register_operand" "r"))
- (match_operand:SI 1 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 3) (const_int 4)))
- (match_operand:SI 2 "nios2_hard_register_operand" ""))])]
- "TARGET_HAS_CDX && XVECLEN (operands[0], 0) == 2"
- "stwm\\t{%1, %2}, (%3)++"
- [(set_attr "type" "stwm")])
-
-(define_insn "*cdx_stwm2_dec_wb"
- [(match_parallel 0 "stwm_operation"
- [(set (match_operand:SI 3 "register_operand" "+&r")
- (plus:SI (match_dup 3) (const_int -8)))
- (set (mem:SI (plus:SI (match_dup 3) (const_int -4)))
- (match_operand:SI 1 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 3) (const_int -8)))
- (match_operand:SI 2 "nios2_hard_register_operand" ""))])]
- "TARGET_HAS_CDX && XVECLEN (operands[0], 0) == 3"
- "stwm\\t{%1, %2}, --(%3), writeback"
- [(set_attr "type" "stwm")])
-
-(define_insn "*cdx_stwm2_dec"
- [(match_parallel 0 "stwm_operation"
- [(set (mem:SI (plus:SI (match_operand:SI 3 "register_operand" "r") (const_int -4)))
- (match_operand:SI 1 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 3) (const_int -8)))
- (match_operand:SI 2 "nios2_hard_register_operand" ""))])]
- "TARGET_HAS_CDX && XVECLEN (operands[0], 0) == 2"
- "stwm\\t{%1, %2}, --(%3)"
- [(set_attr "type" "stwm")])
-
-(define_insn "*cdx_stwm3_inc_wb"
- [(match_parallel 0 "stwm_operation"
- [(set (match_operand:SI 4 "register_operand" "+&r")
- (plus:SI (match_dup 4) (const_int 12)))
- (set (mem:SI (match_dup 4))
- (match_operand:SI 1 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 4) (const_int 4)))
- (match_operand:SI 2 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 4) (const_int 8)))
- (match_operand:SI 3 "nios2_hard_register_operand" ""))])]
- "TARGET_HAS_CDX && XVECLEN (operands[0], 0) == 4"
- "stwm\\t{%1, %2, %3}, (%4)++, writeback"
- [(set_attr "type" "stwm")])
-
-(define_insn "*cdx_stwm3_inc"
- [(match_parallel 0 "stwm_operation"
- [(set (mem:SI (match_operand:SI 4 "register_operand" "r"))
- (match_operand:SI 1 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 4) (const_int 4)))
- (match_operand:SI 2 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 4) (const_int 8)))
- (match_operand:SI 3 "nios2_hard_register_operand" ""))])]
- "TARGET_HAS_CDX && XVECLEN (operands[0], 0) == 3"
- "stwm\\t{%1, %2, %3}, (%4)++"
- [(set_attr "type" "stwm")])
-
-(define_insn "*cdx_stwm3_dec_wb"
- [(match_parallel 0 "stwm_operation"
- [(set (match_operand:SI 4 "register_operand" "+&r")
- (plus:SI (match_dup 4) (const_int -12)))
- (set (mem:SI (plus:SI (match_dup 4) (const_int -4)))
- (match_operand:SI 1 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 4) (const_int -8)))
- (match_operand:SI 2 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 4) (const_int -12)))
- (match_operand:SI 3 "nios2_hard_register_operand" ""))])]
- "TARGET_HAS_CDX && XVECLEN (operands[0], 0) == 4"
- "stwm\\t{%1, %2, %3}, --(%4), writeback"
- [(set_attr "type" "stwm")])
-
-(define_insn "*cdx_stwm3_dec"
- [(match_parallel 0 "stwm_operation"
- [(set (mem:SI (plus:SI (match_operand:SI 4 "register_operand" "r") (const_int -4)))
- (match_operand:SI 1 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 4) (const_int -8)))
- (match_operand:SI 2 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 4) (const_int -12)))
- (match_operand:SI 3 "nios2_hard_register_operand" ""))])]
- "TARGET_HAS_CDX && XVECLEN (operands[0], 0) == 3"
- "stwm\\t{%1, %2, %3}, --(%4)"
- [(set_attr "type" "stwm")])
-
-(define_insn "*cdx_stwm4_inc_wb"
- [(match_parallel 0 "stwm_operation"
- [(set (match_operand:SI 5 "register_operand" "+&r")
- (plus:SI (match_dup 5) (const_int 16)))
- (set (mem:SI (match_dup 5))
- (match_operand:SI 1 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 5) (const_int 4)))
- (match_operand:SI 2 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 5) (const_int 8)))
- (match_operand:SI 3 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 5) (const_int 12)))
- (match_operand:SI 4 "nios2_hard_register_operand" ""))])]
- "TARGET_HAS_CDX && XVECLEN (operands[0], 0) == 5"
- "stwm\\t{%1, %2, %3, %4}, (%5)++, writeback"
- [(set_attr "type" "stwm")])
-
-(define_insn "*cdx_stwm4_inc"
- [(match_parallel 0 "stwm_operation"
- [(set (mem:SI (match_operand:SI 5 "register_operand" "r"))
- (match_operand:SI 1 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 5) (const_int 4)))
- (match_operand:SI 2 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 5) (const_int 8)))
- (match_operand:SI 3 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 5) (const_int 12)))
- (match_operand:SI 4 "nios2_hard_register_operand" ""))])]
- "TARGET_HAS_CDX && XVECLEN (operands[0], 0) == 4"
- "stwm\\t{%1, %2, %3, %4}, (%5)++"
- [(set_attr "type" "stwm")])
-
-(define_insn "*cdx_stwm4_dec_wb"
- [(match_parallel 0 "stwm_operation"
- [(set (match_operand:SI 5 "register_operand" "+&r")
- (plus:SI (match_dup 5) (const_int -16)))
- (set (mem:SI (plus:SI (match_dup 5) (const_int -4)))
- (match_operand:SI 1 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 5) (const_int -8)))
- (match_operand:SI 2 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 5) (const_int -12)))
- (match_operand:SI 3 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 5) (const_int -16)))
- (match_operand:SI 4 "nios2_hard_register_operand" ""))])]
- "TARGET_HAS_CDX && XVECLEN (operands[0], 0) == 5"
- "stwm\\t{%1, %2, %3, %4}, --(%5), writeback"
- [(set_attr "type" "stwm")])
-
-(define_insn "*cdx_stwm4_dec"
- [(match_parallel 0 "stwm_operation"
- [(set (mem:SI (plus:SI (match_operand:SI 5 "register_operand" "r") (const_int -4)))
- (match_operand:SI 1 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 5) (const_int -8)))
- (match_operand:SI 2 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 5) (const_int -12)))
- (match_operand:SI 3 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 5) (const_int -16)))
- (match_operand:SI 4 "nios2_hard_register_operand" ""))])]
- "TARGET_HAS_CDX && XVECLEN (operands[0], 0) == 4"
- "stwm\\t{%1, %2, %3, %4}, --(%5)"
- [(set_attr "type" "stwm")])
-
-(define_insn "*cdx_stwm5_inc_wb"
- [(match_parallel 0 "stwm_operation"
- [(set (match_operand:SI 6 "register_operand" "+&r")
- (plus:SI (match_dup 6) (const_int 20)))
- (set (mem:SI (match_dup 6))
- (match_operand:SI 1 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 6) (const_int 4)))
- (match_operand:SI 2 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 6) (const_int 8)))
- (match_operand:SI 3 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 6) (const_int 12)))
- (match_operand:SI 4 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 6) (const_int 16)))
- (match_operand:SI 5 "nios2_hard_register_operand" ""))])]
- "TARGET_HAS_CDX && XVECLEN (operands[0], 0) == 6"
- "stwm\\t{%1, %2, %3, %4, %5}, (%6)++, writeback"
- [(set_attr "type" "stwm")])
-
-(define_insn "*cdx_stwm5_inc"
- [(match_parallel 0 "stwm_operation"
- [(set (mem:SI (match_operand:SI 6 "register_operand" "r"))
- (match_operand:SI 1 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 6) (const_int 4)))
- (match_operand:SI 2 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 6) (const_int 8)))
- (match_operand:SI 3 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 6) (const_int 12)))
- (match_operand:SI 4 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 6) (const_int 16)))
- (match_operand:SI 5 "nios2_hard_register_operand" ""))])]
- "TARGET_HAS_CDX && XVECLEN (operands[0], 0) == 5"
- "stwm\\t{%1, %2, %3, %4, %5}, (%6)++"
- [(set_attr "type" "stwm")])
-
-(define_insn "*cdx_stwm5_dec_wb"
- [(match_parallel 0 "stwm_operation"
- [(set (match_operand:SI 6 "register_operand" "+&r")
- (plus:SI (match_dup 6) (const_int -20)))
- (set (mem:SI (plus:SI (match_dup 6) (const_int -4)))
- (match_operand:SI 1 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 6) (const_int -8)))
- (match_operand:SI 2 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 6) (const_int -12)))
- (match_operand:SI 3 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 6) (const_int -16)))
- (match_operand:SI 4 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 6) (const_int -20)))
- (match_operand:SI 5 "nios2_hard_register_operand" ""))])]
- "TARGET_HAS_CDX && XVECLEN (operands[0], 0) == 6"
- "stwm\\t{%1, %2, %3, %4, %5}, --(%6), writeback"
- [(set_attr "type" "stwm")])
-
-(define_insn "*cdx_stwm5_dec"
- [(match_parallel 0 "stwm_operation"
- [(set (mem:SI (plus:SI (match_operand:SI 6 "register_operand" "r") (const_int -4)))
- (match_operand:SI 1 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 6) (const_int -8)))
- (match_operand:SI 2 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 6) (const_int -12)))
- (match_operand:SI 3 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 6) (const_int -16)))
- (match_operand:SI 4 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 6) (const_int -20)))
- (match_operand:SI 5 "nios2_hard_register_operand" ""))])]
- "TARGET_HAS_CDX && XVECLEN (operands[0], 0) == 5"
- "stwm\\t{%1, %2, %3, %4, %5}, --(%6)"
- [(set_attr "type" "stwm")])
-
-(define_insn "*cdx_stwm6_inc_wb"
- [(match_parallel 0 "stwm_operation"
- [(set (match_operand:SI 7 "register_operand" "+&r")
- (plus:SI (match_dup 7) (const_int 24)))
- (set (mem:SI (match_dup 7))
- (match_operand:SI 1 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 7) (const_int 4)))
- (match_operand:SI 2 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 7) (const_int 8)))
- (match_operand:SI 3 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 7) (const_int 12)))
- (match_operand:SI 4 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 7) (const_int 16)))
- (match_operand:SI 5 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 7) (const_int 20)))
- (match_operand:SI 6 "nios2_hard_register_operand" ""))])]
- "TARGET_HAS_CDX && XVECLEN (operands[0], 0) == 7"
- "stwm\\t{%1, %2, %3, %4, %5, %6}, (%7)++, writeback"
- [(set_attr "type" "stwm")])
-
-(define_insn "*cdx_stwm6_inc"
- [(match_parallel 0 "stwm_operation"
- [(set (mem:SI (match_operand:SI 7 "register_operand" "r"))
- (match_operand:SI 1 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 7) (const_int 4)))
- (match_operand:SI 2 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 7) (const_int 8)))
- (match_operand:SI 3 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 7) (const_int 12)))
- (match_operand:SI 4 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 7) (const_int 16)))
- (match_operand:SI 5 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 7) (const_int 20)))
- (match_operand:SI 6 "nios2_hard_register_operand" ""))])]
- "TARGET_HAS_CDX && XVECLEN (operands[0], 0) == 6"
- "stwm\\t{%1, %2, %3, %4, %5, %6}, (%7)++"
- [(set_attr "type" "stwm")])
-
-(define_insn "*cdx_stwm6_dec_wb"
- [(match_parallel 0 "stwm_operation"
- [(set (match_operand:SI 7 "register_operand" "+&r")
- (plus:SI (match_dup 7) (const_int -24)))
- (set (mem:SI (plus:SI (match_dup 7) (const_int -4)))
- (match_operand:SI 1 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 7) (const_int -8)))
- (match_operand:SI 2 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 7) (const_int -12)))
- (match_operand:SI 3 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 7) (const_int -16)))
- (match_operand:SI 4 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 7) (const_int -20)))
- (match_operand:SI 5 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 7) (const_int -24)))
- (match_operand:SI 6 "nios2_hard_register_operand" ""))])]
- "TARGET_HAS_CDX && XVECLEN (operands[0], 0) == 7"
- "stwm\\t{%1, %2, %3, %4, %5, %6}, --(%7), writeback"
- [(set_attr "type" "stwm")])
-
-(define_insn "*cdx_stwm6_dec"
- [(match_parallel 0 "stwm_operation"
- [(set (mem:SI (plus:SI (match_operand:SI 7 "register_operand" "r") (const_int -4)))
- (match_operand:SI 1 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 7) (const_int -8)))
- (match_operand:SI 2 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 7) (const_int -12)))
- (match_operand:SI 3 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 7) (const_int -16)))
- (match_operand:SI 4 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 7) (const_int -20)))
- (match_operand:SI 5 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 7) (const_int -24)))
- (match_operand:SI 6 "nios2_hard_register_operand" ""))])]
- "TARGET_HAS_CDX && XVECLEN (operands[0], 0) == 6"
- "stwm\\t{%1, %2, %3, %4, %5, %6}, --(%7)"
- [(set_attr "type" "stwm")])
-
-(define_insn "*cdx_stwm7_inc_wb"
- [(match_parallel 0 "stwm_operation"
- [(set (match_operand:SI 8 "register_operand" "+&r")
- (plus:SI (match_dup 8) (const_int 28)))
- (set (mem:SI (match_dup 8))
- (match_operand:SI 1 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 8) (const_int 4)))
- (match_operand:SI 2 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 8) (const_int 8)))
- (match_operand:SI 3 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 8) (const_int 12)))
- (match_operand:SI 4 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 8) (const_int 16)))
- (match_operand:SI 5 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 8) (const_int 20)))
- (match_operand:SI 6 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 8) (const_int 24)))
- (match_operand:SI 7 "nios2_hard_register_operand" ""))])]
- "TARGET_HAS_CDX && XVECLEN (operands[0], 0) == 8"
- "stwm\\t{%1, %2, %3, %4, %5, %6, %7}, (%8)++, writeback"
- [(set_attr "type" "stwm")])
-
-(define_insn "*cdx_stwm7_inc"
- [(match_parallel 0 "stwm_operation"
- [(set (mem:SI (match_operand:SI 8 "register_operand" "r"))
- (match_operand:SI 1 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 8) (const_int 4)))
- (match_operand:SI 2 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 8) (const_int 8)))
- (match_operand:SI 3 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 8) (const_int 12)))
- (match_operand:SI 4 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 8) (const_int 16)))
- (match_operand:SI 5 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 8) (const_int 20)))
- (match_operand:SI 6 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 8) (const_int 24)))
- (match_operand:SI 7 "nios2_hard_register_operand" ""))])]
- "TARGET_HAS_CDX && XVECLEN (operands[0], 0) == 7"
- "stwm\\t{%1, %2, %3, %4, %5, %6, %7}, (%8)++"
- [(set_attr "type" "stwm")])
-
-(define_insn "*cdx_stwm7_dec_wb"
- [(match_parallel 0 "stwm_operation"
- [(set (match_operand:SI 8 "register_operand" "+&r")
- (plus:SI (match_dup 8) (const_int -28)))
- (set (mem:SI (plus:SI (match_dup 8) (const_int -4)))
- (match_operand:SI 1 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 8) (const_int -8)))
- (match_operand:SI 2 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 8) (const_int -12)))
- (match_operand:SI 3 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 8) (const_int -16)))
- (match_operand:SI 4 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 8) (const_int -20)))
- (match_operand:SI 5 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 8) (const_int -24)))
- (match_operand:SI 6 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 8) (const_int -28)))
- (match_operand:SI 7 "nios2_hard_register_operand" ""))])]
- "TARGET_HAS_CDX && XVECLEN (operands[0], 0) == 8"
- "stwm\\t{%1, %2, %3, %4, %5, %6, %7}, --(%8), writeback"
- [(set_attr "type" "stwm")])
-
-(define_insn "*cdx_stwm7_dec"
- [(match_parallel 0 "stwm_operation"
- [(set (mem:SI (plus:SI (match_operand:SI 8 "register_operand" "r") (const_int -4)))
- (match_operand:SI 1 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 8) (const_int -8)))
- (match_operand:SI 2 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 8) (const_int -12)))
- (match_operand:SI 3 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 8) (const_int -16)))
- (match_operand:SI 4 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 8) (const_int -20)))
- (match_operand:SI 5 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 8) (const_int -24)))
- (match_operand:SI 6 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 8) (const_int -28)))
- (match_operand:SI 7 "nios2_hard_register_operand" ""))])]
- "TARGET_HAS_CDX && XVECLEN (operands[0], 0) == 7"
- "stwm\\t{%1, %2, %3, %4, %5, %6, %7}, --(%8)"
- [(set_attr "type" "stwm")])
-
-(define_insn "*cdx_stwm8_inc_wb"
- [(match_parallel 0 "stwm_operation"
- [(set (match_operand:SI 9 "register_operand" "+&r")
- (plus:SI (match_dup 9) (const_int 32)))
- (set (mem:SI (match_dup 9))
- (match_operand:SI 1 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 9) (const_int 4)))
- (match_operand:SI 2 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 9) (const_int 8)))
- (match_operand:SI 3 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 9) (const_int 12)))
- (match_operand:SI 4 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 9) (const_int 16)))
- (match_operand:SI 5 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 9) (const_int 20)))
- (match_operand:SI 6 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 9) (const_int 24)))
- (match_operand:SI 7 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 9) (const_int 28)))
- (match_operand:SI 8 "nios2_hard_register_operand" ""))])]
- "TARGET_HAS_CDX && XVECLEN (operands[0], 0) == 9"
- "stwm\\t{%1, %2, %3, %4, %5, %6, %7, %8}, (%9)++, writeback"
- [(set_attr "type" "stwm")])
-
-(define_insn "*cdx_stwm8_inc"
- [(match_parallel 0 "stwm_operation"
- [(set (mem:SI (match_operand:SI 9 "register_operand" "r"))
- (match_operand:SI 1 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 9) (const_int 4)))
- (match_operand:SI 2 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 9) (const_int 8)))
- (match_operand:SI 3 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 9) (const_int 12)))
- (match_operand:SI 4 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 9) (const_int 16)))
- (match_operand:SI 5 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 9) (const_int 20)))
- (match_operand:SI 6 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 9) (const_int 24)))
- (match_operand:SI 7 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 9) (const_int 28)))
- (match_operand:SI 8 "nios2_hard_register_operand" ""))])]
- "TARGET_HAS_CDX && XVECLEN (operands[0], 0) == 8"
- "stwm\\t{%1, %2, %3, %4, %5, %6, %7, %8}, (%9)++"
- [(set_attr "type" "stwm")])
-
-(define_insn "*cdx_stwm8_dec_wb"
- [(match_parallel 0 "stwm_operation"
- [(set (match_operand:SI 9 "register_operand" "+&r")
- (plus:SI (match_dup 9) (const_int -32)))
- (set (mem:SI (plus:SI (match_dup 9) (const_int -4)))
- (match_operand:SI 1 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 9) (const_int -8)))
- (match_operand:SI 2 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 9) (const_int -12)))
- (match_operand:SI 3 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 9) (const_int -16)))
- (match_operand:SI 4 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 9) (const_int -20)))
- (match_operand:SI 5 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 9) (const_int -24)))
- (match_operand:SI 6 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 9) (const_int -28)))
- (match_operand:SI 7 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 9) (const_int -32)))
- (match_operand:SI 8 "nios2_hard_register_operand" ""))])]
- "TARGET_HAS_CDX && XVECLEN (operands[0], 0) == 9"
- "stwm\\t{%1, %2, %3, %4, %5, %6, %7, %8}, --(%9), writeback"
- [(set_attr "type" "stwm")])
-
-(define_insn "*cdx_stwm8_dec"
- [(match_parallel 0 "stwm_operation"
- [(set (mem:SI (plus:SI (match_operand:SI 9 "register_operand" "r") (const_int -4)))
- (match_operand:SI 1 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 9) (const_int -8)))
- (match_operand:SI 2 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 9) (const_int -12)))
- (match_operand:SI 3 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 9) (const_int -16)))
- (match_operand:SI 4 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 9) (const_int -20)))
- (match_operand:SI 5 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 9) (const_int -24)))
- (match_operand:SI 6 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 9) (const_int -28)))
- (match_operand:SI 7 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 9) (const_int -32)))
- (match_operand:SI 8 "nios2_hard_register_operand" ""))])]
- "TARGET_HAS_CDX && XVECLEN (operands[0], 0) == 8"
- "stwm\\t{%1, %2, %3, %4, %5, %6, %7, %8}, --(%9)"
- [(set_attr "type" "stwm")])
-
-(define_insn "*cdx_stwm9_inc_wb"
- [(match_parallel 0 "stwm_operation"
- [(set (match_operand:SI 10 "register_operand" "+&r")
- (plus:SI (match_dup 10) (const_int 36)))
- (set (mem:SI (match_dup 10))
- (match_operand:SI 1 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 10) (const_int 4)))
- (match_operand:SI 2 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 10) (const_int 8)))
- (match_operand:SI 3 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 10) (const_int 12)))
- (match_operand:SI 4 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 10) (const_int 16)))
- (match_operand:SI 5 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 10) (const_int 20)))
- (match_operand:SI 6 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 10) (const_int 24)))
- (match_operand:SI 7 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 10) (const_int 28)))
- (match_operand:SI 8 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 10) (const_int 32)))
- (match_operand:SI 9 "nios2_hard_register_operand" ""))])]
- "TARGET_HAS_CDX && XVECLEN (operands[0], 0) == 10"
- "stwm\\t{%1, %2, %3, %4, %5, %6, %7, %8, %9}, (%10)++, writeback"
- [(set_attr "type" "stwm")])
-
-(define_insn "*cdx_stwm9_inc"
- [(match_parallel 0 "stwm_operation"
- [(set (mem:SI (match_operand:SI 10 "register_operand" "r"))
- (match_operand:SI 1 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 10) (const_int 4)))
- (match_operand:SI 2 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 10) (const_int 8)))
- (match_operand:SI 3 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 10) (const_int 12)))
- (match_operand:SI 4 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 10) (const_int 16)))
- (match_operand:SI 5 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 10) (const_int 20)))
- (match_operand:SI 6 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 10) (const_int 24)))
- (match_operand:SI 7 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 10) (const_int 28)))
- (match_operand:SI 8 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 10) (const_int 32)))
- (match_operand:SI 9 "nios2_hard_register_operand" ""))])]
- "TARGET_HAS_CDX && XVECLEN (operands[0], 0) == 9"
- "stwm\\t{%1, %2, %3, %4, %5, %6, %7, %8, %9}, (%10)++"
- [(set_attr "type" "stwm")])
-
-(define_insn "*cdx_stwm9_dec_wb"
- [(match_parallel 0 "stwm_operation"
- [(set (match_operand:SI 10 "register_operand" "+&r")
- (plus:SI (match_dup 10) (const_int -36)))
- (set (mem:SI (plus:SI (match_dup 10) (const_int -4)))
- (match_operand:SI 1 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 10) (const_int -8)))
- (match_operand:SI 2 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 10) (const_int -12)))
- (match_operand:SI 3 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 10) (const_int -16)))
- (match_operand:SI 4 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 10) (const_int -20)))
- (match_operand:SI 5 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 10) (const_int -24)))
- (match_operand:SI 6 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 10) (const_int -28)))
- (match_operand:SI 7 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 10) (const_int -32)))
- (match_operand:SI 8 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 10) (const_int -36)))
- (match_operand:SI 9 "nios2_hard_register_operand" ""))])]
- "TARGET_HAS_CDX && XVECLEN (operands[0], 0) == 10"
- "stwm\\t{%1, %2, %3, %4, %5, %6, %7, %8, %9}, --(%10), writeback"
- [(set_attr "type" "stwm")])
-
-(define_insn "*cdx_stwm9_dec"
- [(match_parallel 0 "stwm_operation"
- [(set (mem:SI (plus:SI (match_operand:SI 10 "register_operand" "r") (const_int -4)))
- (match_operand:SI 1 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 10) (const_int -8)))
- (match_operand:SI 2 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 10) (const_int -12)))
- (match_operand:SI 3 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 10) (const_int -16)))
- (match_operand:SI 4 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 10) (const_int -20)))
- (match_operand:SI 5 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 10) (const_int -24)))
- (match_operand:SI 6 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 10) (const_int -28)))
- (match_operand:SI 7 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 10) (const_int -32)))
- (match_operand:SI 8 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 10) (const_int -36)))
- (match_operand:SI 9 "nios2_hard_register_operand" ""))])]
- "TARGET_HAS_CDX && XVECLEN (operands[0], 0) == 9"
- "stwm\\t{%1, %2, %3, %4, %5, %6, %7, %8, %9}, --(%10)"
- [(set_attr "type" "stwm")])
-
-(define_insn "*cdx_stwm10_inc_wb"
- [(match_parallel 0 "stwm_operation"
- [(set (match_operand:SI 11 "register_operand" "+&r")
- (plus:SI (match_dup 11) (const_int 40)))
- (set (mem:SI (match_dup 11))
- (match_operand:SI 1 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 11) (const_int 4)))
- (match_operand:SI 2 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 11) (const_int 8)))
- (match_operand:SI 3 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 11) (const_int 12)))
- (match_operand:SI 4 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 11) (const_int 16)))
- (match_operand:SI 5 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 11) (const_int 20)))
- (match_operand:SI 6 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 11) (const_int 24)))
- (match_operand:SI 7 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 11) (const_int 28)))
- (match_operand:SI 8 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 11) (const_int 32)))
- (match_operand:SI 9 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 11) (const_int 36)))
- (match_operand:SI 10 "nios2_hard_register_operand" ""))])]
- "TARGET_HAS_CDX && XVECLEN (operands[0], 0) == 11"
- "stwm\\t{%1, %2, %3, %4, %5, %6, %7, %8, %9, %10}, (%11)++, writeback"
- [(set_attr "type" "stwm")])
-
-(define_insn "*cdx_stwm10_inc"
- [(match_parallel 0 "stwm_operation"
- [(set (mem:SI (match_operand:SI 11 "register_operand" "r"))
- (match_operand:SI 1 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 11) (const_int 4)))
- (match_operand:SI 2 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 11) (const_int 8)))
- (match_operand:SI 3 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 11) (const_int 12)))
- (match_operand:SI 4 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 11) (const_int 16)))
- (match_operand:SI 5 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 11) (const_int 20)))
- (match_operand:SI 6 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 11) (const_int 24)))
- (match_operand:SI 7 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 11) (const_int 28)))
- (match_operand:SI 8 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 11) (const_int 32)))
- (match_operand:SI 9 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 11) (const_int 36)))
- (match_operand:SI 10 "nios2_hard_register_operand" ""))])]
- "TARGET_HAS_CDX && XVECLEN (operands[0], 0) == 10"
- "stwm\\t{%1, %2, %3, %4, %5, %6, %7, %8, %9, %10}, (%11)++"
- [(set_attr "type" "stwm")])
-
-(define_insn "*cdx_stwm10_dec_wb"
- [(match_parallel 0 "stwm_operation"
- [(set (match_operand:SI 11 "register_operand" "+&r")
- (plus:SI (match_dup 11) (const_int -40)))
- (set (mem:SI (plus:SI (match_dup 11) (const_int -4)))
- (match_operand:SI 1 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 11) (const_int -8)))
- (match_operand:SI 2 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 11) (const_int -12)))
- (match_operand:SI 3 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 11) (const_int -16)))
- (match_operand:SI 4 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 11) (const_int -20)))
- (match_operand:SI 5 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 11) (const_int -24)))
- (match_operand:SI 6 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 11) (const_int -28)))
- (match_operand:SI 7 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 11) (const_int -32)))
- (match_operand:SI 8 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 11) (const_int -36)))
- (match_operand:SI 9 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 11) (const_int -40)))
- (match_operand:SI 10 "nios2_hard_register_operand" ""))])]
- "TARGET_HAS_CDX && XVECLEN (operands[0], 0) == 11"
- "stwm\\t{%1, %2, %3, %4, %5, %6, %7, %8, %9, %10}, --(%11), writeback"
- [(set_attr "type" "stwm")])
-
-(define_insn "*cdx_stwm10_dec"
- [(match_parallel 0 "stwm_operation"
- [(set (mem:SI (plus:SI (match_operand:SI 11 "register_operand" "r") (const_int -4)))
- (match_operand:SI 1 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 11) (const_int -8)))
- (match_operand:SI 2 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 11) (const_int -12)))
- (match_operand:SI 3 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 11) (const_int -16)))
- (match_operand:SI 4 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 11) (const_int -20)))
- (match_operand:SI 5 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 11) (const_int -24)))
- (match_operand:SI 6 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 11) (const_int -28)))
- (match_operand:SI 7 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 11) (const_int -32)))
- (match_operand:SI 8 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 11) (const_int -36)))
- (match_operand:SI 9 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 11) (const_int -40)))
- (match_operand:SI 10 "nios2_hard_register_operand" ""))])]
- "TARGET_HAS_CDX && XVECLEN (operands[0], 0) == 10"
- "stwm\\t{%1, %2, %3, %4, %5, %6, %7, %8, %9, %10}, --(%11)"
- [(set_attr "type" "stwm")])
-
-(define_insn "*cdx_stwm11_inc_wb"
- [(match_parallel 0 "stwm_operation"
- [(set (match_operand:SI 12 "register_operand" "+&r")
- (plus:SI (match_dup 12) (const_int 44)))
- (set (mem:SI (match_dup 12))
- (match_operand:SI 1 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 12) (const_int 4)))
- (match_operand:SI 2 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 12) (const_int 8)))
- (match_operand:SI 3 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 12) (const_int 12)))
- (match_operand:SI 4 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 12) (const_int 16)))
- (match_operand:SI 5 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 12) (const_int 20)))
- (match_operand:SI 6 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 12) (const_int 24)))
- (match_operand:SI 7 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 12) (const_int 28)))
- (match_operand:SI 8 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 12) (const_int 32)))
- (match_operand:SI 9 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 12) (const_int 36)))
- (match_operand:SI 10 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 12) (const_int 40)))
- (match_operand:SI 11 "nios2_hard_register_operand" ""))])]
- "TARGET_HAS_CDX && XVECLEN (operands[0], 0) == 12"
- "stwm\\t{%1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11}, (%12)++, writeback"
- [(set_attr "type" "stwm")])
-
-(define_insn "*cdx_stwm11_inc"
- [(match_parallel 0 "stwm_operation"
- [(set (mem:SI (match_operand:SI 12 "register_operand" "r"))
- (match_operand:SI 1 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 12) (const_int 4)))
- (match_operand:SI 2 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 12) (const_int 8)))
- (match_operand:SI 3 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 12) (const_int 12)))
- (match_operand:SI 4 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 12) (const_int 16)))
- (match_operand:SI 5 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 12) (const_int 20)))
- (match_operand:SI 6 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 12) (const_int 24)))
- (match_operand:SI 7 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 12) (const_int 28)))
- (match_operand:SI 8 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 12) (const_int 32)))
- (match_operand:SI 9 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 12) (const_int 36)))
- (match_operand:SI 10 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 12) (const_int 40)))
- (match_operand:SI 11 "nios2_hard_register_operand" ""))])]
- "TARGET_HAS_CDX && XVECLEN (operands[0], 0) == 11"
- "stwm\\t{%1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11}, (%12)++"
- [(set_attr "type" "stwm")])
-
-(define_insn "*cdx_stwm11_dec_wb"
- [(match_parallel 0 "stwm_operation"
- [(set (match_operand:SI 12 "register_operand" "+&r")
- (plus:SI (match_dup 12) (const_int -44)))
- (set (mem:SI (plus:SI (match_dup 12) (const_int -4)))
- (match_operand:SI 1 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 12) (const_int -8)))
- (match_operand:SI 2 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 12) (const_int -12)))
- (match_operand:SI 3 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 12) (const_int -16)))
- (match_operand:SI 4 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 12) (const_int -20)))
- (match_operand:SI 5 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 12) (const_int -24)))
- (match_operand:SI 6 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 12) (const_int -28)))
- (match_operand:SI 7 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 12) (const_int -32)))
- (match_operand:SI 8 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 12) (const_int -36)))
- (match_operand:SI 9 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 12) (const_int -40)))
- (match_operand:SI 10 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 12) (const_int -44)))
- (match_operand:SI 11 "nios2_hard_register_operand" ""))])]
- "TARGET_HAS_CDX && XVECLEN (operands[0], 0) == 12"
- "stwm\\t{%1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11}, --(%12), writeback"
- [(set_attr "type" "stwm")])
-
-(define_insn "*cdx_stwm11_dec"
- [(match_parallel 0 "stwm_operation"
- [(set (mem:SI (plus:SI (match_operand:SI 12 "register_operand" "r") (const_int -4)))
- (match_operand:SI 1 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 12) (const_int -8)))
- (match_operand:SI 2 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 12) (const_int -12)))
- (match_operand:SI 3 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 12) (const_int -16)))
- (match_operand:SI 4 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 12) (const_int -20)))
- (match_operand:SI 5 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 12) (const_int -24)))
- (match_operand:SI 6 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 12) (const_int -28)))
- (match_operand:SI 7 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 12) (const_int -32)))
- (match_operand:SI 8 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 12) (const_int -36)))
- (match_operand:SI 9 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 12) (const_int -40)))
- (match_operand:SI 10 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 12) (const_int -44)))
- (match_operand:SI 11 "nios2_hard_register_operand" ""))])]
- "TARGET_HAS_CDX && XVECLEN (operands[0], 0) == 11"
- "stwm\\t{%1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11}, --(%12)"
- [(set_attr "type" "stwm")])
-
-(define_insn "*cdx_stwm12_inc_wb"
- [(match_parallel 0 "stwm_operation"
- [(set (match_operand:SI 13 "register_operand" "+&r")
- (plus:SI (match_dup 13) (const_int 48)))
- (set (mem:SI (match_dup 13))
- (match_operand:SI 1 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 13) (const_int 4)))
- (match_operand:SI 2 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 13) (const_int 8)))
- (match_operand:SI 3 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 13) (const_int 12)))
- (match_operand:SI 4 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 13) (const_int 16)))
- (match_operand:SI 5 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 13) (const_int 20)))
- (match_operand:SI 6 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 13) (const_int 24)))
- (match_operand:SI 7 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 13) (const_int 28)))
- (match_operand:SI 8 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 13) (const_int 32)))
- (match_operand:SI 9 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 13) (const_int 36)))
- (match_operand:SI 10 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 13) (const_int 40)))
- (match_operand:SI 11 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 13) (const_int 44)))
- (match_operand:SI 12 "nios2_hard_register_operand" ""))])]
- "TARGET_HAS_CDX && XVECLEN (operands[0], 0) == 13"
- "stwm\\t{%1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12}, (%13)++, writeback"
- [(set_attr "type" "stwm")])
-
-(define_insn "*cdx_stwm12_inc"
- [(match_parallel 0 "stwm_operation"
- [(set (mem:SI (match_operand:SI 13 "register_operand" "r"))
- (match_operand:SI 1 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 13) (const_int 4)))
- (match_operand:SI 2 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 13) (const_int 8)))
- (match_operand:SI 3 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 13) (const_int 12)))
- (match_operand:SI 4 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 13) (const_int 16)))
- (match_operand:SI 5 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 13) (const_int 20)))
- (match_operand:SI 6 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 13) (const_int 24)))
- (match_operand:SI 7 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 13) (const_int 28)))
- (match_operand:SI 8 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 13) (const_int 32)))
- (match_operand:SI 9 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 13) (const_int 36)))
- (match_operand:SI 10 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 13) (const_int 40)))
- (match_operand:SI 11 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 13) (const_int 44)))
- (match_operand:SI 12 "nios2_hard_register_operand" ""))])]
- "TARGET_HAS_CDX && XVECLEN (operands[0], 0) == 12"
- "stwm\\t{%1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12}, (%13)++"
- [(set_attr "type" "stwm")])
-
-(define_insn "*cdx_stwm12_dec_wb"
- [(match_parallel 0 "stwm_operation"
- [(set (match_operand:SI 13 "register_operand" "+&r")
- (plus:SI (match_dup 13) (const_int -48)))
- (set (mem:SI (plus:SI (match_dup 13) (const_int -4)))
- (match_operand:SI 1 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 13) (const_int -8)))
- (match_operand:SI 2 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 13) (const_int -12)))
- (match_operand:SI 3 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 13) (const_int -16)))
- (match_operand:SI 4 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 13) (const_int -20)))
- (match_operand:SI 5 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 13) (const_int -24)))
- (match_operand:SI 6 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 13) (const_int -28)))
- (match_operand:SI 7 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 13) (const_int -32)))
- (match_operand:SI 8 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 13) (const_int -36)))
- (match_operand:SI 9 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 13) (const_int -40)))
- (match_operand:SI 10 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 13) (const_int -44)))
- (match_operand:SI 11 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 13) (const_int -48)))
- (match_operand:SI 12 "nios2_hard_register_operand" ""))])]
- "TARGET_HAS_CDX && XVECLEN (operands[0], 0) == 13"
- "stwm\\t{%1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12}, --(%13), writeback"
- [(set_attr "type" "stwm")])
-
-(define_insn "*cdx_stwm12_dec"
- [(match_parallel 0 "stwm_operation"
- [(set (mem:SI (plus:SI (match_operand:SI 13 "register_operand" "r") (const_int -4)))
- (match_operand:SI 1 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 13) (const_int -8)))
- (match_operand:SI 2 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 13) (const_int -12)))
- (match_operand:SI 3 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 13) (const_int -16)))
- (match_operand:SI 4 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 13) (const_int -20)))
- (match_operand:SI 5 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 13) (const_int -24)))
- (match_operand:SI 6 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 13) (const_int -28)))
- (match_operand:SI 7 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 13) (const_int -32)))
- (match_operand:SI 8 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 13) (const_int -36)))
- (match_operand:SI 9 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 13) (const_int -40)))
- (match_operand:SI 10 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 13) (const_int -44)))
- (match_operand:SI 11 "nios2_hard_register_operand" ""))
- (set (mem:SI (plus:SI (match_dup 13) (const_int -48)))
- (match_operand:SI 12 "nios2_hard_register_operand" ""))])]
- "TARGET_HAS_CDX && XVECLEN (operands[0], 0) == 12"
- "stwm\\t{%1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12}, --(%13)"
- [(set_attr "type" "stwm")])
-
-(define_peephole2
- [(match_scratch:SI 24 "r")
- (set (match_operand:SI 0 "register_operand" "")
- (match_operand:SI 12 "memory_operand" ""))
- (set (match_operand:SI 1 "register_operand" "")
- (match_operand:SI 13 "memory_operand" ""))
- (set (match_operand:SI 2 "register_operand" "")
- (match_operand:SI 14 "memory_operand" ""))
- (set (match_operand:SI 3 "register_operand" "")
- (match_operand:SI 15 "memory_operand" ""))
- (set (match_operand:SI 4 "register_operand" "")
- (match_operand:SI 16 "memory_operand" ""))
- (set (match_operand:SI 5 "register_operand" "")
- (match_operand:SI 17 "memory_operand" ""))
- (set (match_operand:SI 6 "register_operand" "")
- (match_operand:SI 18 "memory_operand" ""))
- (set (match_operand:SI 7 "register_operand" "")
- (match_operand:SI 19 "memory_operand" ""))
- (set (match_operand:SI 8 "register_operand" "")
- (match_operand:SI 20 "memory_operand" ""))
- (set (match_operand:SI 9 "register_operand" "")
- (match_operand:SI 21 "memory_operand" ""))
- (set (match_operand:SI 10 "register_operand" "")
- (match_operand:SI 22 "memory_operand" ""))
- (set (match_operand:SI 11 "register_operand" "")
- (match_operand:SI 23 "memory_operand" ""))
- (match_dup 24)]
- "TARGET_HAS_CDX"
- [(const_int 0)]
-{
- if (gen_ldstwm_peep (true, 12, operands[24], operands))
- DONE;
- else
- FAIL;
-})
-
-(define_peephole2
- [(match_scratch:SI 22 "r")
- (set (match_operand:SI 0 "register_operand" "")
- (match_operand:SI 11 "memory_operand" ""))
- (set (match_operand:SI 1 "register_operand" "")
- (match_operand:SI 12 "memory_operand" ""))
- (set (match_operand:SI 2 "register_operand" "")
- (match_operand:SI 13 "memory_operand" ""))
- (set (match_operand:SI 3 "register_operand" "")
- (match_operand:SI 14 "memory_operand" ""))
- (set (match_operand:SI 4 "register_operand" "")
- (match_operand:SI 15 "memory_operand" ""))
- (set (match_operand:SI 5 "register_operand" "")
- (match_operand:SI 16 "memory_operand" ""))
- (set (match_operand:SI 6 "register_operand" "")
- (match_operand:SI 17 "memory_operand" ""))
- (set (match_operand:SI 7 "register_operand" "")
- (match_operand:SI 18 "memory_operand" ""))
- (set (match_operand:SI 8 "register_operand" "")
- (match_operand:SI 19 "memory_operand" ""))
- (set (match_operand:SI 9 "register_operand" "")
- (match_operand:SI 20 "memory_operand" ""))
- (set (match_operand:SI 10 "register_operand" "")
- (match_operand:SI 21 "memory_operand" ""))
- (match_dup 22)]
- "TARGET_HAS_CDX"
- [(const_int 0)]
-{
- if (gen_ldstwm_peep (true, 11, operands[22], operands))
- DONE;
- else
- FAIL;
-})
-
-(define_peephole2
- [(match_scratch:SI 20 "r")
- (set (match_operand:SI 0 "register_operand" "")
- (match_operand:SI 10 "memory_operand" ""))
- (set (match_operand:SI 1 "register_operand" "")
- (match_operand:SI 11 "memory_operand" ""))
- (set (match_operand:SI 2 "register_operand" "")
- (match_operand:SI 12 "memory_operand" ""))
- (set (match_operand:SI 3 "register_operand" "")
- (match_operand:SI 13 "memory_operand" ""))
- (set (match_operand:SI 4 "register_operand" "")
- (match_operand:SI 14 "memory_operand" ""))
- (set (match_operand:SI 5 "register_operand" "")
- (match_operand:SI 15 "memory_operand" ""))
- (set (match_operand:SI 6 "register_operand" "")
- (match_operand:SI 16 "memory_operand" ""))
- (set (match_operand:SI 7 "register_operand" "")
- (match_operand:SI 17 "memory_operand" ""))
- (set (match_operand:SI 8 "register_operand" "")
- (match_operand:SI 18 "memory_operand" ""))
- (set (match_operand:SI 9 "register_operand" "")
- (match_operand:SI 19 "memory_operand" ""))
- (match_dup 20)]
- "TARGET_HAS_CDX"
- [(const_int 0)]
-{
- if (gen_ldstwm_peep (true, 10, operands[20], operands))
- DONE;
- else
- FAIL;
-})
-
-(define_peephole2
- [(match_scratch:SI 18 "r")
- (set (match_operand:SI 0 "register_operand" "")
- (match_operand:SI 9 "memory_operand" ""))
- (set (match_operand:SI 1 "register_operand" "")
- (match_operand:SI 10 "memory_operand" ""))
- (set (match_operand:SI 2 "register_operand" "")
- (match_operand:SI 11 "memory_operand" ""))
- (set (match_operand:SI 3 "register_operand" "")
- (match_operand:SI 12 "memory_operand" ""))
- (set (match_operand:SI 4 "register_operand" "")
- (match_operand:SI 13 "memory_operand" ""))
- (set (match_operand:SI 5 "register_operand" "")
- (match_operand:SI 14 "memory_operand" ""))
- (set (match_operand:SI 6 "register_operand" "")
- (match_operand:SI 15 "memory_operand" ""))
- (set (match_operand:SI 7 "register_operand" "")
- (match_operand:SI 16 "memory_operand" ""))
- (set (match_operand:SI 8 "register_operand" "")
- (match_operand:SI 17 "memory_operand" ""))
- (match_dup 18)]
- "TARGET_HAS_CDX"
- [(const_int 0)]
-{
- if (gen_ldstwm_peep (true, 9, operands[18], operands))
- DONE;
- else
- FAIL;
-})
-
-(define_peephole2
- [(match_scratch:SI 16 "r")
- (set (match_operand:SI 0 "register_operand" "")
- (match_operand:SI 8 "memory_operand" ""))
- (set (match_operand:SI 1 "register_operand" "")
- (match_operand:SI 9 "memory_operand" ""))
- (set (match_operand:SI 2 "register_operand" "")
- (match_operand:SI 10 "memory_operand" ""))
- (set (match_operand:SI 3 "register_operand" "")
- (match_operand:SI 11 "memory_operand" ""))
- (set (match_operand:SI 4 "register_operand" "")
- (match_operand:SI 12 "memory_operand" ""))
- (set (match_operand:SI 5 "register_operand" "")
- (match_operand:SI 13 "memory_operand" ""))
- (set (match_operand:SI 6 "register_operand" "")
- (match_operand:SI 14 "memory_operand" ""))
- (set (match_operand:SI 7 "register_operand" "")
- (match_operand:SI 15 "memory_operand" ""))
- (match_dup 16)]
- "TARGET_HAS_CDX"
- [(const_int 0)]
-{
- if (gen_ldstwm_peep (true, 8, operands[16], operands))
- DONE;
- else
- FAIL;
-})
-
-(define_peephole2
- [(match_scratch:SI 14 "r")
- (set (match_operand:SI 0 "register_operand" "")
- (match_operand:SI 7 "memory_operand" ""))
- (set (match_operand:SI 1 "register_operand" "")
- (match_operand:SI 8 "memory_operand" ""))
- (set (match_operand:SI 2 "register_operand" "")
- (match_operand:SI 9 "memory_operand" ""))
- (set (match_operand:SI 3 "register_operand" "")
- (match_operand:SI 10 "memory_operand" ""))
- (set (match_operand:SI 4 "register_operand" "")
- (match_operand:SI 11 "memory_operand" ""))
- (set (match_operand:SI 5 "register_operand" "")
- (match_operand:SI 12 "memory_operand" ""))
- (set (match_operand:SI 6 "register_operand" "")
- (match_operand:SI 13 "memory_operand" ""))
- (match_dup 14)]
- "TARGET_HAS_CDX"
- [(const_int 0)]
-{
- if (gen_ldstwm_peep (true, 7, operands[14], operands))
- DONE;
- else
- FAIL;
-})
-
-(define_peephole2
- [(match_scratch:SI 12 "r")
- (set (match_operand:SI 0 "register_operand" "")
- (match_operand:SI 6 "memory_operand" ""))
- (set (match_operand:SI 1 "register_operand" "")
- (match_operand:SI 7 "memory_operand" ""))
- (set (match_operand:SI 2 "register_operand" "")
- (match_operand:SI 8 "memory_operand" ""))
- (set (match_operand:SI 3 "register_operand" "")
- (match_operand:SI 9 "memory_operand" ""))
- (set (match_operand:SI 4 "register_operand" "")
- (match_operand:SI 10 "memory_operand" ""))
- (set (match_operand:SI 5 "register_operand" "")
- (match_operand:SI 11 "memory_operand" ""))
- (match_dup 12)]
- "TARGET_HAS_CDX"
- [(const_int 0)]
-{
- if (gen_ldstwm_peep (true, 6, operands[12], operands))
- DONE;
- else
- FAIL;
-})
-
-(define_peephole2
- [(match_scratch:SI 10 "r")
- (set (match_operand:SI 0 "register_operand" "")
- (match_operand:SI 5 "memory_operand" ""))
- (set (match_operand:SI 1 "register_operand" "")
- (match_operand:SI 6 "memory_operand" ""))
- (set (match_operand:SI 2 "register_operand" "")
- (match_operand:SI 7 "memory_operand" ""))
- (set (match_operand:SI 3 "register_operand" "")
- (match_operand:SI 8 "memory_operand" ""))
- (set (match_operand:SI 4 "register_operand" "")
- (match_operand:SI 9 "memory_operand" ""))
- (match_dup 10)]
- "TARGET_HAS_CDX"
- [(const_int 0)]
-{
- if (gen_ldstwm_peep (true, 5, operands[10], operands))
- DONE;
- else
- FAIL;
-})
-
-(define_peephole2
- [(match_scratch:SI 8 "r")
- (set (match_operand:SI 0 "register_operand" "")
- (match_operand:SI 4 "memory_operand" ""))
- (set (match_operand:SI 1 "register_operand" "")
- (match_operand:SI 5 "memory_operand" ""))
- (set (match_operand:SI 2 "register_operand" "")
- (match_operand:SI 6 "memory_operand" ""))
- (set (match_operand:SI 3 "register_operand" "")
- (match_operand:SI 7 "memory_operand" ""))
- (match_dup 8)]
- "TARGET_HAS_CDX"
- [(const_int 0)]
-{
- if (gen_ldstwm_peep (true, 4, operands[8], operands))
- DONE;
- else
- FAIL;
-})
-
-(define_peephole2
- [(match_scratch:SI 6 "r")
- (set (match_operand:SI 0 "register_operand" "")
- (match_operand:SI 3 "memory_operand" ""))
- (set (match_operand:SI 1 "register_operand" "")
- (match_operand:SI 4 "memory_operand" ""))
- (set (match_operand:SI 2 "register_operand" "")
- (match_operand:SI 5 "memory_operand" ""))
- (match_dup 6)]
- "TARGET_HAS_CDX"
- [(const_int 0)]
-{
- if (gen_ldstwm_peep (true, 3, operands[6], operands))
- DONE;
- else
- FAIL;
-})
-
-(define_peephole2
- [(match_scratch:SI 4 "r")
- (set (match_operand:SI 0 "register_operand" "")
- (match_operand:SI 2 "memory_operand" ""))
- (set (match_operand:SI 1 "register_operand" "")
- (match_operand:SI 3 "memory_operand" ""))
- (match_dup 4)]
- "TARGET_HAS_CDX"
- [(const_int 0)]
-{
- if (gen_ldstwm_peep (true, 2, operands[4], operands))
- DONE;
- else
- FAIL;
-})
-
-(define_peephole2
- [(match_scratch:SI 24 "r")
- (set (match_operand:SI 12 "memory_operand" "")
- (match_operand:SI 0 "register_operand" ""))
- (set (match_operand:SI 13 "memory_operand" "")
- (match_operand:SI 1 "register_operand" ""))
- (set (match_operand:SI 14 "memory_operand" "")
- (match_operand:SI 2 "register_operand" ""))
- (set (match_operand:SI 15 "memory_operand" "")
- (match_operand:SI 3 "register_operand" ""))
- (set (match_operand:SI 16 "memory_operand" "")
- (match_operand:SI 4 "register_operand" ""))
- (set (match_operand:SI 17 "memory_operand" "")
- (match_operand:SI 5 "register_operand" ""))
- (set (match_operand:SI 18 "memory_operand" "")
- (match_operand:SI 6 "register_operand" ""))
- (set (match_operand:SI 19 "memory_operand" "")
- (match_operand:SI 7 "register_operand" ""))
- (set (match_operand:SI 20 "memory_operand" "")
- (match_operand:SI 8 "register_operand" ""))
- (set (match_operand:SI 21 "memory_operand" "")
- (match_operand:SI 9 "register_operand" ""))
- (set (match_operand:SI 22 "memory_operand" "")
- (match_operand:SI 10 "register_operand" ""))
- (set (match_operand:SI 23 "memory_operand" "")
- (match_operand:SI 11 "register_operand" ""))
- (match_dup 24)]
- "TARGET_HAS_CDX"
- [(const_int 0)]
-{
- if (gen_ldstwm_peep (false, 12, operands[24], operands))
- DONE;
- else
- FAIL;
-})
-
-(define_peephole2
- [(match_scratch:SI 22 "r")
- (set (match_operand:SI 11 "memory_operand" "")
- (match_operand:SI 0 "register_operand" ""))
- (set (match_operand:SI 12 "memory_operand" "")
- (match_operand:SI 1 "register_operand" ""))
- (set (match_operand:SI 13 "memory_operand" "")
- (match_operand:SI 2 "register_operand" ""))
- (set (match_operand:SI 14 "memory_operand" "")
- (match_operand:SI 3 "register_operand" ""))
- (set (match_operand:SI 15 "memory_operand" "")
- (match_operand:SI 4 "register_operand" ""))
- (set (match_operand:SI 16 "memory_operand" "")
- (match_operand:SI 5 "register_operand" ""))
- (set (match_operand:SI 17 "memory_operand" "")
- (match_operand:SI 6 "register_operand" ""))
- (set (match_operand:SI 18 "memory_operand" "")
- (match_operand:SI 7 "register_operand" ""))
- (set (match_operand:SI 19 "memory_operand" "")
- (match_operand:SI 8 "register_operand" ""))
- (set (match_operand:SI 20 "memory_operand" "")
- (match_operand:SI 9 "register_operand" ""))
- (set (match_operand:SI 21 "memory_operand" "")
- (match_operand:SI 10 "register_operand" ""))
- (match_dup 22)]
- "TARGET_HAS_CDX"
- [(const_int 0)]
-{
- if (gen_ldstwm_peep (false, 11, operands[22], operands))
- DONE;
- else
- FAIL;
-})
-
-(define_peephole2
- [(match_scratch:SI 20 "r")
- (set (match_operand:SI 10 "memory_operand" "")
- (match_operand:SI 0 "register_operand" ""))
- (set (match_operand:SI 11 "memory_operand" "")
- (match_operand:SI 1 "register_operand" ""))
- (set (match_operand:SI 12 "memory_operand" "")
- (match_operand:SI 2 "register_operand" ""))
- (set (match_operand:SI 13 "memory_operand" "")
- (match_operand:SI 3 "register_operand" ""))
- (set (match_operand:SI 14 "memory_operand" "")
- (match_operand:SI 4 "register_operand" ""))
- (set (match_operand:SI 15 "memory_operand" "")
- (match_operand:SI 5 "register_operand" ""))
- (set (match_operand:SI 16 "memory_operand" "")
- (match_operand:SI 6 "register_operand" ""))
- (set (match_operand:SI 17 "memory_operand" "")
- (match_operand:SI 7 "register_operand" ""))
- (set (match_operand:SI 18 "memory_operand" "")
- (match_operand:SI 8 "register_operand" ""))
- (set (match_operand:SI 19 "memory_operand" "")
- (match_operand:SI 9 "register_operand" ""))
- (match_dup 20)]
- "TARGET_HAS_CDX"
- [(const_int 0)]
-{
- if (gen_ldstwm_peep (false, 10, operands[20], operands))
- DONE;
- else
- FAIL;
-})
-
-(define_peephole2
- [(match_scratch:SI 18 "r")
- (set (match_operand:SI 9 "memory_operand" "")
- (match_operand:SI 0 "register_operand" ""))
- (set (match_operand:SI 10 "memory_operand" "")
- (match_operand:SI 1 "register_operand" ""))
- (set (match_operand:SI 11 "memory_operand" "")
- (match_operand:SI 2 "register_operand" ""))
- (set (match_operand:SI 12 "memory_operand" "")
- (match_operand:SI 3 "register_operand" ""))
- (set (match_operand:SI 13 "memory_operand" "")
- (match_operand:SI 4 "register_operand" ""))
- (set (match_operand:SI 14 "memory_operand" "")
- (match_operand:SI 5 "register_operand" ""))
- (set (match_operand:SI 15 "memory_operand" "")
- (match_operand:SI 6 "register_operand" ""))
- (set (match_operand:SI 16 "memory_operand" "")
- (match_operand:SI 7 "register_operand" ""))
- (set (match_operand:SI 17 "memory_operand" "")
- (match_operand:SI 8 "register_operand" ""))
- (match_dup 18)]
- "TARGET_HAS_CDX"
- [(const_int 0)]
-{
- if (gen_ldstwm_peep (false, 9, operands[18], operands))
- DONE;
- else
- FAIL;
-})
-
-(define_peephole2
- [(match_scratch:SI 16 "r")
- (set (match_operand:SI 8 "memory_operand" "")
- (match_operand:SI 0 "register_operand" ""))
- (set (match_operand:SI 9 "memory_operand" "")
- (match_operand:SI 1 "register_operand" ""))
- (set (match_operand:SI 10 "memory_operand" "")
- (match_operand:SI 2 "register_operand" ""))
- (set (match_operand:SI 11 "memory_operand" "")
- (match_operand:SI 3 "register_operand" ""))
- (set (match_operand:SI 12 "memory_operand" "")
- (match_operand:SI 4 "register_operand" ""))
- (set (match_operand:SI 13 "memory_operand" "")
- (match_operand:SI 5 "register_operand" ""))
- (set (match_operand:SI 14 "memory_operand" "")
- (match_operand:SI 6 "register_operand" ""))
- (set (match_operand:SI 15 "memory_operand" "")
- (match_operand:SI 7 "register_operand" ""))
- (match_dup 16)]
- "TARGET_HAS_CDX"
- [(const_int 0)]
-{
- if (gen_ldstwm_peep (false, 8, operands[16], operands))
- DONE;
- else
- FAIL;
-})
-
-(define_peephole2
- [(match_scratch:SI 14 "r")
- (set (match_operand:SI 7 "memory_operand" "")
- (match_operand:SI 0 "register_operand" ""))
- (set (match_operand:SI 8 "memory_operand" "")
- (match_operand:SI 1 "register_operand" ""))
- (set (match_operand:SI 9 "memory_operand" "")
- (match_operand:SI 2 "register_operand" ""))
- (set (match_operand:SI 10 "memory_operand" "")
- (match_operand:SI 3 "register_operand" ""))
- (set (match_operand:SI 11 "memory_operand" "")
- (match_operand:SI 4 "register_operand" ""))
- (set (match_operand:SI 12 "memory_operand" "")
- (match_operand:SI 5 "register_operand" ""))
- (set (match_operand:SI 13 "memory_operand" "")
- (match_operand:SI 6 "register_operand" ""))
- (match_dup 14)]
- "TARGET_HAS_CDX"
- [(const_int 0)]
-{
- if (gen_ldstwm_peep (false, 7, operands[14], operands))
- DONE;
- else
- FAIL;
-})
-
-(define_peephole2
- [(match_scratch:SI 12 "r")
- (set (match_operand:SI 6 "memory_operand" "")
- (match_operand:SI 0 "register_operand" ""))
- (set (match_operand:SI 7 "memory_operand" "")
- (match_operand:SI 1 "register_operand" ""))
- (set (match_operand:SI 8 "memory_operand" "")
- (match_operand:SI 2 "register_operand" ""))
- (set (match_operand:SI 9 "memory_operand" "")
- (match_operand:SI 3 "register_operand" ""))
- (set (match_operand:SI 10 "memory_operand" "")
- (match_operand:SI 4 "register_operand" ""))
- (set (match_operand:SI 11 "memory_operand" "")
- (match_operand:SI 5 "register_operand" ""))
- (match_dup 12)]
- "TARGET_HAS_CDX"
- [(const_int 0)]
-{
- if (gen_ldstwm_peep (false, 6, operands[12], operands))
- DONE;
- else
- FAIL;
-})
-
-(define_peephole2
- [(match_scratch:SI 10 "r")
- (set (match_operand:SI 5 "memory_operand" "")
- (match_operand:SI 0 "register_operand" ""))
- (set (match_operand:SI 6 "memory_operand" "")
- (match_operand:SI 1 "register_operand" ""))
- (set (match_operand:SI 7 "memory_operand" "")
- (match_operand:SI 2 "register_operand" ""))
- (set (match_operand:SI 8 "memory_operand" "")
- (match_operand:SI 3 "register_operand" ""))
- (set (match_operand:SI 9 "memory_operand" "")
- (match_operand:SI 4 "register_operand" ""))
- (match_dup 10)]
- "TARGET_HAS_CDX"
- [(const_int 0)]
-{
- if (gen_ldstwm_peep (false, 5, operands[10], operands))
- DONE;
- else
- FAIL;
-})
-
-(define_peephole2
- [(match_scratch:SI 8 "r")
- (set (match_operand:SI 4 "memory_operand" "")
- (match_operand:SI 0 "register_operand" ""))
- (set (match_operand:SI 5 "memory_operand" "")
- (match_operand:SI 1 "register_operand" ""))
- (set (match_operand:SI 6 "memory_operand" "")
- (match_operand:SI 2 "register_operand" ""))
- (set (match_operand:SI 7 "memory_operand" "")
- (match_operand:SI 3 "register_operand" ""))
- (match_dup 8)]
- "TARGET_HAS_CDX"
- [(const_int 0)]
-{
- if (gen_ldstwm_peep (false, 4, operands[8], operands))
- DONE;
- else
- FAIL;
-})
-
-(define_peephole2
- [(match_scratch:SI 6 "r")
- (set (match_operand:SI 3 "memory_operand" "")
- (match_operand:SI 0 "register_operand" ""))
- (set (match_operand:SI 4 "memory_operand" "")
- (match_operand:SI 1 "register_operand" ""))
- (set (match_operand:SI 5 "memory_operand" "")
- (match_operand:SI 2 "register_operand" ""))
- (match_dup 6)]
- "TARGET_HAS_CDX"
- [(const_int 0)]
-{
- if (gen_ldstwm_peep (false, 3, operands[6], operands))
- DONE;
- else
- FAIL;
-})
-
-(define_peephole2
- [(match_scratch:SI 4 "r")
- (set (match_operand:SI 2 "memory_operand" "")
- (match_operand:SI 0 "register_operand" ""))
- (set (match_operand:SI 3 "memory_operand" "")
- (match_operand:SI 1 "register_operand" ""))
- (match_dup 4)]
- "TARGET_HAS_CDX"
- [(const_int 0)]
-{
- if (gen_ldstwm_peep (false, 2, operands[4], operands))
- DONE;
- else
- FAIL;
-})
-
diff --git a/gcc/config/nios2/linux.h b/gcc/config/nios2/linux.h
deleted file mode 100644
index 06c442e85f41..000000000000
--- a/gcc/config/nios2/linux.h
+++ /dev/null
@@ -1,53 +0,0 @@
-/* Definitions of target support for Altera Nios II systems
- running GNU/Linux with ELF format.
- Copyright (C) 2012-2024 Free Software Foundation, Inc.
- Contributed by Mentor Graphics, Inc.
-
- This file is part of GCC.
-
- GCC is free software; you can redistribute it and/or modify it
- under the terms of the GNU General Public License as published
- by the Free Software Foundation; either version 3, or (at your
- option) any later version.
-
- GCC is distributed in the hope that it will be useful, but WITHOUT
- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
- License for more details.
-
- You should have received a copy of the GNU General Public License
- along with GCC; see the file COPYING3. If not see
- <http://www.gnu.org/licenses/>. */
-
-#define TARGET_OS_CPP_BUILTINS() \
- do \
- { \
- GNU_USER_TARGET_OS_CPP_BUILTINS(); \
- } \
- while (0)
-
-#undef CPP_SPEC
-#define CPP_SPEC "%{posix:-D_POSIX_SOURCE} %{pthread:-D_REENTRANT}"
-
-#define GLIBC_DYNAMIC_LINKER "/lib/ld-linux-nios2.so.1"
-
-#undef MUSL_DYNAMIC_LINKER
-#define MUSL_DYNAMIC_LINKER "/lib/ld-musl-nios2.so.1"
-
-#undef LINK_SPEC
-#define LINK_SPEC LINK_SPEC_ENDIAN \
- "%{shared:-shared} \
- %{!shared: \
- %{!static: \
- %{rdynamic:-export-dynamic} \
- -dynamic-linker " GNU_USER_DYNAMIC_LINKER "} \
- %{static:-static}}"
-
-/* This toolchain implements the ABI for Linux Systems documented in the
- Nios II Processor Reference Handbook. */
-#define TARGET_LINUX_ABI 1
-
-/* For Linux, we have access to kernel support for atomic operations,
- add initialization for __sync_* builtins. */
-#undef TARGET_INIT_LIBFUNCS
-#define TARGET_INIT_LIBFUNCS nios2_init_libfuncs
diff --git a/gcc/config/nios2/nios2-ldstwm.sml b/gcc/config/nios2/nios2-ldstwm.sml
deleted file mode 100644
index fd79967d75b1..000000000000
--- a/gcc/config/nios2/nios2-ldstwm.sml
+++ /dev/null
@@ -1,277 +0,0 @@
-(* Auto-generate Nios II R2 CDX ldwm/stwm/push.n/pop.n patterns
- Copyright (C) 2014-2024 Free Software Foundation, Inc.
- Contributed by Mentor Graphics.
-
- This file is part of GCC.
-
- GCC is free software; you can redistribute it and/or modify it under
- the terms of the GNU General Public License as published by the Free
- Software Foundation; either version 3, or (at your option) any later
- version.
-
- GCC is distributed in the hope that it will be useful, but WITHOUT ANY
- WARRANTY; without even the implied warranty of MERCHANTABILITY or
- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
- for more details.
-
- You should have received a copy of the GNU General Public License
- along with GCC; see the file COPYING3. If not see
- <http://www.gnu.org/licenses/>.
-
- This is a Standard ML program. There are multiple Standard ML
- implementations widely available. We recommend the MLton optimizing
- SML compiler, due to its ease of creating a standalone executable.
-
- http://www.mlton.org/
-
- Or from your favourite OS's friendly packaging system. Tested with
- MLton Release 20130715, though other versions will probably work too.
-
- Run with:
- mlton -output a.out /path/to/gcc/config/nios2/nios2-ldstwm.sml
- ./a.out >/path/to/gcc/config/nios2/ldstwm.md
-*)
-
-datatype ld_st = ld | st;
-datatype push_pop = push | pop;
-datatype inc_dec = inc | dec;
-
-fun for ls f = map f ls;
-fun conds cond str = if cond then str else "";
-fun ints n = if n>=0 then (Int.toString n) else ("-" ^ (Int.toString (~n)));
-
-fun pushpop_pattern pptype n fp =
- let
- val sp_reg = "(reg:SI SP_REGNO)";
- val ra_reg = "(reg:SI RA_REGNO)";
- val fp_reg = "(reg:SI FP_REGNO)";
-
- fun sets lhs rhs = "(set " ^ lhs ^
- (if pptype=push then " "
- else " ") ^ rhs ^ ")";
- val sp_adj =
- "(set " ^ sp_reg ^ "\n " ^
- "(plus:SI " ^ sp_reg ^
- " (match_operand 1 \"const_int_operand\" \"\")))";
-
- fun reg i regi = "(reg:SI " ^ (ints regi) ^ ")";
- fun mem i opndi =
- if pptype=push then
- "(mem:SI (plus:SI (reg:SI SP_REGNO) (const_int " ^ (ints (~4*i)) ^ ")))"
- else
- "(match_operand:SI " ^
- (ints opndi) ^ " \"stack_memory_operand\" \"\")";
-
- val start = 1 + (if fp then 2 else 1);
- val lim = n + (if fp then 2 else 1);
- fun set_elt i regi opndi =
- if pptype=push then (sets (mem i opndi) (reg i regi))
- else (sets (reg i regi) (mem i opndi));
- fun get_elt_list (i, regi, opndi) =
- if i > lim then []
- else (set_elt i regi opndi) :: get_elt_list (i+1, regi-1, opndi+1);
-
- val set_elements = get_elt_list (start, 16+n-1, start+1);
-
- val ra_set = if pptype=push then sets (mem 1 2) ra_reg
- else sets ra_reg (mem 1 2);
- val fp_set = (conds fp (if pptype=push then sets (mem 2 3) fp_reg
- else sets fp_reg (mem 2 3)));
- val ret = (conds (pptype=pop) "(return)");
- val element_list =
- List.filter (fn x => x<>"")
- ([ret, sp_adj, ra_set, fp_set] @ set_elements);
-
- fun reg_index i = 16 + n - i;
- fun pop_opnds 0 spl = (conds fp ("fp" ^ spl)) ^ "ra"
- | pop_opnds n spl = "r" ^ (ints (reg_index n)) ^ spl ^ (pop_opnds (n-1) spl);
- fun push_opnds 0 spl = "ra" ^ (conds fp (spl ^ "fp"))
- | push_opnds n spl = (push_opnds (n-1) spl) ^ spl ^ "r" ^ (ints (reg_index n));
-
- val spadj_opnd = if pptype=push then 2 else (start+n);
- val spadj = ints spadj_opnd;
- val regsave_num = n + (if fp then 2 else 1);
-
- val ppname = if pptype=push then "push" else "pop";
- val name = if pptype=push then "push" ^ "_" ^ (push_opnds n "_")
- else "pop" ^ "_" ^ (pop_opnds n "_");
- in
- "(define_insn \"*cdx_" ^ name ^ "\"\n" ^
- " [(match_parallel 0 \"" ^
- (conds (pptype=pop) "pop_operation") ^ "\"\n" ^
- " [" ^ (String.concatWith ("\n ") element_list) ^ "])]\n" ^
- " \"TARGET_HAS_CDX && XVECLEN (operands[0], 0) == " ^
- (ints (length element_list)) ^
- (conds (pptype=push)
- ("\n && (-INTVAL (operands[1]) & 3) == 0\n" ^
- " && (-INTVAL (operands[1]) - " ^
- (ints (4*regsave_num)) ^ ") <= 60")) ^
- "\"\n" ^
- (if pptype=pop then
- "{\n" ^
- " rtx x = XEXP (operands[" ^ spadj ^ "], 0);\n" ^
- " operands[" ^ spadj ^ "] = REG_P (x) ? const0_rtx : XEXP (x, 1);\n" ^
- " return \"pop.n\\\\t{" ^ (pop_opnds n ", ") ^ "}, %" ^ spadj ^ "\";\n" ^
- "}\n"
- else
- "{\n" ^
- " operands[" ^ spadj ^ "] = " ^
- "GEN_INT (-INTVAL (operands[1]) - " ^ (ints (4*regsave_num)) ^ ");\n" ^
- " return \"push.n\\\\t{" ^ (push_opnds n ", ") ^ "}, %" ^ spadj ^ "\";\n" ^
- "}\n") ^
- " [(set_attr \"type\" \"" ^ ppname ^ "\")])\n\n"
- end;
-
-fun ldstwm_pattern ldst n id wb pc =
- let
- val ldstwm = (if ldst=ld then "ldwm" else "stwm");
- val name = "*cdx_" ^ ldstwm ^ (Int.toString n) ^
- (if id=inc then "_inc" else "_dec") ^
- (conds wb "_wb") ^ (conds pc "_ret");
- val base_reg_referenced_p = ref false;
- val base_regno = ints (n+1);
- fun plus_addr base offset =
- "(plus:SI " ^ base ^ " (const_int " ^ (ints offset) ^ "))";
- fun base_reg () =
- if !base_reg_referenced_p then
- "(match_dup " ^ base_regno ^ ")"
- else (base_reg_referenced_p := true;
- "(match_operand:SI " ^ base_regno ^
- " \"register_operand\" \"" ^ (conds wb "+&") ^ "r\")");
- fun reg i = "(match_operand:SI " ^ (ints i) ^
- " \"nios2_hard_register_operand\" \"" ^
- (conds (ldst=ld) "") ^ "\")";
-
- fun addr 1 = if id=inc then base_reg ()
- else plus_addr (base_reg ()) (~4)
- | addr i = let val offset = if id=inc then (i-1)*4 else (~i*4)
- in plus_addr (base_reg ()) offset end;
-
- fun mem i = "(mem:SI " ^ (addr i) ^ ")";
- fun lhs i = if ldst=ld then reg i else mem i;
- fun rhs i = if ldst=st then reg i else mem i;
- fun sets lhs rhs = "(set " ^ lhs ^ "\n " ^ rhs ^ ")";
- fun set_elements i =
- if i > n then []
- else (sets (lhs i) (rhs i)) :: (set_elements (i+1));
-
- fun opnds 1 = "%1"
- | opnds n = opnds(n-1) ^ ", %" ^ (Int.toString n);
-
- val asm_template = ldstwm ^ "\\\\t{" ^ (opnds n) ^ "}" ^
- (if id=inc
- then ", (%" ^ base_regno ^ ")++"
- else ", --(%" ^ base_regno ^ ")") ^
- (conds wb ", writeback") ^
- (conds pc ", ret");
- val wbtmp =
- if wb then
- (sets (base_reg ())
- (plus_addr (base_reg ())
- ((if id=inc then n else ~n)*4)))
- else "";
- val pctmp = conds pc "(return)";
- val set_list = List.filter (fn x => x<>"")
- ([pctmp, wbtmp] @ (set_elements 1));
- in
- if ldst=st andalso pc then ""
- else
- "(define_insn \"" ^ name ^ "\"\n" ^
- " [(match_parallel 0 \"" ^ ldstwm ^ "_operation\"\n" ^
- " [" ^ (String.concatWith ("\n ") set_list) ^ "])]\n" ^
- " \"TARGET_HAS_CDX && XVECLEN (operands[0], 0) == " ^
- (ints (length set_list)) ^ "\"\n" ^
- " \"" ^ asm_template ^ "\"\n" ^
- " [(set_attr \"type\" \"" ^ ldstwm ^ "\")])\n\n"
- end;
-
-fun peephole_pattern ldst n scratch_p =
- let
- fun sets lhs rhs = "(set " ^ lhs ^ "\n " ^ rhs ^ ")";
- fun single_set i indent =
- let val reg = "(match_operand:SI " ^ (ints i) ^
- " \"register_operand\" \"\")";
- val mem = "(match_operand:SI " ^ (ints (i+n)) ^
- " \"memory_operand\" \"\")";
- in
- if ldst=ld then sets reg mem
- else sets mem reg
- end;
-
- fun single_sets i =
- if i=n then []
- else (single_set i " ") :: (single_sets (i+1));
-
- val scratch = ints (2*n);
- val peephole_elements =
- let val tmp = single_sets 0 in
- if scratch_p
- then (["(match_scratch:SI " ^ scratch ^ " \"r\")"] @
- tmp @
- ["(match_dup " ^ scratch ^ ")"])
- else tmp
- end;
- in
- "(define_peephole2\n" ^
- " [" ^ (String.concatWith ("\n ") peephole_elements) ^ "]\n" ^
- " \"TARGET_HAS_CDX\"\n" ^
- " [(const_int 0)]\n" ^
- "{\n" ^
- " if (gen_ldstwm_peep (" ^
- (if ldst=st then "false" else "true") ^ ", " ^ (ints n) ^ ", " ^
- (if scratch_p then ("operands[" ^ scratch ^ "]") else "NULL_RTX") ^
- ", operands))\n" ^
- " DONE;\n" ^
- " else\n" ^
- " FAIL;\n" ^
- "})\n\n"
- end;
-
-
-print
-("/* Nios II R2 CDX ldwm/stwm/push.h/pop.n instruction patterns.\n" ^
- " This file was automatically generated using nios2-ldstwm.sml.\n" ^
- " Please do not edit manually.\n" ^
- "\n" ^
- " Copyright (C) 2014-2024 Free Software Foundation, Inc.\n" ^
- " Contributed by Mentor Graphics.\n" ^
- "\n" ^
- " This file is part of GCC.\n" ^
- "\n" ^
- " GCC is free software; you can redistribute it and/or modify it\n" ^
- " under the terms of the GNU General Public License as published\n" ^
- " by the Free Software Foundation; either version 3, or (at your\n" ^
- " option) any later version.\n" ^
- "\n" ^
- " GCC is distributed in the hope that it will be useful, but WITHOUT\n" ^
- " ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\n" ^
- " or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public\n" ^
- " License for more details.\n" ^
- "\n" ^
- " You should have received a copy of the GNU General Public License and\n" ^
- " a copy of the GCC Runtime Library Exception along with this program;\n" ^
- " see the files COPYING3 and COPYING.RUNTIME respectively. If not, see\n" ^
- " <http://www.gnu.org/licenses/>. */\n\n");
-
-fun seq a b = if a=b then [b]
- else a :: (seq (if a<b then a+1 else a-1) b);
-
-(* push/pop patterns *)
-for (seq 0 8) (fn n =>
- for [push, pop] (fn p =>
- for [true, false] (fn fp =>
- print (pushpop_pattern p n fp))));
-
-(* ldwm/stwm patterns *)
-for [ld, st] (fn l =>
- for (seq 1 12) (fn n =>
- for [inc, dec] (fn id =>
- for [true, false] (fn wb =>
- for [true, false] (fn pc =>
- print (ldstwm_pattern l n id wb pc))))));
-
-(* peephole patterns *)
-for [ld, st] (fn l =>
- for (seq 12 2) (fn n =>
- print (peephole_pattern l n true)));
-
diff --git a/gcc/config/nios2/nios2-opts.h b/gcc/config/nios2/nios2-opts.h
deleted file mode 100644
index 9ab7977ebf95..000000000000
--- a/gcc/config/nios2/nios2-opts.h
+++ /dev/null
@@ -1,88 +0,0 @@
-/* Definitions for option handling for Nios II.
- Copyright (C) 2013-2024 Free Software Foundation, Inc.
-
-This file is part of GCC.
-
-GCC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 3, or (at your option)
-any later version.
-
-GCC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GCC; see the file COPYING3. If not see
-<http://www.gnu.org/licenses/>. */
-
-#ifndef NIOS2_OPTS_H
-#define NIOS2_OPTS_H
-
-/* Enumerate the possible -mgpopt choices. */
-enum nios2_gpopt_type
-{
- gpopt_unspecified = -1,
- gpopt_none,
- gpopt_local,
- gpopt_global,
- gpopt_data,
- gpopt_all
-};
-
-
-/* Enumeration of all FPU insn codes. */
-#define N2FPU_ALL_CODES \
- N2FPU_CODE(fadds) N2FPU_CODE(fsubs) N2FPU_CODE(fmuls) N2FPU_CODE(fdivs) \
- N2FPU_CODE(fmins) N2FPU_CODE(fmaxs) \
- N2FPU_CODE(fnegs) N2FPU_CODE(fabss) N2FPU_CODE(fsqrts) \
- N2FPU_CODE(fsins) N2FPU_CODE(fcoss) N2FPU_CODE(ftans) N2FPU_CODE(fatans) \
- N2FPU_CODE(fexps) N2FPU_CODE(flogs) \
- N2FPU_CODE(fcmpeqs) N2FPU_CODE(fcmpnes) \
- N2FPU_CODE(fcmplts) N2FPU_CODE(fcmples) \
- N2FPU_CODE(fcmpgts) N2FPU_CODE(fcmpges) \
- \
- N2FPU_CODE(faddd) N2FPU_CODE(fsubd) N2FPU_CODE(fmuld) N2FPU_CODE(fdivd) \
- N2FPU_CODE(fmind) N2FPU_CODE(fmaxd) \
- N2FPU_CODE(fnegd) N2FPU_CODE(fabsd) N2FPU_CODE(fsqrtd) \
- N2FPU_CODE(fsind) N2FPU_CODE(fcosd) N2FPU_CODE(ftand) N2FPU_CODE(fatand) \
- N2FPU_CODE(fexpd) N2FPU_CODE(flogd) \
- N2FPU_CODE(fcmpeqd) N2FPU_CODE(fcmpned) \
- N2FPU_CODE(fcmpltd) N2FPU_CODE(fcmpled) \
- N2FPU_CODE(fcmpgtd) N2FPU_CODE(fcmpged) \
- \
- N2FPU_CODE(floatis) N2FPU_CODE(floatus) \
- N2FPU_CODE(floatid) N2FPU_CODE(floatud) \
- N2FPU_CODE(round) N2FPU_CODE(fixsi) N2FPU_CODE(fixsu) \
- N2FPU_CODE(fixdi) N2FPU_CODE(fixdu) \
- N2FPU_CODE(fextsd) N2FPU_CODE(ftruncds) \
- \
- N2FPU_CODE(fwrx) N2FPU_CODE(fwry) \
- N2FPU_CODE(frdxlo) N2FPU_CODE(frdxhi) N2FPU_CODE(frdy)
-
-enum n2fpu_code {
-#define N2FPU_CODE(name) n2fpu_ ## name,
- N2FPU_ALL_CODES
-#undef N2FPU_CODE
- n2fpu_code_num
-};
-
-/* An enumeration to indicate the custom code status; if values within 0--255
- are registered to an FPU insn, or custom insn. */
-enum nios2_ccs_code
-{
- CCS_UNUSED,
- CCS_FPU,
- CCS_BUILTIN_CALL
-};
-
-/* Supported Nios II Architectures. */
-enum nios2_arch_type
-{
- ARCH_R1=1,
- ARCH_R2
-};
-
-#endif
-
diff --git a/gcc/config/nios2/nios2-protos.h b/gcc/config/nios2/nios2-protos.h
deleted file mode 100644
index 049480c4976c..000000000000
--- a/gcc/config/nios2/nios2-protos.h
+++ /dev/null
@@ -1,72 +0,0 @@
-/* Subroutine declarations for Altera Nios II target support.
- Copyright (C) 2012-2024 Free Software Foundation, Inc.
- Contributed by Jonah Graham (jgraham@altera.com).
- Contributed by Mentor Graphics, Inc.
-
- This file is part of GCC.
-
- GCC is free software; you can redistribute it and/or modify it
- under the terms of the GNU General Public License as published
- by the Free Software Foundation; either version 3, or (at your
- option) any later version.
-
- GCC is distributed in the hope that it will be useful, but WITHOUT
- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
- License for more details.
-
- You should have received a copy of the GNU General Public License
- along with GCC; see the file COPYING3. If not see
- <http://www.gnu.org/licenses/>. */
-
-#ifndef GCC_NIOS2_PROTOS_H
-#define GCC_NIOS2_PROTOS_H
-
-extern int nios2_initial_elimination_offset (int, int);
-extern int nios2_can_use_return_insn (void);
-extern void nios2_expand_prologue (void);
-extern void nios2_expand_epilogue (bool);
-extern bool nios2_expand_return (void);
-extern void nios2_function_profiler (FILE *, int);
-extern bool nios2_fpu_insn_enabled (enum n2fpu_code);
-
-#ifdef RTX_CODE
-extern bool nios2_large_constant_p (rtx);
-extern bool nios2_large_constant_memory_operand_p (rtx);
-
-extern rtx nios2_split_large_constant (rtx, rtx);
-extern rtx nios2_split_large_constant_memory_operand (rtx);
-extern bool nios2_emit_move_sequence (rtx *, machine_mode);
-extern void nios2_emit_expensive_div (rtx *, machine_mode);
-extern void nios2_adjust_call_address (rtx *, rtx);
-
-extern rtx nios2_get_return_address (int);
-extern void nios2_set_return_address (rtx, rtx);
-
-extern bool nios2_validate_compare (machine_mode, rtx *, rtx *, rtx *);
-extern bool nios2_validate_fpu_compare (machine_mode, rtx *, rtx *, rtx *,
- bool);
-
-extern const char * nios2_fpu_insn_asm (enum n2fpu_code);
-extern const char * nios2_add_insn_asm (rtx_insn *, rtx *);
-
-extern bool nios2_legitimate_pic_operand_p (rtx);
-extern bool gprel_constant_p (rtx);
-extern bool r0rel_constant_p (rtx);
-extern bool nios2_regno_ok_for_base_p (int, bool);
-extern bool nios2_unspec_reloc_p (rtx);
-
-extern int nios2_label_align (rtx);
-extern bool nios2_cdx_narrow_form_p (rtx_insn *);
-
-extern bool pop_operation_p (rtx);
-extern bool ldstwm_operation_p (rtx, bool);
-extern bool gen_ldstwm_peep (bool, int, rtx, rtx *);
-
-extern void nios2_adjust_reg_alloc_order (void);
-
-extern pad_direction nios2_block_reg_padding (machine_mode, tree, int);
-
-#endif /* RTX_CODE */
-
-#endif /* GCC_NIOS2_PROTOS_H */
diff --git a/gcc/config/nios2/nios2.cc b/gcc/config/nios2/nios2.cc
deleted file mode 100644
index cb33c67ed2fd..000000000000
--- a/gcc/config/nios2/nios2.cc
+++ /dev/null
@@ -1,5630 +0,0 @@
-/* Target machine subroutines for Altera Nios II.
- Copyright (C) 2012-2024 Free Software Foundation, Inc.
- Contributed by Jonah Graham (jgraham@altera.com),
- Will Reece (wreece@altera.com), and Jeff DaSilva (jdasilva@altera.com).
- Contributed by Mentor Graphics, Inc.
-
- This file is part of GCC.
-
- GCC is free software; you can redistribute it and/or modify it
- under the terms of the GNU General Public License as published
- by the Free Software Foundation; either version 3, or (at your
- option) any later version.
-
- GCC is distributed in the hope that it will be useful, but WITHOUT
- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
- License for more details.
-
- You should have received a copy of the GNU General Public License
- along with GCC; see the file COPYING3. If not see
- <http://www.gnu.org/licenses/>. */
-
-#define IN_TARGET_CODE 1
-
-#include "config.h"
-#include "system.h"
-#include "coretypes.h"
-#include "backend.h"
-#include "target.h"
-#include "rtl.h"
-#include "tree.h"
-#include "stringpool.h"
-#include "attribs.h"
-#include "df.h"
-#include "memmodel.h"
-#include "tm_p.h"
-#include "optabs.h"
-#include "regs.h"
-#include "emit-rtl.h"
-#include "recog.h"
-#include "diagnostic-core.h"
-#include "output.h"
-#include "insn-attr.h"
-#include "flags.h"
-#include "explow.h"
-#include "calls.h"
-#include "varasm.h"
-#include "expr.h"
-#include "toplev.h"
-#include "langhooks.h"
-#include "stor-layout.h"
-#include "builtins.h"
-#include "tree-pass.h"
-#include "xregex.h"
-#include "opts.h"
-
-/* This file should be included last. */
-#include "target-def.h"
-
-/* Forward function declarations. */
-static bool nios2_symbolic_constant_p (rtx);
-static bool prologue_saved_reg_p (unsigned);
-static void nios2_load_pic_register (void);
-static void nios2_register_custom_code (unsigned int, enum nios2_ccs_code, int);
-static const char *nios2_unspec_reloc_name (int);
-static void nios2_register_builtin_fndecl (unsigned, tree);
-static rtx nios2_ldst_parallel (bool, bool, bool, rtx, int,
- unsigned HOST_WIDE_INT, bool);
-static int nios2_address_cost (rtx, machine_mode, addr_space_t, bool);
-
-/* Threshold for data being put into the small data/bss area, instead
- of the normal data area (references to the small data/bss area take
- 1 instruction, and use the global pointer, references to the normal
- data area takes 2 instructions). */
-unsigned HOST_WIDE_INT nios2_section_threshold = NIOS2_DEFAULT_GVALUE;
-
-struct GTY (()) machine_function
-{
- /* Current frame information, to be filled in by nios2_compute_frame_layout
- with register save masks, and offsets for the current function. */
-
- /* Mask of registers to save. */
- unsigned int save_mask;
- /* Number of bytes that the entire frame takes up. */
- int total_size;
- /* Number of bytes that variables take up. */
- int var_size;
- /* Number of bytes that outgoing arguments take up. */
- int args_size;
- /* Number of bytes needed to store registers in frame. */
- int save_reg_size;
- /* Number of bytes used to store callee-saved registers. */
- int callee_save_reg_size;
- /* Offset from new stack pointer to store registers. */
- int save_regs_offset;
- /* Offset from save_regs_offset to store frame pointer register. */
- int fp_save_offset;
- /* != 0 if function has a variable argument list. */
- int uses_anonymous_args;
- /* != 0 if frame layout already calculated. */
- int initialized;
-};
-
-/* State to track the assignment of custom codes to FPU/custom builtins. */
-static enum nios2_ccs_code custom_code_status[256];
-static int custom_code_index[256];
-/* Set to true if any conflicts (re-use of a code between 0-255) are found. */
-static bool custom_code_conflict = false;
-
-/* State for command-line options. */
-regex_t nios2_gprel_sec_regex;
-regex_t nios2_r0rel_sec_regex;
-
-
-/* Definition of builtin function types for nios2. */
-
-#define N2_FTYPES \
- N2_FTYPE(1, (SF)) \
- N2_FTYPE(1, (VOID)) \
- N2_FTYPE(2, (DF, DF)) \
- N2_FTYPE(3, (DF, DF, DF)) \
- N2_FTYPE(2, (DF, SF)) \
- N2_FTYPE(2, (DF, SI)) \
- N2_FTYPE(2, (DF, UI)) \
- N2_FTYPE(2, (SF, DF)) \
- N2_FTYPE(2, (SF, SF)) \
- N2_FTYPE(3, (SF, SF, SF)) \
- N2_FTYPE(2, (SF, SI)) \
- N2_FTYPE(2, (SF, UI)) \
- N2_FTYPE(2, (SI, CVPTR)) \
- N2_FTYPE(2, (SI, DF)) \
- N2_FTYPE(3, (SI, DF, DF)) \
- N2_FTYPE(2, (SI, SF)) \
- N2_FTYPE(3, (SI, SF, SF)) \
- N2_FTYPE(2, (SI, SI)) \
- N2_FTYPE(3, (SI, SI, SI)) \
- N2_FTYPE(3, (SI, VPTR, SI)) \
- N2_FTYPE(2, (UI, CVPTR)) \
- N2_FTYPE(2, (UI, DF)) \
- N2_FTYPE(2, (UI, SF)) \
- N2_FTYPE(2, (VOID, DF)) \
- N2_FTYPE(2, (VOID, SF)) \
- N2_FTYPE(2, (VOID, SI)) \
- N2_FTYPE(3, (VOID, SI, SI)) \
- N2_FTYPE(2, (VOID, VPTR)) \
- N2_FTYPE(3, (VOID, VPTR, SI))
-
-#define N2_FTYPE_OP1(R) N2_FTYPE_ ## R ## _VOID
-#define N2_FTYPE_OP2(R, A1) N2_FTYPE_ ## R ## _ ## A1
-#define N2_FTYPE_OP3(R, A1, A2) N2_FTYPE_ ## R ## _ ## A1 ## _ ## A2
-
-/* Expand ftcode enumeration. */
-enum nios2_ftcode {
-#define N2_FTYPE(N,ARGS) N2_FTYPE_OP ## N ARGS,
-N2_FTYPES
-#undef N2_FTYPE
-N2_FTYPE_MAX
-};
-
-/* Return the tree function type, based on the ftcode. */
-static tree
-nios2_ftype (enum nios2_ftcode ftcode)
-{
- static tree types[(int) N2_FTYPE_MAX];
-
- tree N2_TYPE_SF = float_type_node;
- tree N2_TYPE_DF = double_type_node;
- tree N2_TYPE_SI = integer_type_node;
- tree N2_TYPE_UI = unsigned_type_node;
- tree N2_TYPE_VOID = void_type_node;
-
- static const_tree N2_TYPE_CVPTR, N2_TYPE_VPTR;
- if (!N2_TYPE_CVPTR)
- {
- /* const volatile void *. */
- N2_TYPE_CVPTR
- = build_pointer_type (build_qualified_type (void_type_node,
- (TYPE_QUAL_CONST
- | TYPE_QUAL_VOLATILE)));
- /* volatile void *. */
- N2_TYPE_VPTR
- = build_pointer_type (build_qualified_type (void_type_node,
- TYPE_QUAL_VOLATILE));
- }
- if (types[(int) ftcode] == NULL_TREE)
- switch (ftcode)
- {
-#define N2_FTYPE_ARGS1(R) N2_TYPE_ ## R
-#define N2_FTYPE_ARGS2(R,A1) N2_TYPE_ ## R, N2_TYPE_ ## A1
-#define N2_FTYPE_ARGS3(R,A1,A2) N2_TYPE_ ## R, N2_TYPE_ ## A1, N2_TYPE_ ## A2
-#define N2_FTYPE(N,ARGS) \
- case N2_FTYPE_OP ## N ARGS: \
- types[(int) ftcode] \
- = build_function_type_list (N2_FTYPE_ARGS ## N ARGS, NULL_TREE); \
- break;
- N2_FTYPES
-#undef N2_FTYPE
- default: gcc_unreachable ();
- }
- return types[(int) ftcode];
-}
-
-
-/* Definition of FPU instruction descriptions. */
-
-struct nios2_fpu_insn_info
-{
- const char *name;
- int num_operands, *optvar;
- int opt, no_opt;
-#define N2F_DF 0x1
-#define N2F_DFREQ 0x2
-#define N2F_UNSAFE 0x4
-#define N2F_FINITE 0x8
-#define N2F_NO_ERRNO 0x10
- unsigned int flags;
- enum insn_code icode;
- enum nios2_ftcode ftcode;
-};
-
-/* Base macro for defining FPU instructions. */
-#define N2FPU_INSN_DEF_BASE(insn, nop, flags, icode, args) \
- { #insn, nop, &nios2_custom_ ## insn, OPT_mcustom_##insn##_, \
- OPT_mno_custom_##insn, flags, CODE_FOR_ ## icode, \
- N2_FTYPE_OP ## nop args }
-
-/* Arithmetic and math functions; 2 or 3 operand FP operations. */
-#define N2FPU_OP2(mode) (mode, mode)
-#define N2FPU_OP3(mode) (mode, mode, mode)
-#define N2FPU_INSN_DEF(code, icode, nop, flags, m, M) \
- N2FPU_INSN_DEF_BASE (f ## code ## m, nop, flags, \
- icode ## m ## f ## nop, N2FPU_OP ## nop (M ## F))
-#define N2FPU_INSN_SF(code, nop, flags) \
- N2FPU_INSN_DEF (code, code, nop, flags, s, S)
-#define N2FPU_INSN_DF(code, nop, flags) \
- N2FPU_INSN_DEF (code, code, nop, flags | N2F_DF, d, D)
-
-/* Compare instructions, 3 operand FP operation with a SI result. */
-#define N2FPU_CMP_DEF(code, flags, m, M) \
- N2FPU_INSN_DEF_BASE (fcmp ## code ## m, 3, flags, \
- nios2_s ## code ## m ## f, (SI, M ## F, M ## F))
-#define N2FPU_CMP_SF(code) N2FPU_CMP_DEF (code, 0, s, S)
-#define N2FPU_CMP_DF(code) N2FPU_CMP_DEF (code, N2F_DF, d, D)
-
-/* The order of definition needs to be maintained consistent with
- enum n2fpu_code in nios2-opts.h. */
-struct nios2_fpu_insn_info nios2_fpu_insn[] =
- {
- /* Single precision instructions. */
- N2FPU_INSN_SF (add, 3, 0),
- N2FPU_INSN_SF (sub, 3, 0),
- N2FPU_INSN_SF (mul, 3, 0),
- N2FPU_INSN_SF (div, 3, 0),
- /* Due to textual difference between min/max and smin/smax. */
- N2FPU_INSN_DEF (min, smin, 3, N2F_FINITE, s, S),
- N2FPU_INSN_DEF (max, smax, 3, N2F_FINITE, s, S),
- N2FPU_INSN_SF (neg, 2, 0),
- N2FPU_INSN_SF (abs, 2, 0),
- N2FPU_INSN_SF (sqrt, 2, 0),
- N2FPU_INSN_SF (sin, 2, N2F_UNSAFE),
- N2FPU_INSN_SF (cos, 2, N2F_UNSAFE),
- N2FPU_INSN_SF (tan, 2, N2F_UNSAFE),
- N2FPU_INSN_SF (atan, 2, N2F_UNSAFE),
- N2FPU_INSN_SF (exp, 2, N2F_UNSAFE),
- N2FPU_INSN_SF (log, 2, N2F_UNSAFE),
- /* Single precision compares. */
- N2FPU_CMP_SF (eq), N2FPU_CMP_SF (ne),
- N2FPU_CMP_SF (lt), N2FPU_CMP_SF (le),
- N2FPU_CMP_SF (gt), N2FPU_CMP_SF (ge),
-
- /* Double precision instructions. */
- N2FPU_INSN_DF (add, 3, 0),
- N2FPU_INSN_DF (sub, 3, 0),
- N2FPU_INSN_DF (mul, 3, 0),
- N2FPU_INSN_DF (div, 3, 0),
- /* Due to textual difference between min/max and smin/smax. */
- N2FPU_INSN_DEF (min, smin, 3, N2F_FINITE, d, D),
- N2FPU_INSN_DEF (max, smax, 3, N2F_FINITE, d, D),
- N2FPU_INSN_DF (neg, 2, 0),
- N2FPU_INSN_DF (abs, 2, 0),
- N2FPU_INSN_DF (sqrt, 2, 0),
- N2FPU_INSN_DF (sin, 2, N2F_UNSAFE),
- N2FPU_INSN_DF (cos, 2, N2F_UNSAFE),
- N2FPU_INSN_DF (tan, 2, N2F_UNSAFE),
- N2FPU_INSN_DF (atan, 2, N2F_UNSAFE),
- N2FPU_INSN_DF (exp, 2, N2F_UNSAFE),
- N2FPU_INSN_DF (log, 2, N2F_UNSAFE),
- /* Double precision compares. */
- N2FPU_CMP_DF (eq), N2FPU_CMP_DF (ne),
- N2FPU_CMP_DF (lt), N2FPU_CMP_DF (le),
- N2FPU_CMP_DF (gt), N2FPU_CMP_DF (ge),
-
- /* Conversion instructions. */
- N2FPU_INSN_DEF_BASE (floatis, 2, 0, floatsisf2, (SF, SI)),
- N2FPU_INSN_DEF_BASE (floatus, 2, 0, floatunssisf2, (SF, UI)),
- N2FPU_INSN_DEF_BASE (floatid, 2, 0, floatsidf2, (DF, SI)),
- N2FPU_INSN_DEF_BASE (floatud, 2, 0, floatunssidf2, (DF, UI)),
- N2FPU_INSN_DEF_BASE (round, 2, N2F_NO_ERRNO, lroundsfsi2, (SI, SF)),
- N2FPU_INSN_DEF_BASE (fixsi, 2, 0, fix_truncsfsi2, (SI, SF)),
- N2FPU_INSN_DEF_BASE (fixsu, 2, 0, fixuns_truncsfsi2, (UI, SF)),
- N2FPU_INSN_DEF_BASE (fixdi, 2, 0, fix_truncdfsi2, (SI, DF)),
- N2FPU_INSN_DEF_BASE (fixdu, 2, 0, fixuns_truncdfsi2, (UI, DF)),
- N2FPU_INSN_DEF_BASE (fextsd, 2, 0, extendsfdf2, (DF, SF)),
- N2FPU_INSN_DEF_BASE (ftruncds, 2, 0, truncdfsf2, (SF, DF)),
-
- /* X, Y access instructions. */
- N2FPU_INSN_DEF_BASE (fwrx, 2, N2F_DFREQ, nios2_fwrx, (VOID, DF)),
- N2FPU_INSN_DEF_BASE (fwry, 2, N2F_DFREQ, nios2_fwry, (VOID, SF)),
- N2FPU_INSN_DEF_BASE (frdxlo, 1, N2F_DFREQ, nios2_frdxlo, (SF)),
- N2FPU_INSN_DEF_BASE (frdxhi, 1, N2F_DFREQ, nios2_frdxhi, (SF)),
- N2FPU_INSN_DEF_BASE (frdy, 1, N2F_DFREQ, nios2_frdy, (SF))
- };
-
-/* Some macros for ease of access. */
-#define N2FPU(code) nios2_fpu_insn[(int) code]
-#define N2FPU_ENABLED_P(code) (N2FPU_N(code) >= 0)
-#define N2FPU_N(code) (*N2FPU(code).optvar)
-#define N2FPU_NAME(code) (N2FPU(code).name)
-#define N2FPU_ICODE(code) (N2FPU(code).icode)
-#define N2FPU_FTCODE(code) (N2FPU(code).ftcode)
-#define N2FPU_FINITE_P(code) (N2FPU(code).flags & N2F_FINITE)
-#define N2FPU_UNSAFE_P(code) (N2FPU(code).flags & N2F_UNSAFE)
-#define N2FPU_NO_ERRNO_P(code) (N2FPU(code).flags & N2F_NO_ERRNO)
-#define N2FPU_DOUBLE_P(code) (N2FPU(code).flags & N2F_DF)
-#define N2FPU_DOUBLE_REQUIRED_P(code) (N2FPU(code).flags & N2F_DFREQ)
-
-/* Same as above, but for cases where using only the op part is shorter. */
-#define N2FPU_OP(op) N2FPU(n2fpu_ ## op)
-#define N2FPU_OP_NAME(op) N2FPU_NAME(n2fpu_ ## op)
-#define N2FPU_OP_ENABLED_P(op) N2FPU_ENABLED_P(n2fpu_ ## op)
-
-/* Export the FPU insn enabled predicate to nios2.md. */
-bool
-nios2_fpu_insn_enabled (enum n2fpu_code code)
-{
- return N2FPU_ENABLED_P (code);
-}
-
-/* Return true if COND comparison for mode MODE is enabled under current
- settings. */
-
-static bool
-nios2_fpu_compare_enabled (enum rtx_code cond, machine_mode mode)
-{
- if (mode == SFmode)
- switch (cond)
- {
- case EQ: return N2FPU_OP_ENABLED_P (fcmpeqs);
- case NE: return N2FPU_OP_ENABLED_P (fcmpnes);
- case GT: return N2FPU_OP_ENABLED_P (fcmpgts);
- case GE: return N2FPU_OP_ENABLED_P (fcmpges);
- case LT: return N2FPU_OP_ENABLED_P (fcmplts);
- case LE: return N2FPU_OP_ENABLED_P (fcmples);
- default: break;
- }
- else if (mode == DFmode)
- switch (cond)
- {
- case EQ: return N2FPU_OP_ENABLED_P (fcmpeqd);
- case NE: return N2FPU_OP_ENABLED_P (fcmpned);
- case GT: return N2FPU_OP_ENABLED_P (fcmpgtd);
- case GE: return N2FPU_OP_ENABLED_P (fcmpged);
- case LT: return N2FPU_OP_ENABLED_P (fcmpltd);
- case LE: return N2FPU_OP_ENABLED_P (fcmpled);
- default: break;
- }
- return false;
-}
-
-/* Stack layout and calling conventions. */
-
-#define NIOS2_STACK_ALIGN(LOC) \
- (((LOC) + ((PREFERRED_STACK_BOUNDARY / BITS_PER_UNIT) - 1)) \
- & ~((PREFERRED_STACK_BOUNDARY / BITS_PER_UNIT) - 1))
-
-/* Return the bytes needed to compute the frame pointer from the current
- stack pointer. */
-static int
-nios2_compute_frame_layout (void)
-{
- unsigned int regno;
- unsigned int save_mask = 0;
- int total_size;
- int var_size;
- int out_args_size;
- int save_reg_size;
- int callee_save_reg_size;
-
- if (cfun->machine->initialized)
- return cfun->machine->total_size;
-
- /* Calculate space needed for gp registers. */
- save_reg_size = 0;
- for (regno = 0; regno <= LAST_GP_REG; regno++)
- if (prologue_saved_reg_p (regno))
- {
- save_mask |= 1 << regno;
- save_reg_size += 4;
- }
-
- /* If we are saving any callee-save register, then assume
- push.n/pop.n should be used. Make sure RA is saved, and
- contiguous registers starting from r16-- are all saved. */
- if (TARGET_HAS_CDX && save_reg_size != 0)
- {
- if ((save_mask & (1 << RA_REGNO)) == 0)
- {
- save_mask |= 1 << RA_REGNO;
- save_reg_size += 4;
- }
-
- for (regno = 23; regno >= 16; regno--)
- if ((save_mask & (1 << regno)) != 0)
- {
- /* Starting from highest numbered callee-saved
- register that is used, make sure all regs down
- to r16 is saved, to maintain contiguous range
- for push.n/pop.n. */
- unsigned int i;
- for (i = regno - 1; i >= 16; i--)
- if ((save_mask & (1 << i)) == 0)
- {
- save_mask |= 1 << i;
- save_reg_size += 4;
- }
- break;
- }
- }
-
- callee_save_reg_size = save_reg_size;
-
- /* If we call eh_return, we need to save the EH data registers. */
- if (crtl->calls_eh_return)
- {
- unsigned i;
- unsigned r;
-
- for (i = 0; (r = EH_RETURN_DATA_REGNO (i)) != INVALID_REGNUM; i++)
- if (!(save_mask & (1 << r)))
- {
- save_mask |= 1 << r;
- save_reg_size += 4;
- }
- }
-
- cfun->machine->fp_save_offset = 0;
- if (save_mask & (1 << HARD_FRAME_POINTER_REGNUM))
- {
- int fp_save_offset = 0;
- for (regno = 0; regno < HARD_FRAME_POINTER_REGNUM; regno++)
- if (save_mask & (1 << regno))
- fp_save_offset += 4;
-
- cfun->machine->fp_save_offset = fp_save_offset;
- }
-
- var_size = NIOS2_STACK_ALIGN (get_frame_size ());
- out_args_size = NIOS2_STACK_ALIGN (crtl->outgoing_args_size);
- total_size = var_size + out_args_size;
-
- save_reg_size = NIOS2_STACK_ALIGN (save_reg_size);
- total_size += save_reg_size;
- total_size += NIOS2_STACK_ALIGN (crtl->args.pretend_args_size);
-
- /* Save other computed information. */
- cfun->machine->save_mask = save_mask;
- cfun->machine->total_size = total_size;
- cfun->machine->var_size = var_size;
- cfun->machine->args_size = out_args_size;
- cfun->machine->save_reg_size = save_reg_size;
- cfun->machine->callee_save_reg_size = callee_save_reg_size;
- cfun->machine->initialized = reload_completed;
- cfun->machine->save_regs_offset = out_args_size + var_size;
-
- return total_size;
-}
-
-/* Generate save/restore of register REGNO at SP + OFFSET. Used by the
- prologue/epilogue expand routines. */
-static void
-save_reg (int regno, unsigned offset)
-{
- rtx reg = gen_rtx_REG (SImode, regno);
- rtx addr = plus_constant (Pmode, stack_pointer_rtx, offset, false);
- rtx_insn *insn = emit_move_insn (gen_frame_mem (Pmode, addr), reg);
- RTX_FRAME_RELATED_P (insn) = 1;
-}
-
-static void
-restore_reg (int regno, unsigned offset)
-{
- rtx reg = gen_rtx_REG (SImode, regno);
- rtx addr = plus_constant (Pmode, stack_pointer_rtx, offset, false);
- rtx_insn *insn = emit_move_insn (reg, gen_frame_mem (Pmode, addr));
- /* Tag epilogue unwind note. */
- add_reg_note (insn, REG_CFA_RESTORE, reg);
- RTX_FRAME_RELATED_P (insn) = 1;
-}
-
-/* This routine tests for the base register update SET in load/store
- multiple RTL insns, used in pop_operation_p and ldstwm_operation_p. */
-static bool
-base_reg_adjustment_p (rtx set, rtx *base_reg, rtx *offset)
-{
- if (GET_CODE (set) == SET
- && REG_P (SET_DEST (set))
- && GET_CODE (SET_SRC (set)) == PLUS
- && REG_P (XEXP (SET_SRC (set), 0))
- && rtx_equal_p (SET_DEST (set), XEXP (SET_SRC (set), 0))
- && CONST_INT_P (XEXP (SET_SRC (set), 1)))
- {
- *base_reg = XEXP (SET_SRC (set), 0);
- *offset = XEXP (SET_SRC (set), 1);
- return true;
- }
- return false;
-}
-
-/* Does the CFA note work for push/pop prologue/epilogue instructions. */
-static void
-nios2_create_cfa_notes (rtx_insn *insn, bool epilogue_p)
-{
- int i = 0;
- rtx base_reg, offset, elt, pat = PATTERN (insn);
- if (epilogue_p)
- {
- elt = XVECEXP (pat, 0, 0);
- if (GET_CODE (elt) == RETURN)
- i++;
- elt = XVECEXP (pat, 0, i);
- if (base_reg_adjustment_p (elt, &base_reg, &offset))
- {
- add_reg_note (insn, REG_CFA_ADJUST_CFA, copy_rtx (elt));
- i++;
- }
- for (; i < XVECLEN (pat, 0); i++)
- {
- elt = SET_DEST (XVECEXP (pat, 0, i));
- gcc_assert (REG_P (elt));
- add_reg_note (insn, REG_CFA_RESTORE, elt);
- }
- }
- else
- {
- /* Tag each of the prologue sets. */
- for (i = 0; i < XVECLEN (pat, 0); i++)
- RTX_FRAME_RELATED_P (XVECEXP (pat, 0, i)) = 1;
- }
-}
-
-/* Temp regno used inside prologue/epilogue. */
-#define TEMP_REG_NUM 8
-
-/* Emit conditional trap for checking stack limit. SIZE is the number of
- additional bytes required.
-
- GDB prologue analysis depends on this generating a direct comparison
- to the SP register, so the adjustment to add SIZE needs to be done on
- the other operand to the comparison. Use TEMP_REG_NUM as a temporary,
- if necessary. */
-static void
-nios2_emit_stack_limit_check (int size)
-{
- rtx sum = NULL_RTX;
-
- if (GET_CODE (stack_limit_rtx) == SYMBOL_REF)
- {
- /* This generates a %hiadj/%lo pair with the constant size
- add handled by the relocations. */
- sum = gen_rtx_REG (Pmode, TEMP_REG_NUM);
- emit_move_insn (sum, plus_constant (Pmode, stack_limit_rtx, size));
- }
- else if (!REG_P (stack_limit_rtx))
- sorry ("Unknown form for stack limit expression");
- else if (size == 0)
- sum = stack_limit_rtx;
- else if (SMALL_INT (size))
- {
- sum = gen_rtx_REG (Pmode, TEMP_REG_NUM);
- emit_move_insn (sum, plus_constant (Pmode, stack_limit_rtx, size));
- }
- else
- {
- sum = gen_rtx_REG (Pmode, TEMP_REG_NUM);
- emit_move_insn (sum, gen_int_mode (size, Pmode));
- emit_insn (gen_add2_insn (sum, stack_limit_rtx));
- }
-
- emit_insn (gen_ctrapsi4 (gen_rtx_LTU (VOIDmode, stack_pointer_rtx, sum),
- stack_pointer_rtx, sum, GEN_INT (3)));
-}
-
-static rtx_insn *
-nios2_emit_add_constant (rtx reg, HOST_WIDE_INT immed)
-{
- rtx_insn *insn;
- if (SMALL_INT (immed))
- insn = emit_insn (gen_add2_insn (reg, gen_int_mode (immed, Pmode)));
- else
- {
- rtx tmp = gen_rtx_REG (Pmode, TEMP_REG_NUM);
- emit_move_insn (tmp, gen_int_mode (immed, Pmode));
- insn = emit_insn (gen_add2_insn (reg, tmp));
- }
- return insn;
-}
-
-static rtx_insn *
-nios2_adjust_stack (int sp_adjust, bool epilogue_p)
-{
- enum reg_note note_kind = REG_NOTE_MAX;
- rtx_insn *insn = NULL;
- if (sp_adjust)
- {
- if (SMALL_INT (sp_adjust))
- insn = emit_insn (gen_add2_insn (stack_pointer_rtx,
- gen_int_mode (sp_adjust, Pmode)));
- else
- {
- rtx tmp = gen_rtx_REG (Pmode, TEMP_REG_NUM);
- emit_move_insn (tmp, gen_int_mode (sp_adjust, Pmode));
- insn = emit_insn (gen_add2_insn (stack_pointer_rtx, tmp));
- /* Attach a note indicating what happened. */
- if (!epilogue_p)
- note_kind = REG_FRAME_RELATED_EXPR;
- }
- if (epilogue_p)
- note_kind = REG_CFA_ADJUST_CFA;
- if (note_kind != REG_NOTE_MAX)
- {
- rtx cfa_adj = gen_rtx_SET (stack_pointer_rtx,
- plus_constant (Pmode, stack_pointer_rtx,
- sp_adjust));
- add_reg_note (insn, note_kind, cfa_adj);
- }
- RTX_FRAME_RELATED_P (insn) = 1;
- }
- return insn;
-}
-
-void
-nios2_expand_prologue (void)
-{
- unsigned int regno;
- int total_frame_size, save_offset;
- int sp_offset; /* offset from base_reg to final stack value. */
- int save_regs_base; /* offset from base_reg to register save area. */
- rtx_insn *insn;
-
- total_frame_size = nios2_compute_frame_layout ();
-
- if (flag_stack_usage_info)
- current_function_static_stack_size = total_frame_size;
-
- /* When R2 CDX push.n/stwm is available, arrange for stack frame to be built
- using them. */
- if (TARGET_HAS_CDX
- && (cfun->machine->save_reg_size != 0
- || cfun->machine->uses_anonymous_args))
- {
- unsigned int regmask = cfun->machine->save_mask;
- unsigned int callee_save_regs = regmask & 0xffff0000;
- unsigned int caller_save_regs = regmask & 0x0000ffff;
- int push_immed = 0;
- int pretend_args_size = NIOS2_STACK_ALIGN (crtl->args.pretend_args_size);
- rtx stack_mem =
- gen_frame_mem (SImode, plus_constant (Pmode, stack_pointer_rtx, -4));
-
- /* Check that there is room for the entire stack frame before doing
- any SP adjustments or pushes. */
- if (crtl->limit_stack)
- nios2_emit_stack_limit_check (total_frame_size);
-
- if (pretend_args_size)
- {
- if (cfun->machine->uses_anonymous_args)
- {
- /* Emit a stwm to push copy of argument registers onto
- the stack for va_arg processing. */
- unsigned int r, mask = 0, n = pretend_args_size / 4;
- for (r = LAST_ARG_REGNO - n + 1; r <= LAST_ARG_REGNO; r++)
- mask |= (1 << r);
- insn = emit_insn (nios2_ldst_parallel
- (false, false, false, stack_mem,
- -pretend_args_size, mask, false));
- /* Tag first SP adjustment as frame-related. */
- RTX_FRAME_RELATED_P (XVECEXP (PATTERN (insn), 0, 0)) = 1;
- RTX_FRAME_RELATED_P (insn) = 1;
- }
- else
- nios2_adjust_stack (-pretend_args_size, false);
- }
- if (callee_save_regs)
- {
- /* Emit a push.n to save registers and optionally allocate
- push_immed extra bytes on the stack. */
- int sp_adjust;
- if (caller_save_regs)
- /* Can't allocate extra stack space yet. */
- push_immed = 0;
- else if (cfun->machine->save_regs_offset <= 60)
- /* Stack adjustment fits entirely in the push.n. */
- push_immed = cfun->machine->save_regs_offset;
- else if (frame_pointer_needed
- && cfun->machine->fp_save_offset == 0)
- /* Deferring the entire stack adjustment until later
- allows us to use a mov.n instead of a 32-bit addi
- instruction to set the frame pointer. */
- push_immed = 0;
- else
- /* Splitting the stack adjustment between the push.n
- and an explicit adjustment makes it more likely that
- we can use spdeci.n for the explicit part. */
- push_immed = 60;
- sp_adjust = -(cfun->machine->callee_save_reg_size + push_immed);
- insn = emit_insn (nios2_ldst_parallel (false, false, false,
- stack_mem, sp_adjust,
- callee_save_regs, false));
- nios2_create_cfa_notes (insn, false);
- RTX_FRAME_RELATED_P (insn) = 1;
- }
-
- if (caller_save_regs)
- {
- /* Emit a stwm to save the EH data regs, r4-r7. */
- int caller_save_size = (cfun->machine->save_reg_size
- - cfun->machine->callee_save_reg_size);
- gcc_assert ((caller_save_regs & ~0xf0) == 0);
- insn = emit_insn (nios2_ldst_parallel
- (false, false, false, stack_mem,
- -caller_save_size, caller_save_regs, false));
- nios2_create_cfa_notes (insn, false);
- RTX_FRAME_RELATED_P (insn) = 1;
- }
-
- save_regs_base = push_immed;
- sp_offset = -(cfun->machine->save_regs_offset - push_immed);
- }
- /* The non-CDX cases decrement the stack pointer, to prepare for individual
- register saves to the stack. */
- else if (!SMALL_INT (total_frame_size))
- {
- /* We need an intermediary point, this will point at the spill block. */
- nios2_adjust_stack (cfun->machine->save_regs_offset - total_frame_size,
- false);
- save_regs_base = 0;
- sp_offset = -cfun->machine->save_regs_offset;
- if (crtl->limit_stack)
- nios2_emit_stack_limit_check (cfun->machine->save_regs_offset);
- }
- else if (total_frame_size)
- {
- nios2_adjust_stack (-total_frame_size, false);
- save_regs_base = cfun->machine->save_regs_offset;
- sp_offset = 0;
- if (crtl->limit_stack)
- nios2_emit_stack_limit_check (0);
- }
- else
- save_regs_base = sp_offset = 0;
-
- /* Save the registers individually in the non-CDX case. */
- if (!TARGET_HAS_CDX)
- {
- save_offset = save_regs_base + cfun->machine->save_reg_size;
-
- for (regno = LAST_GP_REG; regno > 0; regno--)
- if (cfun->machine->save_mask & (1 << regno))
- {
- save_offset -= 4;
- save_reg (regno, save_offset);
- }
- }
-
- /* Set the hard frame pointer. */
- if (frame_pointer_needed)
- {
- int fp_save_offset = save_regs_base + cfun->machine->fp_save_offset;
- insn =
- (fp_save_offset == 0
- ? emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx)
- : emit_insn (gen_add3_insn (hard_frame_pointer_rtx,
- stack_pointer_rtx,
- gen_int_mode (fp_save_offset, Pmode))));
- RTX_FRAME_RELATED_P (insn) = 1;
- }
-
- /* Allocate sp_offset more bytes in the stack frame. */
- nios2_adjust_stack (sp_offset, false);
-
- /* Load the PIC register if needed. */
- if (crtl->uses_pic_offset_table)
- nios2_load_pic_register ();
-
- /* If we are profiling, make sure no instructions are scheduled before
- the call to mcount. */
- if (crtl->profile)
- emit_insn (gen_blockage ());
-}
-
-void
-nios2_expand_epilogue (bool sibcall_p)
-{
- rtx_insn *insn;
- rtx cfa_adj;
- int total_frame_size;
- int sp_adjust, save_offset;
- unsigned int regno;
-
- if (!sibcall_p && nios2_can_use_return_insn ())
- {
- emit_jump_insn (gen_return ());
- return;
- }
-
- emit_insn (gen_blockage ());
-
- total_frame_size = nios2_compute_frame_layout ();
- if (frame_pointer_needed)
- {
- /* Recover the stack pointer. */
- insn =
- (cfun->machine->fp_save_offset == 0
- ? emit_move_insn (stack_pointer_rtx, hard_frame_pointer_rtx)
- : emit_insn (gen_add3_insn
- (stack_pointer_rtx, hard_frame_pointer_rtx,
- gen_int_mode (-cfun->machine->fp_save_offset, Pmode))));
- cfa_adj = plus_constant (Pmode, stack_pointer_rtx,
- (total_frame_size
- - cfun->machine->save_regs_offset));
- add_reg_note (insn, REG_CFA_DEF_CFA, cfa_adj);
- RTX_FRAME_RELATED_P (insn) = 1;
-
- save_offset = 0;
- sp_adjust = total_frame_size - cfun->machine->save_regs_offset;
- }
- else if (!SMALL_INT (total_frame_size))
- {
- nios2_adjust_stack (cfun->machine->save_regs_offset, true);
- save_offset = 0;
- sp_adjust = total_frame_size - cfun->machine->save_regs_offset;
- }
- else
- {
- save_offset = cfun->machine->save_regs_offset;
- sp_adjust = total_frame_size;
- }
-
- if (!TARGET_HAS_CDX)
- {
- /* Generate individual register restores. */
- save_offset += cfun->machine->save_reg_size;
-
- for (regno = LAST_GP_REG; regno > 0; regno--)
- if (cfun->machine->save_mask & (1 << regno))
- {
- save_offset -= 4;
- restore_reg (regno, save_offset);
- }
- nios2_adjust_stack (sp_adjust, true);
- }
- else if (cfun->machine->save_reg_size == 0)
- {
- /* Nothing to restore, just recover the stack position. */
- nios2_adjust_stack (sp_adjust, true);
- }
- else
- {
- /* Emit CDX pop.n/ldwm to restore registers and optionally return. */
- unsigned int regmask = cfun->machine->save_mask;
- unsigned int callee_save_regs = regmask & 0xffff0000;
- unsigned int caller_save_regs = regmask & 0x0000ffff;
- int callee_save_size = cfun->machine->callee_save_reg_size;
- int caller_save_size = cfun->machine->save_reg_size - callee_save_size;
- int pretend_args_size = NIOS2_STACK_ALIGN (crtl->args.pretend_args_size);
- bool ret_p = (!pretend_args_size && !crtl->calls_eh_return
- && !sibcall_p);
-
- if (!ret_p || caller_save_size > 0)
- sp_adjust = save_offset;
- else
- sp_adjust = (save_offset > 60 ? save_offset - 60 : 0);
-
- save_offset -= sp_adjust;
-
- nios2_adjust_stack (sp_adjust, true);
-
- if (caller_save_regs)
- {
- /* Emit a ldwm to restore EH data regs. */
- rtx stack_mem = gen_frame_mem (SImode, stack_pointer_rtx);
- insn = emit_insn (nios2_ldst_parallel
- (true, true, true, stack_mem,
- caller_save_size, caller_save_regs, false));
- RTX_FRAME_RELATED_P (insn) = 1;
- nios2_create_cfa_notes (insn, true);
- }
-
- if (callee_save_regs)
- {
- int sp_adjust = save_offset + callee_save_size;
- rtx stack_mem;
- if (ret_p)
- {
- /* Emit a pop.n to restore regs and return. */
- stack_mem =
- gen_frame_mem (SImode,
- gen_rtx_PLUS (Pmode, stack_pointer_rtx,
- gen_int_mode (sp_adjust - 4,
- Pmode)));
- insn =
- emit_jump_insn (nios2_ldst_parallel (true, false, false,
- stack_mem, sp_adjust,
- callee_save_regs, ret_p));
- RTX_FRAME_RELATED_P (insn) = 1;
- /* No need to attach CFA notes since we cannot step over
- a return. */
- return;
- }
- else
- {
- /* If no return, we have to use the ldwm form. */
- stack_mem = gen_frame_mem (SImode, stack_pointer_rtx);
- insn =
- emit_insn (nios2_ldst_parallel (true, true, true,
- stack_mem, sp_adjust,
- callee_save_regs, ret_p));
- RTX_FRAME_RELATED_P (insn) = 1;
- nios2_create_cfa_notes (insn, true);
- }
- }
-
- if (pretend_args_size)
- nios2_adjust_stack (pretend_args_size, true);
- }
-
- /* Add in the __builtin_eh_return stack adjustment. */
- if (crtl->calls_eh_return)
- emit_insn (gen_add2_insn (stack_pointer_rtx, EH_RETURN_STACKADJ_RTX));
-
- if (!sibcall_p)
- emit_jump_insn (gen_simple_return ());
-}
-
-bool
-nios2_expand_return (void)
-{
- /* If CDX is available, generate a pop.n instruction to do both
- the stack pop and return. */
- if (TARGET_HAS_CDX)
- {
- int total_frame_size = nios2_compute_frame_layout ();
- int sp_adjust = (cfun->machine->save_regs_offset
- + cfun->machine->callee_save_reg_size);
- gcc_assert (sp_adjust == total_frame_size);
- if (sp_adjust != 0)
- {
- rtx mem =
- gen_frame_mem (SImode,
- plus_constant (Pmode, stack_pointer_rtx,
- sp_adjust - 4, false));
- rtx_insn *insn =
- emit_jump_insn (nios2_ldst_parallel (true, false, false,
- mem, sp_adjust,
- cfun->machine->save_mask,
- true));
- RTX_FRAME_RELATED_P (insn) = 1;
- /* No need to create CFA notes since we can't step over
- a return. */
- return true;
- }
- }
- return false;
-}
-
-/* Implement RETURN_ADDR_RTX. Note, we do not support moving
- back to a previous frame. */
-rtx
-nios2_get_return_address (int count)
-{
- if (count != 0)
- return const0_rtx;
-
- return get_hard_reg_initial_val (Pmode, RA_REGNO);
-}
-
-/* Emit code to change the current function's return address to
- ADDRESS. SCRATCH is available as a scratch register, if needed.
- ADDRESS and SCRATCH are both word-mode GPRs. */
-void
-nios2_set_return_address (rtx address, rtx scratch)
-{
- nios2_compute_frame_layout ();
- if (cfun->machine->save_mask & (1 << RA_REGNO))
- {
- unsigned offset = cfun->machine->save_reg_size - 4;
- rtx base;
-
- if (frame_pointer_needed)
- base = hard_frame_pointer_rtx;
- else
- {
- base = stack_pointer_rtx;
- offset += cfun->machine->save_regs_offset;
-
- if (!SMALL_INT (offset))
- {
- emit_move_insn (scratch, gen_int_mode (offset, Pmode));
- emit_insn (gen_add2_insn (scratch, base));
- base = scratch;
- offset = 0;
- }
- }
- if (offset)
- base = plus_constant (Pmode, base, offset);
- emit_move_insn (gen_rtx_MEM (Pmode, base), address);
- }
- else
- emit_move_insn (gen_rtx_REG (Pmode, RA_REGNO), address);
-}
-
-/* Implement FUNCTION_PROFILER macro. */
-void
-nios2_function_profiler (FILE *file, int labelno ATTRIBUTE_UNUSED)
-{
- fprintf (file, "\tmov\tr8, ra\n");
- if (flag_pic == 1)
- {
- fprintf (file, "\tnextpc\tr2\n");
- fprintf (file, "\t1: movhi\tr3, %%hiadj(_gp_got - 1b)\n");
- fprintf (file, "\taddi\tr3, r3, %%lo(_gp_got - 1b)\n");
- fprintf (file, "\tadd\tr2, r2, r3\n");
- fprintf (file, "\tldw\tr2, %%call(_mcount)(r2)\n");
- fprintf (file, "\tcallr\tr2\n");
- }
- else if (flag_pic == 2)
- {
- fprintf (file, "\tnextpc\tr2\n");
- fprintf (file, "\t1: movhi\tr3, %%hiadj(_gp_got - 1b)\n");
- fprintf (file, "\taddi\tr3, r3, %%lo(_gp_got - 1b)\n");
- fprintf (file, "\tadd\tr2, r2, r3\n");
- fprintf (file, "\tmovhi\tr3, %%call_hiadj(_mcount)\n");
- fprintf (file, "\taddi\tr3, r3, %%call_lo(_mcount)\n");
- fprintf (file, "\tadd\tr3, r2, r3\n");
- fprintf (file, "\tldw\tr2, 0(r3)\n");
- fprintf (file, "\tcallr\tr2\n");
- }
- else
- fprintf (file, "\tcall\t_mcount\n");
- fprintf (file, "\tmov\tra, r8\n");
-}
-
-/* Dump stack layout. */
-static void
-nios2_dump_frame_layout (FILE *file)
-{
- fprintf (file, "\t%s Current Frame Info\n", ASM_COMMENT_START);
- fprintf (file, "\t%s total_size = %d\n", ASM_COMMENT_START,
- cfun->machine->total_size);
- fprintf (file, "\t%s var_size = %d\n", ASM_COMMENT_START,
- cfun->machine->var_size);
- fprintf (file, "\t%s args_size = %d\n", ASM_COMMENT_START,
- cfun->machine->args_size);
- fprintf (file, "\t%s save_reg_size = %d\n", ASM_COMMENT_START,
- cfun->machine->save_reg_size);
- fprintf (file, "\t%s initialized = %d\n", ASM_COMMENT_START,
- cfun->machine->initialized);
- fprintf (file, "\t%s save_regs_offset = %d\n", ASM_COMMENT_START,
- cfun->machine->save_regs_offset);
- fprintf (file, "\t%s is_leaf = %d\n", ASM_COMMENT_START,
- crtl->is_leaf);
- fprintf (file, "\t%s frame_pointer_needed = %d\n", ASM_COMMENT_START,
- frame_pointer_needed);
- fprintf (file, "\t%s pretend_args_size = %d\n", ASM_COMMENT_START,
- crtl->args.pretend_args_size);
-}
-
-/* Return true if REGNO should be saved in the prologue. */
-static bool
-prologue_saved_reg_p (unsigned regno)
-{
- gcc_assert (GP_REG_P (regno));
-
- if (df_regs_ever_live_p (regno) && !call_used_or_fixed_reg_p (regno))
- return true;
-
- if (regno == HARD_FRAME_POINTER_REGNUM && frame_pointer_needed)
- return true;
-
- if (regno == PIC_OFFSET_TABLE_REGNUM && crtl->uses_pic_offset_table)
- return true;
-
- if (regno == RA_REGNO && df_regs_ever_live_p (RA_REGNO))
- return true;
-
- return false;
-}
-
-/* Implement TARGET_CAN_ELIMINATE. */
-static bool
-nios2_can_eliminate (const int from ATTRIBUTE_UNUSED, const int to)
-{
- if (to == STACK_POINTER_REGNUM)
- return !frame_pointer_needed;
- return true;
-}
-
-/* Implement INITIAL_ELIMINATION_OFFSET macro. */
-int
-nios2_initial_elimination_offset (int from, int to)
-{
- int offset;
-
- nios2_compute_frame_layout ();
-
- /* Set OFFSET to the offset from the stack pointer. */
- switch (from)
- {
- case FRAME_POINTER_REGNUM:
- /* This is the high end of the local variable storage, not the
- hard frame pointer. */
- offset = cfun->machine->args_size + cfun->machine->var_size;
- break;
-
- case ARG_POINTER_REGNUM:
- offset = cfun->machine->total_size;
- offset -= crtl->args.pretend_args_size;
- break;
-
- default:
- gcc_unreachable ();
- }
-
- /* If we are asked for the frame pointer offset, then adjust OFFSET
- by the offset from the frame pointer to the stack pointer. */
- if (to == HARD_FRAME_POINTER_REGNUM)
- offset -= (cfun->machine->save_regs_offset
- + cfun->machine->fp_save_offset);
-
- return offset;
-}
-
-/* Return nonzero if this function is known to have a null epilogue.
- This allows the optimizer to omit jumps to jumps if no stack
- was created. */
-int
-nios2_can_use_return_insn (void)
-{
- int total_frame_size;
-
- if (!reload_completed || crtl->profile)
- return 0;
-
- total_frame_size = nios2_compute_frame_layout ();
-
- /* If CDX is available, check if we can return using a
- single pop.n instruction. */
- if (TARGET_HAS_CDX
- && !frame_pointer_needed
- && cfun->machine->save_regs_offset <= 60
- && (cfun->machine->save_mask & 0x80000000) != 0
- && (cfun->machine->save_mask & 0xffff) == 0
- && crtl->args.pretend_args_size == 0)
- return true;
-
- return total_frame_size == 0;
-}
-
-
-/* Check and signal some warnings/errors on FPU insn options. */
-static void
-nios2_custom_check_insns (void)
-{
- unsigned int i, j;
- bool errors = false;
-
- for (i = 0; i < ARRAY_SIZE (nios2_fpu_insn); i++)
- if (N2FPU_ENABLED_P (i) && N2FPU_DOUBLE_P (i))
- {
- for (j = 0; j < ARRAY_SIZE (nios2_fpu_insn); j++)
- if (N2FPU_DOUBLE_REQUIRED_P (j) && ! N2FPU_ENABLED_P (j))
- {
- error ("switch %<-mcustom-%s%> is required for "
- "double-precision floating-point", N2FPU_NAME (j));
- errors = true;
- }
- break;
- }
-
- if (errors || custom_code_conflict)
- fatal_error (input_location,
- "conflicting use of %<-mcustom%> switches, "
- "target attributes, "
- "and/or %<__builtin_custom_%> functions");
-}
-
-static void
-nios2_set_fpu_custom_code (enum n2fpu_code code, int n, bool override_p)
-{
- if (override_p || N2FPU_N (code) == -1)
- N2FPU_N (code) = n;
- nios2_register_custom_code (n, CCS_FPU, (int) code);
-}
-
-/* Type to represent a standard FPU config. */
-struct nios2_fpu_config
-{
- const char *name;
- bool set_sp_constants;
- int code[n2fpu_code_num];
-};
-
-#define NIOS2_FPU_CONFIG_NUM 4
-static struct nios2_fpu_config custom_fpu_config[NIOS2_FPU_CONFIG_NUM];
-
-static void
-nios2_init_fpu_configs (void)
-{
- struct nios2_fpu_config* cfg;
- int i = 0;
-#define NEXT_FPU_CONFIG \
- do { \
- cfg = &custom_fpu_config[i++]; \
- memset (cfg, -1, sizeof (struct nios2_fpu_config));\
- } while (0)
-
- NEXT_FPU_CONFIG;
- cfg->name = "60-1";
- cfg->set_sp_constants = true;
- cfg->code[n2fpu_fmuls] = 252;
- cfg->code[n2fpu_fadds] = 253;
- cfg->code[n2fpu_fsubs] = 254;
-
- NEXT_FPU_CONFIG;
- cfg->name = "60-2";
- cfg->set_sp_constants = true;
- cfg->code[n2fpu_fmuls] = 252;
- cfg->code[n2fpu_fadds] = 253;
- cfg->code[n2fpu_fsubs] = 254;
- cfg->code[n2fpu_fdivs] = 255;
-
- NEXT_FPU_CONFIG;
- cfg->name = "72-3";
- cfg->set_sp_constants = true;
- cfg->code[n2fpu_floatus] = 243;
- cfg->code[n2fpu_fixsi] = 244;
- cfg->code[n2fpu_floatis] = 245;
- cfg->code[n2fpu_fcmpgts] = 246;
- cfg->code[n2fpu_fcmples] = 249;
- cfg->code[n2fpu_fcmpeqs] = 250;
- cfg->code[n2fpu_fcmpnes] = 251;
- cfg->code[n2fpu_fmuls] = 252;
- cfg->code[n2fpu_fadds] = 253;
- cfg->code[n2fpu_fsubs] = 254;
- cfg->code[n2fpu_fdivs] = 255;
-
- NEXT_FPU_CONFIG;
- cfg->name = "fph2";
- cfg->code[n2fpu_fabss] = 224;
- cfg->code[n2fpu_fnegs] = 225;
- cfg->code[n2fpu_fcmpnes] = 226;
- cfg->code[n2fpu_fcmpeqs] = 227;
- cfg->code[n2fpu_fcmpges] = 228;
- cfg->code[n2fpu_fcmpgts] = 229;
- cfg->code[n2fpu_fcmples] = 230;
- cfg->code[n2fpu_fcmplts] = 231;
- cfg->code[n2fpu_fmaxs] = 232;
- cfg->code[n2fpu_fmins] = 233;
- cfg->code[n2fpu_round] = 248;
- cfg->code[n2fpu_fixsi] = 249;
- cfg->code[n2fpu_floatis] = 250;
- cfg->code[n2fpu_fsqrts] = 251;
- cfg->code[n2fpu_fmuls] = 252;
- cfg->code[n2fpu_fadds] = 253;
- cfg->code[n2fpu_fsubs] = 254;
- cfg->code[n2fpu_fdivs] = 255;
-
-#undef NEXT_FPU_CONFIG
- gcc_assert (i == NIOS2_FPU_CONFIG_NUM);
-}
-
-static struct nios2_fpu_config *
-nios2_match_custom_fpu_cfg (const char *cfgname, const char *endp)
-{
- int i;
- for (i = 0; i < NIOS2_FPU_CONFIG_NUM; i++)
- {
- bool match = !(endp != NULL
- ? strncmp (custom_fpu_config[i].name, cfgname,
- endp - cfgname)
- : strcmp (custom_fpu_config[i].name, cfgname));
- if (match)
- return &custom_fpu_config[i];
- }
- return NULL;
-}
-
-/* Use CFGNAME to lookup FPU config, ENDP if not NULL marks end of string.
- OVERRIDE is true if loaded config codes should overwrite current state. */
-static void
-nios2_handle_custom_fpu_cfg (const char *cfgname, const char *endp,
- bool override)
-{
- struct nios2_fpu_config *cfg = nios2_match_custom_fpu_cfg (cfgname, endp);
- if (cfg)
- {
- unsigned int i;
- for (i = 0; i < ARRAY_SIZE (nios2_fpu_insn); i++)
- if (cfg->code[i] >= 0)
- nios2_set_fpu_custom_code ((enum n2fpu_code) i, cfg->code[i],
- override);
- if (cfg->set_sp_constants)
- flag_single_precision_constant = 1;
- }
- else
- warning (0, "ignoring unrecognized switch %<-mcustom-fpu-cfg%> "
- "value %<%s%>", cfgname);
-
- /* Guard against errors in the standard configurations. */
- nios2_custom_check_insns ();
-}
-
-/* Check individual FPU insn options, and register custom code. */
-static void
-nios2_handle_custom_fpu_insn_option (int fpu_insn_index)
-{
- int param = N2FPU_N (fpu_insn_index);
-
- if (param >= 0 && param <= 255)
- nios2_register_custom_code (param, CCS_FPU, fpu_insn_index);
-
- /* Valid values are 0-255, but also allow -1 so that the
- -mno-custom-<opt> switches work. */
- else if (param != -1)
- error ("switch %<-mcustom-%s%> value %d must be between 0 and 255",
- N2FPU_NAME (fpu_insn_index), param);
-}
-
-/* Allocate a chunk of memory for per-function machine-dependent data. */
-static struct machine_function *
-nios2_init_machine_status (void)
-{
- return ggc_cleared_alloc<machine_function> ();
-}
-
-/* Implement TARGET_OPTION_OVERRIDE. */
-static void
-nios2_option_override (void)
-{
- unsigned int i;
-
-#ifdef SUBTARGET_OVERRIDE_OPTIONS
- SUBTARGET_OVERRIDE_OPTIONS;
-#endif
-
- /* Check for unsupported options. */
- if (flag_pic && !TARGET_LINUX_ABI)
- sorry ("position-independent code requires the Linux ABI");
- if (flag_pic && stack_limit_rtx
- && GET_CODE (stack_limit_rtx) == SYMBOL_REF)
- sorry ("PIC support for %<-fstack-limit-symbol%>");
-
- /* Function to allocate machine-dependent function status. */
- init_machine_status = &nios2_init_machine_status;
-
- nios2_section_threshold
- = (OPTION_SET_P (g_switch_value)
- ? g_switch_value : NIOS2_DEFAULT_GVALUE);
-
- if (nios2_gpopt_option == gpopt_unspecified)
- {
- /* Default to -mgpopt unless -fpic or -fPIC. */
- if (flag_pic)
- nios2_gpopt_option = gpopt_none;
- else
- nios2_gpopt_option = gpopt_local;
- }
-
- /* GP-relative and r0-relative addressing don't make sense for PIC. */
- if (flag_pic)
- {
- if (nios2_gpopt_option != gpopt_none)
- error ("%<-mgpopt%> not supported with PIC");
- if (nios2_gprel_sec)
- error ("%<-mgprel-sec=%> not supported with PIC");
- if (nios2_r0rel_sec)
- error ("%<-mr0rel-sec=%> not supported with PIC");
- }
-
- /* Process -mgprel-sec= and -m0rel-sec=. */
- if (nios2_gprel_sec)
- {
- if (regcomp (&nios2_gprel_sec_regex, nios2_gprel_sec,
- REG_EXTENDED | REG_NOSUB))
- error ("%<-mgprel-sec=%> argument is not a valid regular expression");
- }
- if (nios2_r0rel_sec)
- {
- if (regcomp (&nios2_r0rel_sec_regex, nios2_r0rel_sec,
- REG_EXTENDED | REG_NOSUB))
- error ("%<-mr0rel-sec=%> argument is not a valid regular expression");
- }
-
- /* If we don't have mul, we don't have mulx either! */
- if (!TARGET_HAS_MUL && TARGET_HAS_MULX)
- target_flags &= ~MASK_HAS_MULX;
-
- /* Optional BMX and CDX instructions only make sense for R2. */
- if (!TARGET_ARCH_R2)
- {
- if (TARGET_HAS_BMX)
- error ("BMX instructions are only supported with R2 architecture");
- if (TARGET_HAS_CDX)
- error ("CDX instructions are only supported with R2 architecture");
- }
-
- /* R2 is little-endian only. */
- if (TARGET_ARCH_R2 && TARGET_BIG_ENDIAN)
- error ("R2 architecture is little-endian only");
-
- /* Initialize default FPU configurations. */
- nios2_init_fpu_configs ();
-
- /* Set up default handling for floating point custom instructions.
-
- Putting things in this order means that the -mcustom-fpu-cfg=
- switch will always be overridden by individual -mcustom-fadds=
- switches, regardless of the order in which they were specified
- on the command line.
-
- This behavior of prioritization of individual -mcustom-<insn>=
- options before the -mcustom-fpu-cfg= switch is maintained for
- compatibility. */
- if (nios2_custom_fpu_cfg_string && *nios2_custom_fpu_cfg_string)
- nios2_handle_custom_fpu_cfg (nios2_custom_fpu_cfg_string, NULL, false);
-
- /* Handle options for individual FPU insns. */
- for (i = 0; i < ARRAY_SIZE (nios2_fpu_insn); i++)
- nios2_handle_custom_fpu_insn_option (i);
-
- nios2_custom_check_insns ();
-
- /* Save the initial options in case the user does function specific
- options. */
- target_option_default_node = target_option_current_node
- = build_target_option_node (&global_options, &global_options_set);
-}
-
-
-/* Return true if CST is a constant within range of movi/movui/movhi. */
-static bool
-nios2_simple_const_p (const_rtx cst)
-{
- if (!CONST_INT_P (cst))
- return false;
- HOST_WIDE_INT val = INTVAL (cst);
- return SMALL_INT (val) || SMALL_INT_UNSIGNED (val) || UPPER16_INT (val);
-}
-
-/* Compute a (partial) cost for rtx X. Return true if the complete
- cost has been computed, and false if subexpressions should be
- scanned. In either case, *TOTAL contains the cost result. */
-static bool
-nios2_rtx_costs (rtx x, machine_mode mode,
- int outer_code,
- int opno,
- int *total, bool speed)
-{
- int code = GET_CODE (x);
-
- switch (code)
- {
- case CONST_INT:
- if (INTVAL (x) == 0 || nios2_simple_const_p (x))
- {
- *total = COSTS_N_INSNS (0);
- return true;
- }
- else
- {
- /* High + lo_sum. */
- *total = COSTS_N_INSNS (1);
- return true;
- }
-
- case LABEL_REF:
- case SYMBOL_REF:
- case CONST:
- case CONST_DOUBLE:
- if (gprel_constant_p (x) || r0rel_constant_p (x))
- {
- *total = COSTS_N_INSNS (1);
- return true;
- }
- else
- {
- /* High + lo_sum. */
- *total = COSTS_N_INSNS (1);
- return true;
- }
-
- case HIGH:
- {
- /* This is essentially a constant. */
- *total = COSTS_N_INSNS (0);
- return true;
- }
-
- case LO_SUM:
- {
- *total = COSTS_N_INSNS (0);
- return true;
- }
-
- case AND:
- {
- /* Recognize 'nor' insn pattern. */
- if (GET_CODE (XEXP (x, 0)) == NOT
- && GET_CODE (XEXP (x, 1)) == NOT)
- {
- *total = COSTS_N_INSNS (1);
- return true;
- }
- return false;
- }
-
- /* For insns that have an execution latency (3 cycles), don't
- penalize by the full amount since we can often schedule
- to avoid it. */
- case MULT:
- {
- if (!TARGET_HAS_MUL)
- *total = COSTS_N_INSNS (5); /* Guess? */
- else if (speed)
- *total = COSTS_N_INSNS (2); /* Latency adjustment. */
- else
- *total = COSTS_N_INSNS (1);
- if (TARGET_HAS_MULX && GET_MODE (x) == DImode)
- {
- enum rtx_code c0 = GET_CODE (XEXP (x, 0));
- enum rtx_code c1 = GET_CODE (XEXP (x, 1));
- if ((c0 == SIGN_EXTEND && c1 == SIGN_EXTEND)
- || (c0 == ZERO_EXTEND && c1 == ZERO_EXTEND))
- /* This is the <mul>sidi3 pattern, which expands into 4 insns,
- 2 multiplies and 2 moves. */
- {
- *total = *total * 2 + COSTS_N_INSNS (2);
- return true;
- }
- }
- return false;
- }
-
- case DIV:
- {
- if (!TARGET_HAS_DIV)
- *total = COSTS_N_INSNS (5); /* Guess? */
- else if (speed)
- *total = COSTS_N_INSNS (2); /* Latency adjustment. */
- else
- *total = COSTS_N_INSNS (1);
- return false;
- }
-
- case ASHIFT:
- case ASHIFTRT:
- case LSHIFTRT:
- case ROTATE:
- {
- if (!speed)
- *total = COSTS_N_INSNS (1);
- else
- *total = COSTS_N_INSNS (2); /* Latency adjustment. */
- return false;
- }
-
- case ZERO_EXTRACT:
- if (TARGET_HAS_BMX)
- {
- *total = COSTS_N_INSNS (1);
- return true;
- }
- return false;
-
- case SIGN_EXTEND:
- {
- if (MEM_P (XEXP (x, 0)))
- *total = COSTS_N_INSNS (1);
- else
- *total = COSTS_N_INSNS (3);
- return false;
- }
-
- case MEM:
- {
- rtx addr = XEXP (x, 0);
-
- /* Account for cost of different addressing modes. */
- *total = nios2_address_cost (addr, mode, ADDR_SPACE_GENERIC, speed);
-
- if (outer_code == SET && opno == 0)
- /* Stores execute in 1 cycle accounted for by
- the outer SET. */
- ;
- else if (outer_code == SET || outer_code == SIGN_EXTEND
- || outer_code == ZERO_EXTEND)
- /* Latency adjustment. */
- {
- if (speed)
- *total += COSTS_N_INSNS (1);
- }
- else
- /* This is going to have to be split into a load. */
- *total += COSTS_N_INSNS (speed ? 2 : 1);
- return true;
- }
-
- default:
- return false;
- }
-}
-
-/* Implement TARGET_PREFERRED_RELOAD_CLASS. */
-static reg_class_t
-nios2_preferred_reload_class (rtx x ATTRIBUTE_UNUSED, reg_class_t regclass)
-{
- return regclass == NO_REGS ? GENERAL_REGS : regclass;
-}
-
-/* Emit a call to __tls_get_addr. TI is the argument to this function.
- RET is an RTX for the return value location. The entire insn sequence
- is returned. */
-static GTY(()) rtx nios2_tls_symbol;
-
-static rtx
-nios2_call_tls_get_addr (rtx ti)
-{
- rtx arg = gen_rtx_REG (Pmode, FIRST_ARG_REGNO);
- rtx ret = gen_rtx_REG (Pmode, FIRST_RETVAL_REGNO);
- rtx fn;
- rtx_insn *insn;
-
- if (!nios2_tls_symbol)
- nios2_tls_symbol = init_one_libfunc ("__tls_get_addr");
-
- emit_move_insn (arg, ti);
- fn = gen_rtx_MEM (QImode, nios2_tls_symbol);
- insn = emit_call_insn (gen_call_value (ret, fn, const0_rtx));
- RTL_CONST_CALL_P (insn) = 1;
- use_reg (&CALL_INSN_FUNCTION_USAGE (insn), ret);
- use_reg (&CALL_INSN_FUNCTION_USAGE (insn), arg);
-
- return ret;
-}
-
-/* Return true for large offsets requiring hiadj/lo relocation pairs. */
-static bool
-nios2_large_offset_p (int unspec)
-{
- gcc_assert (nios2_unspec_reloc_name (unspec) != NULL);
-
- if (flag_pic == 2
- /* FIXME: TLS GOT offset relocations will eventually also get this
- treatment, after binutils support for those are also completed. */
- && (unspec == UNSPEC_PIC_SYM || unspec == UNSPEC_PIC_CALL_SYM))
- return true;
-
- /* 'gotoff' offsets are always hiadj/lo. */
- if (unspec == UNSPEC_PIC_GOTOFF_SYM)
- return true;
-
- return false;
-}
-
-/* Return true for conforming unspec relocations. Also used in
- constraints.md and predicates.md. */
-bool
-nios2_unspec_reloc_p (rtx op)
-{
- return (GET_CODE (op) == CONST
- && GET_CODE (XEXP (op, 0)) == UNSPEC
- && ! nios2_large_offset_p (XINT (XEXP (op, 0), 1)));
-}
-
-static bool
-nios2_large_unspec_reloc_p (rtx op)
-{
- return (GET_CODE (op) == CONST
- && GET_CODE (XEXP (op, 0)) == UNSPEC
- && nios2_large_offset_p (XINT (XEXP (op, 0), 1)));
-}
-
-/* Helper to generate unspec constant. */
-static rtx
-nios2_unspec_offset (rtx loc, int unspec)
-{
- return gen_rtx_CONST (Pmode, gen_rtx_UNSPEC (Pmode, gen_rtvec (1, loc),
- unspec));
-}
-
-/* Generate GOT pointer based address with large offset. */
-static rtx
-nios2_large_got_address (rtx offset, rtx tmp)
-{
- if (!tmp)
- tmp = gen_reg_rtx (Pmode);
- emit_move_insn (tmp, offset);
- return gen_rtx_PLUS (Pmode, tmp, pic_offset_table_rtx);
-}
-
-/* Generate a GOT pointer based address. */
-static rtx
-nios2_got_address (rtx loc, int unspec)
-{
- rtx offset = nios2_unspec_offset (loc, unspec);
- crtl->uses_pic_offset_table = 1;
-
- if (nios2_large_offset_p (unspec))
- return force_reg (Pmode, nios2_large_got_address (offset, NULL_RTX));
-
- return gen_rtx_PLUS (Pmode, pic_offset_table_rtx, offset);
-}
-
-/* Generate the code to access LOC, a thread local SYMBOL_REF. The
- return value will be a valid address and move_operand (either a REG
- or a LO_SUM). */
-static rtx
-nios2_legitimize_tls_address (rtx loc)
-{
- rtx tmp, mem, tp;
- enum tls_model model = SYMBOL_REF_TLS_MODEL (loc);
-
- switch (model)
- {
- case TLS_MODEL_GLOBAL_DYNAMIC:
- tmp = gen_reg_rtx (Pmode);
- emit_move_insn (tmp, nios2_got_address (loc, UNSPEC_ADD_TLS_GD));
- return nios2_call_tls_get_addr (tmp);
-
- case TLS_MODEL_LOCAL_DYNAMIC:
- tmp = gen_reg_rtx (Pmode);
- emit_move_insn (tmp, nios2_got_address (loc, UNSPEC_ADD_TLS_LDM));
- return gen_rtx_PLUS (Pmode, nios2_call_tls_get_addr (tmp),
- nios2_unspec_offset (loc, UNSPEC_ADD_TLS_LDO));
-
- case TLS_MODEL_INITIAL_EXEC:
- tmp = gen_reg_rtx (Pmode);
- mem = gen_const_mem (Pmode, nios2_got_address (loc, UNSPEC_LOAD_TLS_IE));
- emit_move_insn (tmp, mem);
- tp = gen_rtx_REG (Pmode, TP_REGNO);
- return gen_rtx_PLUS (Pmode, tp, tmp);
-
- case TLS_MODEL_LOCAL_EXEC:
- tp = gen_rtx_REG (Pmode, TP_REGNO);
- return gen_rtx_PLUS (Pmode, tp,
- nios2_unspec_offset (loc, UNSPEC_ADD_TLS_LE));
- default:
- gcc_unreachable ();
- }
-}
-
-/* Divide Support
-
- If -O3 is used, we want to output a table lookup for
- divides between small numbers (both num and den >= 0
- and < 0x10). The overhead of this method in the worst
- case is 40 bytes in the text section (10 insns) and
- 256 bytes in the data section. Additional divides do
- not incur additional penalties in the data section.
-
- Code speed is improved for small divides by about 5x
- when using this method in the worse case (~9 cycles
- vs ~45). And in the worst case divides not within the
- table are penalized by about 10% (~5 cycles vs ~45).
- However in the typical case the penalty is not as bad
- because doing the long divide in only 45 cycles is
- quite optimistic.
-
- ??? would be nice to have some benchmarks other
- than Dhrystone to back this up.
-
- This bit of expansion is to create this instruction
- sequence as rtl.
- or $8, $4, $5
- slli $9, $4, 4
- cmpgeui $3, $8, 16
- beq $3, $0, .L3
- or $10, $9, $5
- add $12, $11, divide_table
- ldbu $2, 0($12)
- br .L1
-.L3:
- call slow_div
-.L1:
-# continue here with result in $2
-
- ??? Ideally I would like the libcall block to contain all
- of this code, but I don't know how to do that. What it
- means is that if the divide can be eliminated, it may not
- completely disappear.
-
- ??? The __divsi3_table label should ideally be moved out
- of this block and into a global. If it is placed into the
- sdata section we can save even more cycles by doing things
- gp relative. */
-void
-nios2_emit_expensive_div (rtx *operands, machine_mode mode)
-{
- rtx or_result, shift_left_result;
- rtx lookup_value;
- rtx_code_label *lab1, *lab3;
- rtx_insn *insns;
- rtx libfunc;
- rtx final_result;
- rtx_insn *tmp;
- rtx table;
-
- /* It may look a little generic, but only SImode is supported for now. */
- gcc_assert (mode == SImode);
- libfunc = optab_libfunc (sdiv_optab, SImode);
-
- lab1 = gen_label_rtx ();
- lab3 = gen_label_rtx ();
-
- or_result = expand_simple_binop (SImode, IOR,
- operands[1], operands[2],
- 0, 0, OPTAB_LIB_WIDEN);
-
- emit_cmp_and_jump_insns (or_result, GEN_INT (15), GTU, 0,
- GET_MODE (or_result), 0, lab3);
- JUMP_LABEL (get_last_insn ()) = lab3;
-
- shift_left_result = expand_simple_binop (SImode, ASHIFT,
- operands[1], GEN_INT (4),
- 0, 0, OPTAB_LIB_WIDEN);
-
- lookup_value = expand_simple_binop (SImode, IOR,
- shift_left_result, operands[2],
- 0, 0, OPTAB_LIB_WIDEN);
- table = gen_rtx_PLUS (SImode, lookup_value,
- gen_rtx_SYMBOL_REF (SImode, "__divsi3_table"));
- convert_move (operands[0], gen_rtx_MEM (QImode, table), 1);
-
- tmp = emit_jump_insn (gen_jump (lab1));
- JUMP_LABEL (tmp) = lab1;
- emit_barrier ();
-
- emit_label (lab3);
- LABEL_NUSES (lab3) = 1;
-
- start_sequence ();
- final_result = emit_library_call_value (libfunc, NULL_RTX,
- LCT_CONST, SImode,
- operands[1], SImode,
- operands[2], SImode);
-
- insns = get_insns ();
- end_sequence ();
- emit_libcall_block (insns, operands[0], final_result,
- gen_rtx_DIV (SImode, operands[1], operands[2]));
-
- emit_label (lab1);
- LABEL_NUSES (lab1) = 1;
-}
-
-
-/* Branches and compares. */
-
-/* Return in *ALT_CODE and *ALT_OP, an alternate equivalent constant
- comparison, e.g. >= 1 into > 0. */
-static void
-nios2_alternate_compare_const (enum rtx_code code, rtx op,
- enum rtx_code *alt_code, rtx *alt_op,
- machine_mode mode)
-{
- gcc_assert (CONST_INT_P (op));
-
- HOST_WIDE_INT opval = INTVAL (op);
- enum rtx_code scode = signed_condition (code);
- bool dec_p = (scode == LT || scode == GE);
-
- if (code == EQ || code == NE)
- {
- *alt_code = code;
- *alt_op = op;
- return;
- }
-
- *alt_op = (dec_p
- ? gen_int_mode (opval - 1, mode)
- : gen_int_mode (opval + 1, mode));
-
- /* The required conversion between [>,>=] and [<,<=] is captured
- by a reverse + swap of condition codes. */
- *alt_code = reverse_condition (swap_condition (code));
-
- {
- /* Test if the incremented/decremented value crosses the over/underflow
- boundary. Supposedly, such boundary cases should already be transformed
- into always-true/false or EQ conditions, so use an assertion here. */
- unsigned HOST_WIDE_INT alt_opval = INTVAL (*alt_op);
- if (code == scode)
- alt_opval ^= (1 << (GET_MODE_BITSIZE (mode) - 1));
- alt_opval &= GET_MODE_MASK (mode);
- gcc_assert (dec_p ? alt_opval != GET_MODE_MASK (mode) : alt_opval != 0);
- }
-}
-
-/* Return true if the constant comparison is supported by nios2. */
-static bool
-nios2_valid_compare_const_p (enum rtx_code code, rtx op)
-{
- gcc_assert (CONST_INT_P (op));
- switch (code)
- {
- case EQ: case NE: case GE: case LT:
- return SMALL_INT (INTVAL (op));
- case GEU: case LTU:
- return SMALL_INT_UNSIGNED (INTVAL (op));
- default:
- return false;
- }
-}
-
-/* Checks if the FPU comparison in *CMP, *OP1, and *OP2 can be supported in
- the current configuration. Perform modifications if MODIFY_P is true.
- Returns true if FPU compare can be done. */
-
-bool
-nios2_validate_fpu_compare (machine_mode mode, rtx *cmp, rtx *op1, rtx *op2,
- bool modify_p)
-{
- bool rev_p = false;
- enum rtx_code code = GET_CODE (*cmp);
-
- if (!nios2_fpu_compare_enabled (code, mode))
- {
- code = swap_condition (code);
- if (nios2_fpu_compare_enabled (code, mode))
- rev_p = true;
- else
- return false;
- }
-
- if (modify_p)
- {
- if (rev_p)
- {
- rtx tmp = *op1;
- *op1 = *op2;
- *op2 = tmp;
- }
- *op1 = force_reg (mode, *op1);
- *op2 = force_reg (mode, *op2);
- *cmp = gen_rtx_fmt_ee (code, mode, *op1, *op2);
- }
- return true;
-}
-
-/* Checks and modifies the comparison in *CMP, *OP1, and *OP2 into valid
- nios2 supported form. Returns true if success. */
-bool
-nios2_validate_compare (machine_mode mode, rtx *cmp, rtx *op1, rtx *op2)
-{
- enum rtx_code code = GET_CODE (*cmp);
- enum rtx_code alt_code;
- rtx alt_op2;
-
- if (GET_MODE_CLASS (mode) == MODE_FLOAT)
- return nios2_validate_fpu_compare (mode, cmp, op1, op2, true);
-
- if (CONST_INT_P (*op2) && *op2 != const0_rtx)
- {
- /* Create alternate constant compare. */
- nios2_alternate_compare_const (code, *op2, &alt_code, &alt_op2, mode);
-
- /* If alterate op2 is zero(0), we can use it directly, possibly
- swapping the compare code. */
- if (alt_op2 == const0_rtx)
- {
- code = alt_code;
- *op2 = alt_op2;
- goto check_rebuild_cmp;
- }
-
- /* Check if either constant compare can be used. */
- if (nios2_valid_compare_const_p (code, *op2))
- return true;
- else if (nios2_valid_compare_const_p (alt_code, alt_op2))
- {
- code = alt_code;
- *op2 = alt_op2;
- goto rebuild_cmp;
- }
-
- /* We have to force op2 into a register now. Try to pick one
- with a lower cost. */
- if (! nios2_simple_const_p (*op2)
- && nios2_simple_const_p (alt_op2))
- {
- code = alt_code;
- *op2 = alt_op2;
- }
- *op2 = force_reg (mode, *op2);
- }
- else if (!reg_or_0_operand (*op2, mode))
- *op2 = force_reg (mode, *op2);
-
- check_rebuild_cmp:
- if (code == GT || code == GTU || code == LE || code == LEU)
- {
- rtx t = *op1; *op1 = *op2; *op2 = t;
- code = swap_condition (code);
- }
- rebuild_cmp:
- *cmp = gen_rtx_fmt_ee (code, mode, *op1, *op2);
- return true;
-}
-
-
-/* Addressing modes and constants. */
-
-/* Symbol references and other 32-bit constants are split into
- high/lo_sum pairs during the split1 pass. After that, they are not
- considered legitimate addresses.
- This function returns true if in a pre-split context where these
- constants are allowed. */
-static bool
-nios2_large_constant_allowed (void)
-{
- /* The reload_completed check is for the benefit of
- nios2_asm_output_mi_thunk and perhaps other places that try to
- emulate a post-reload pass. */
- return !(cfun->curr_properties & PROP_rtl_split_insns) && !reload_completed;
-}
-
-/* Return true if X is constant expression with a reference to an
- "ordinary" symbol; not GOT-relative, not GP-relative, not TLS. */
-static bool
-nios2_symbolic_constant_p (rtx x)
-{
- rtx base, offset;
-
- if (flag_pic)
- return false;
- if (GET_CODE (x) == LABEL_REF)
- return true;
- else if (CONSTANT_P (x))
- {
- split_const (x, &base, &offset);
- return (SYMBOL_REF_P (base)
- && !SYMBOL_REF_TLS_MODEL (base)
- && !gprel_constant_p (base)
- && !r0rel_constant_p (base)
- && SMALL_INT (INTVAL (offset)));
- }
- return false;
-}
-
-/* Return true if X is an expression of the form
- (PLUS reg large_constant). */
-static bool
-nios2_plus_large_constant_p (rtx x)
-{
- return (GET_CODE (x) == PLUS
- && REG_P (XEXP (x, 0))
- && nios2_large_constant_p (XEXP (x, 1)));
-}
-
-/* Implement TARGET_LEGITIMATE_CONSTANT_P. */
-static bool
-nios2_legitimate_constant_p (machine_mode mode ATTRIBUTE_UNUSED, rtx x)
-{
- rtx base, offset;
- split_const (x, &base, &offset);
- return GET_CODE (base) != SYMBOL_REF || !SYMBOL_REF_TLS_MODEL (base);
-}
-
-/* Implement TARGET_CANNOT_FORCE_CONST_MEM. */
-static bool
-nios2_cannot_force_const_mem (machine_mode mode ATTRIBUTE_UNUSED, rtx x)
-{
- return nios2_legitimate_constant_p (mode, x) == false;
-}
-
-/* Return true if register REGNO is a valid base register.
- STRICT_P is true if REG_OK_STRICT is in effect. */
-
-bool
-nios2_regno_ok_for_base_p (int regno, bool strict_p)
-{
- if (!HARD_REGISTER_NUM_P (regno))
- {
- if (!strict_p)
- return true;
-
- if (!reg_renumber)
- return false;
-
- regno = reg_renumber[regno];
- }
-
- /* The fake registers will be eliminated to either the stack or
- hard frame pointer, both of which are usually valid base registers.
- Reload deals with the cases where the eliminated form isn't valid. */
- return (GP_REG_P (regno)
- || regno == FRAME_POINTER_REGNUM
- || regno == ARG_POINTER_REGNUM);
-}
-
-/* Return true if OFFSET is permitted in a load/store address expression.
- Normally any 16-bit value is permitted, but on R2 if we may be emitting
- the IO forms of these instructions we must restrict the offset to fit
- in a 12-bit field instead. */
-
-static bool
-nios2_valid_addr_offset_p (rtx offset)
-{
- return (CONST_INT_P (offset)
- && ((TARGET_ARCH_R2 && (TARGET_BYPASS_CACHE
- || TARGET_BYPASS_CACHE_VOLATILE))
- ? SMALL_INT12 (INTVAL (offset))
- : SMALL_INT (INTVAL (offset))));
-}
-
-/* Return true if the address expression formed by BASE + OFFSET is
- valid. */
-static bool
-nios2_valid_addr_expr_p (rtx base, rtx offset, bool strict_p)
-{
- if (!strict_p && GET_CODE (base) == SUBREG)
- base = SUBREG_REG (base);
- return (REG_P (base)
- && nios2_regno_ok_for_base_p (REGNO (base), strict_p)
- && (offset == NULL_RTX
- || nios2_valid_addr_offset_p (offset)
- || (nios2_large_constant_allowed ()
- && nios2_symbolic_constant_p (offset))
- || nios2_unspec_reloc_p (offset)));
-}
-
-/* Implement TARGET_LEGITIMATE_ADDRESS_P. */
-static bool
-nios2_legitimate_address_p (machine_mode mode ATTRIBUTE_UNUSED, rtx operand,
- bool strict_p,
- code_helper = ERROR_MARK)
-{
- switch (GET_CODE (operand))
- {
- /* Direct. */
- case SYMBOL_REF:
- if (SYMBOL_REF_TLS_MODEL (operand))
- return false;
-
- /* Else, fall through. */
- case CONST:
- if (gprel_constant_p (operand) || r0rel_constant_p (operand))
- return true;
-
- /* Else, fall through. */
- case LABEL_REF:
- if (nios2_large_constant_allowed ()
- && nios2_symbolic_constant_p (operand))
- return true;
- return false;
-
- case CONST_INT:
- if (r0rel_constant_p (operand))
- return true;
- return nios2_large_constant_allowed ();
-
- case CONST_DOUBLE:
- return false;
-
- /* Register indirect. */
- case REG:
- return nios2_regno_ok_for_base_p (REGNO (operand), strict_p);
-
- /* Register indirect with displacement. */
- case PLUS:
- {
- rtx op0 = XEXP (operand, 0);
- rtx op1 = XEXP (operand, 1);
-
- if (nios2_valid_addr_expr_p (op0, op1, strict_p)
- || nios2_valid_addr_expr_p (op1, op0, strict_p))
- return true;
- }
- break;
-
- /* %lo(constant)(reg)
- This requires a 16-bit relocation and isn't valid with R2
- io-variant load/stores. */
- case LO_SUM:
- if (TARGET_ARCH_R2
- && (TARGET_BYPASS_CACHE || TARGET_BYPASS_CACHE_VOLATILE))
- return false;
- else
- {
- rtx op0 = XEXP (operand, 0);
- rtx op1 = XEXP (operand, 1);
-
- return (REG_P (op0)
- && nios2_regno_ok_for_base_p (REGNO (op0), strict_p)
- && nios2_large_constant_p (op1));
- }
-
- default:
- break;
- }
- return false;
-}
-
-/* Implement TARGET_ADDRESS_COST.
- Experimentation has shown that we get better code by penalizing the
- the (plus reg symbolic_constant) and (plus reg (const ...)) forms
- but giving (plus reg symbol_ref) address modes the same cost as those
- that don't require splitting. Also, from a theoretical point of view:
- - This is in line with the recommendation in the GCC internals
- documentation to make address forms involving multiple
- registers more expensive than single-register forms.
- - OTOH it still encourages fwprop1 to propagate constants into
- address expressions more aggressively.
- - We should discourage splitting (symbol + offset) into hi/lo pairs
- to allow CSE'ing the symbol when it's used with more than one offset,
- but not so heavily as to avoid this addressing mode at all. */
-static int
-nios2_address_cost (rtx address,
- machine_mode mode ATTRIBUTE_UNUSED,
- addr_space_t as ATTRIBUTE_UNUSED,
- bool speed ATTRIBUTE_UNUSED)
-{
- if (nios2_plus_large_constant_p (address))
- return COSTS_N_INSNS (1);
- if (nios2_large_constant_p (address))
- {
- if (GET_CODE (address) == CONST)
- return COSTS_N_INSNS (1);
- else
- return COSTS_N_INSNS (0);
- }
- return COSTS_N_INSNS (0);
-}
-
-/* Return true if X is a MEM whose address expression involves a large (32-bit)
- constant. */
-bool
-nios2_large_constant_memory_operand_p (rtx x)
-{
- rtx addr;
-
- if (GET_CODE (x) != MEM)
- return false;
- addr = XEXP (x, 0);
-
- return (nios2_large_constant_p (addr)
- || nios2_plus_large_constant_p (addr));
-}
-
-
-/* Return true if X is something that needs to be split into a
- high/lo_sum pair. */
-bool
-nios2_large_constant_p (rtx x)
-{
- return (nios2_symbolic_constant_p (x)
- || nios2_large_unspec_reloc_p (x)
- || (CONST_INT_P (x) && !SMALL_INT (INTVAL (x))));
-}
-
-/* Given an RTX X that satisfies nios2_large_constant_p, split it into
- high and lo_sum parts using TEMP as a scratch register. Emit the high
- instruction and return the lo_sum expression.
- Also handle special cases involving constant integers. */
-rtx
-nios2_split_large_constant (rtx x, rtx temp)
-{
- if (CONST_INT_P (x))
- {
- HOST_WIDE_INT val = INTVAL (x);
- if (SMALL_INT (val))
- return x;
- else if (SMALL_INT_UNSIGNED (val) || UPPER16_INT (val))
- {
- emit_move_insn (temp, x);
- return temp;
- }
- else
- {
- HOST_WIDE_INT high = (val + 0x8000) & ~0xffff;
- HOST_WIDE_INT low = val - high;
- emit_move_insn (temp, gen_int_mode (high, Pmode));
- return gen_rtx_PLUS (Pmode, temp, gen_int_mode (low, Pmode));
- }
- }
-
- emit_insn (gen_rtx_SET (temp, gen_rtx_HIGH (Pmode, copy_rtx (x))));
- return gen_rtx_LO_SUM (Pmode, temp, copy_rtx (x));
-}
-
-/* Split an RTX of the form
- (plus op0 op1)
- where op1 is a large constant into
- (set temp (high op1))
- (set temp (plus op0 temp))
- (lo_sum temp op1)
- returning the lo_sum expression as the value. */
-static rtx
-nios2_split_plus_large_constant (rtx op0, rtx op1)
-{
- rtx temp = gen_reg_rtx (Pmode);
- op0 = force_reg (Pmode, op0);
-
- emit_insn (gen_rtx_SET (temp, gen_rtx_HIGH (Pmode, copy_rtx (op1))));
- emit_insn (gen_rtx_SET (temp, gen_rtx_PLUS (Pmode, op0, temp)));
- return gen_rtx_LO_SUM (Pmode, temp, copy_rtx (op1));
-}
-
-/* Given a MEM OP with an address that includes a splittable symbol or
- other large constant, emit some instructions to do the split and
- return a new MEM. */
-rtx
-nios2_split_large_constant_memory_operand (rtx op)
-{
- rtx addr = XEXP (op, 0);
-
- if (nios2_large_constant_p (addr))
- addr = nios2_split_large_constant (addr, gen_reg_rtx (Pmode));
- else if (nios2_plus_large_constant_p (addr))
- addr = nios2_split_plus_large_constant (XEXP (addr, 0), XEXP (addr, 1));
- else
- gcc_unreachable ();
- return replace_equiv_address (op, addr, false);
-}
-
-/* Return true if SECTION is a small section name. */
-static bool
-nios2_small_section_name_p (const char *section)
-{
- return (strcmp (section, ".sbss") == 0
- || startswith (section, ".sbss.")
- || strcmp (section, ".sdata") == 0
- || startswith (section, ".sdata.")
- || (nios2_gprel_sec
- && regexec (&nios2_gprel_sec_regex, section, 0, NULL, 0) == 0));
-}
-
-/* Return true if SECTION is a r0-relative section name. */
-static bool
-nios2_r0rel_section_name_p (const char *section)
-{
- return (nios2_r0rel_sec
- && regexec (&nios2_r0rel_sec_regex, section, 0, NULL, 0) == 0);
-}
-
-/* Return true if EXP should be placed in the small data section. */
-static bool
-nios2_in_small_data_p (const_tree exp)
-{
- /* We want to merge strings, so we never consider them small data. */
- if (TREE_CODE (exp) == STRING_CST)
- return false;
-
- if (TREE_CODE (exp) == VAR_DECL)
- {
- if (DECL_SECTION_NAME (exp))
- {
- const char *section = DECL_SECTION_NAME (exp);
- if (nios2_small_section_name_p (section))
- return true;
- }
- else if (flexible_array_type_p (TREE_TYPE (exp))
- && (!TREE_PUBLIC (exp) || DECL_EXTERNAL (exp)))
- {
- /* We really should not consider any objects of any flexibly-sized
- type to be small data, but pre-GCC 10 did not test
- for this and just fell through to the next case. Thus older
- code compiled with -mgpopt=global could contain GP-relative
- accesses to objects defined in this compilation unit with
- external linkage. We retain the possible small-data treatment
- of such definitions for backward ABI compatibility, but
- no longer generate GP-relative accesses for external
- references (so that the ABI could be changed in the future
- with less potential impact), or objects with internal
- linkage. */
- return false;
- }
- else
- {
- HOST_WIDE_INT size = int_size_in_bytes (TREE_TYPE (exp));
-
- /* If this is an incomplete type with size 0, then we can't put it
- in sdata because it might be too big when completed. */
- if (size > 0
- && (unsigned HOST_WIDE_INT) size <= nios2_section_threshold)
- return true;
- }
- }
-
- return false;
-}
-
-/* Return true if symbol is in small data section. */
-
-static bool
-nios2_symbol_ref_in_small_data_p (rtx sym)
-{
- tree decl;
-
- gcc_assert (GET_CODE (sym) == SYMBOL_REF);
- decl = SYMBOL_REF_DECL (sym);
-
- /* TLS variables are not accessed through the GP. */
- if (SYMBOL_REF_TLS_MODEL (sym) != 0)
- return false;
-
- /* On Nios II R2, there is no GP-relative relocation that can be
- used with "io" instructions. So, if we are implicitly generating
- those instructions, we cannot emit GP-relative accesses. */
- if (TARGET_ARCH_R2
- && (TARGET_BYPASS_CACHE || TARGET_BYPASS_CACHE_VOLATILE))
- return false;
-
- /* If the user has explicitly placed the symbol in a small data section
- via an attribute, generate gp-relative addressing even if the symbol
- is external, weak, or larger than we'd automatically put in the
- small data section. OTOH, if the symbol is located in some
- non-small-data section, we can't use gp-relative accesses on it
- unless the user has requested gpopt_data or gpopt_all. */
-
- switch (nios2_gpopt_option)
- {
- case gpopt_none:
- /* Don't generate a gp-relative addressing mode if that's been
- disabled. */
- return false;
-
- case gpopt_local:
- /* Use GP-relative addressing for small data symbols that are
- not external or weak or uninitialized common, plus any symbols
- that have explicitly been placed in a small data section. */
- if (decl && DECL_SECTION_NAME (decl))
- return nios2_small_section_name_p (DECL_SECTION_NAME (decl));
- return (SYMBOL_REF_SMALL_P (sym)
- && !SYMBOL_REF_EXTERNAL_P (sym)
- && !(decl && DECL_WEAK (decl))
- && !(decl && DECL_COMMON (decl)
- && (DECL_INITIAL (decl) == NULL
- || (!in_lto_p
- && DECL_INITIAL (decl) == error_mark_node))));
-
- case gpopt_global:
- /* Use GP-relative addressing for small data symbols, even if
- they are external or weak. Note that SYMBOL_REF_SMALL_P
- is also true of symbols that have explicitly been placed
- in a small data section. */
- return SYMBOL_REF_SMALL_P (sym);
-
- case gpopt_data:
- /* Use GP-relative addressing for all data symbols regardless
- of the object size, but not for code symbols. This option
- is equivalent to the user asserting that the entire data
- section is accessible from the GP. */
- return !SYMBOL_REF_FUNCTION_P (sym);
-
- case gpopt_all:
- /* Use GP-relative addressing for everything, including code.
- Effectively, the user has asserted that the entire program
- fits within the 64K range of the GP offset. */
- return true;
-
- default:
- /* We shouldn't get here. */
- return false;
- }
-}
-
-/* Likewise for r0-relative addressing. */
-static bool
-nios2_symbol_ref_in_r0rel_data_p (rtx sym)
-{
- tree decl;
-
- gcc_assert (GET_CODE (sym) == SYMBOL_REF);
- decl = SYMBOL_REF_DECL (sym);
-
- /* TLS variables are not accessed through r0. */
- if (SYMBOL_REF_TLS_MODEL (sym) != 0)
- return false;
-
- /* On Nios II R2, there is no r0-relative relocation that can be
- used with "io" instructions. So, if we are implicitly generating
- those instructions, we cannot emit r0-relative accesses. */
- if (TARGET_ARCH_R2
- && (TARGET_BYPASS_CACHE || TARGET_BYPASS_CACHE_VOLATILE))
- return false;
-
- /* If the user has explicitly placed the symbol in a r0rel section
- via an attribute, generate r0-relative addressing. */
- if (decl && DECL_SECTION_NAME (decl))
- return nios2_r0rel_section_name_p (DECL_SECTION_NAME (decl));
- return false;
-}
-
-/* Implement TARGET_SECTION_TYPE_FLAGS. */
-
-static unsigned int
-nios2_section_type_flags (tree decl, const char *name, int reloc)
-{
- unsigned int flags;
-
- flags = default_section_type_flags (decl, name, reloc);
-
- if (nios2_small_section_name_p (name))
- flags |= SECTION_SMALL;
-
- return flags;
-}
-
-/* Return true if SYMBOL_REF X binds locally. */
-
-static bool
-nios2_symbol_binds_local_p (const_rtx x)
-{
- return (SYMBOL_REF_DECL (x)
- ? targetm.binds_local_p (SYMBOL_REF_DECL (x))
- : SYMBOL_REF_LOCAL_P (x));
-}
-
-/* Position independent code related. */
-
-/* Emit code to load the PIC register. */
-static void
-nios2_load_pic_register (void)
-{
- rtx tmp = gen_rtx_REG (Pmode, TEMP_REG_NUM);
-
- emit_insn (gen_load_got_register (pic_offset_table_rtx, tmp));
- emit_insn (gen_add3_insn (pic_offset_table_rtx, pic_offset_table_rtx, tmp));
-}
-
-/* Generate a PIC address as a MEM rtx. */
-static rtx
-nios2_load_pic_address (rtx sym, int unspec, rtx tmp)
-{
- if (flag_pic == 2
- && GET_CODE (sym) == SYMBOL_REF
- && nios2_symbol_binds_local_p (sym))
- /* Under -fPIC, generate a GOTOFF address for local symbols. */
- {
- rtx offset = nios2_unspec_offset (sym, UNSPEC_PIC_GOTOFF_SYM);
- crtl->uses_pic_offset_table = 1;
- return nios2_large_got_address (offset, tmp);
- }
-
- if (unspec == UNSPEC_PIC_CALL_SYM)
- return gen_rtx_MEM (Pmode, nios2_got_address (sym, unspec));
- else
- return gen_const_mem (Pmode, nios2_got_address (sym, unspec));
-}
-
-/* Nonzero if the constant value X is a legitimate general operand
- when generating PIC code. It is given that flag_pic is on and
- that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
-bool
-nios2_legitimate_pic_operand_p (rtx x)
-{
- if (nios2_large_unspec_reloc_p (x))
- return true;
-
- return ! (GET_CODE (x) == SYMBOL_REF
- || GET_CODE (x) == LABEL_REF || GET_CODE (x) == CONST);
-}
-
-/* Return TRUE if X is a thread-local symbol. */
-static bool
-nios2_tls_symbol_p (rtx x)
-{
- return (targetm.have_tls && GET_CODE (x) == SYMBOL_REF
- && SYMBOL_REF_TLS_MODEL (x) != 0);
-}
-
-/* Legitimize addresses that are CONSTANT_P expressions. */
-static rtx
-nios2_legitimize_constant_address (rtx addr)
-{
- rtx base, offset;
- split_const (addr, &base, &offset);
-
- if (nios2_tls_symbol_p (base))
- base = nios2_legitimize_tls_address (base);
- else if (flag_pic)
- base = nios2_load_pic_address (base, UNSPEC_PIC_SYM, NULL_RTX);
- else if (!nios2_large_constant_allowed ()
- && nios2_symbolic_constant_p (addr))
- return nios2_split_large_constant (addr, gen_reg_rtx (Pmode));
- else if (CONST_INT_P (addr))
- {
- HOST_WIDE_INT val = INTVAL (addr);
- if (SMALL_INT (val))
- /* Use r0-relative addressing. */
- return addr;
- else if (!nios2_large_constant_allowed ())
- /* Split into high/lo pair. */
- return nios2_split_large_constant (addr, gen_reg_rtx (Pmode));
- }
- else
- return addr;
-
- if (offset != const0_rtx)
- {
- gcc_assert (can_create_pseudo_p ());
- return gen_rtx_PLUS (Pmode, force_reg (Pmode, base),
- (CONST_INT_P (offset)
- ? (SMALL_INT (INTVAL (offset))
- ? offset : force_reg (Pmode, offset))
- : offset));
- }
- return base;
-}
-
-/* Implement TARGET_LEGITIMIZE_ADDRESS. */
-static rtx
-nios2_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
- machine_mode mode ATTRIBUTE_UNUSED)
-{
- rtx op0, op1;
-
- if (CONSTANT_P (x))
- return nios2_legitimize_constant_address (x);
-
- /* Remaining cases all involve something + a constant. */
- if (GET_CODE (x) != PLUS)
- return x;
-
- op0 = XEXP (x, 0);
- op1 = XEXP (x, 1);
-
- /* Target-independent code turns (exp + constant) into plain
- register indirect. Although subsequent optimization passes will
- eventually sort that out, ivopts uses the unoptimized form for
- computing its cost model, so we get better results by generating
- the correct form from the start. */
- if (nios2_valid_addr_offset_p (op1))
- return gen_rtx_PLUS (Pmode, force_reg (Pmode, op0), copy_rtx (op1));
-
- /* We may need to split symbolic constants now. */
- else if (nios2_symbolic_constant_p (op1))
- {
- if (nios2_large_constant_allowed ())
- return gen_rtx_PLUS (Pmode, force_reg (Pmode, op0), copy_rtx (op1));
- else
- return nios2_split_plus_large_constant (op0, op1);
- }
-
- /* For the TLS LE (Local Exec) model, the compiler may try to
- combine constant offsets with unspec relocs, creating address RTXs
- looking like this:
- (plus:SI (reg:SI 23 r23)
- (const:SI
- (plus:SI
- (unspec:SI [(symbol_ref:SI ("var"))] UNSPEC_ADD_TLS_LE)
- (const_int 48 [0x30]))))
-
- This usually happens when 'var' is a thread-local struct variable,
- and access of a field in var causes the addend.
-
- We typically want this combining, so transform the above into this
- form, which is allowed:
- (plus:SI (reg:SI 23 r23)
- (const:SI
- (unspec:SI
- [(const:SI
- (plus:SI (symbol_ref:SI ("var"))
- (const_int 48 [0x30])))] UNSPEC_ADD_TLS_LE)))
-
- Which will be output as '%tls_le(var+48)(r23)' in assembly. */
- else if (GET_CODE (op1) == CONST)
- {
- rtx unspec, offset;
- split_const (op1, &unspec, &offset);
- if (GET_CODE (unspec) == UNSPEC
- && !nios2_large_offset_p (XINT (unspec, 1))
- && offset != const0_rtx)
- {
- rtx reg = force_reg (Pmode, op0);
- unspec = copy_rtx (unspec);
- XVECEXP (unspec, 0, 0)
- = plus_constant (Pmode, XVECEXP (unspec, 0, 0), INTVAL (offset));
- return gen_rtx_PLUS (Pmode, reg, gen_rtx_CONST (Pmode, unspec));
- }
- }
-
- return x;
-}
-
-static rtx
-nios2_delegitimize_address (rtx x)
-{
- x = delegitimize_mem_from_attrs (x);
-
- if (GET_CODE (x) == CONST && GET_CODE (XEXP (x, 0)) == UNSPEC)
- {
- switch (XINT (XEXP (x, 0), 1))
- {
- case UNSPEC_PIC_SYM:
- case UNSPEC_PIC_CALL_SYM:
- case UNSPEC_PIC_GOTOFF_SYM:
- case UNSPEC_ADD_TLS_GD:
- case UNSPEC_ADD_TLS_LDM:
- case UNSPEC_LOAD_TLS_IE:
- case UNSPEC_ADD_TLS_LE:
- x = XVECEXP (XEXP (x, 0), 0, 0);
- gcc_assert (CONSTANT_P (x));
- break;
- }
- }
- return x;
-}
-
-/* Main expander function for RTL moves. */
-bool
-nios2_emit_move_sequence (rtx *operands, machine_mode mode)
-{
- rtx to = operands[0];
- rtx from = operands[1];
-
- if (!register_operand (to, mode) && !reg_or_0_operand (from, mode))
- {
- gcc_assert (can_create_pseudo_p ());
- from = copy_to_mode_reg (mode, from);
- }
-
- if (CONSTANT_P (from))
- {
- if (CONST_INT_P (from))
- {
- if (!SMALL_INT (INTVAL (from))
- && !SMALL_INT_UNSIGNED (INTVAL (from))
- && !UPPER16_INT (INTVAL (from)))
- {
- HOST_WIDE_INT high = (INTVAL (from) + 0x8000) & ~0xffff;
- HOST_WIDE_INT low = INTVAL (from) & 0xffff;
- emit_move_insn (to, gen_int_mode (high, SImode));
- emit_insn (gen_add2_insn (to, gen_int_mode (low, HImode)));
- set_unique_reg_note (get_last_insn (), REG_EQUAL,
- copy_rtx (from));
- return true;
- }
- }
- else if (gprel_constant_p (from) || r0rel_constant_p (from))
- /* Handled directly by movsi_internal as gp + offset
- or r0 + offset. */
- ;
- else if (nios2_large_constant_p (from))
- /* This case covers either a regular symbol reference or an UNSPEC
- representing a 32-bit offset. We split the former
- only conditionally and the latter always. */
- {
- if (!nios2_large_constant_allowed ()
- || nios2_large_unspec_reloc_p (from))
- {
- rtx lo = nios2_split_large_constant (from, to);
- emit_insn (gen_rtx_SET (to, lo));
- set_unique_reg_note (get_last_insn (), REG_EQUAL,
- copy_rtx (operands[1]));
- return true;
- }
- }
- else
- /* This is a TLS or PIC symbol. */
- {
- from = nios2_legitimize_constant_address (from);
- if (CONSTANT_P (from))
- {
- emit_insn (gen_rtx_SET (to,
- gen_rtx_HIGH (Pmode, copy_rtx (from))));
- emit_insn (gen_rtx_SET (to, gen_rtx_LO_SUM (Pmode, to, from)));
- set_unique_reg_note (get_last_insn (), REG_EQUAL,
- copy_rtx (operands[1]));
- return true;
- }
- }
- }
-
- operands[0] = to;
- operands[1] = from;
- return false;
-}
-
-/* The function with address *ADDR is being called. If the address
- needs to be loaded from the GOT, emit the instruction to do so and
- update *ADDR to point to the rtx for the loaded value.
- If REG != NULL_RTX, it is used as the target/scratch register in the
- GOT address calculation. */
-void
-nios2_adjust_call_address (rtx *call_op, rtx reg)
-{
- if (MEM_P (*call_op))
- call_op = &XEXP (*call_op, 0);
-
- rtx addr = *call_op;
- if (flag_pic && CONSTANT_P (addr))
- {
- rtx tmp = reg ? reg : NULL_RTX;
- if (!reg)
- reg = gen_reg_rtx (Pmode);
- addr = nios2_load_pic_address (addr, UNSPEC_PIC_CALL_SYM, tmp);
- emit_insn (gen_rtx_SET (reg, addr));
- *call_op = reg;
- }
-}
-
-
-/* Output assembly language related definitions. */
-
-/* Implement TARGET_PRINT_OPERAND_PUNCT_VALID_P. */
-static bool
-nios2_print_operand_punct_valid_p (unsigned char code)
-{
- return (code == '.' || code == '!');
-}
-
-
-/* Print the operand OP to file stream FILE modified by LETTER.
- LETTER can be one of:
-
- i: print i/hi/ui suffixes (used for mov instruction variants),
- when OP is the appropriate immediate operand.
-
- u: like 'i', except without "ui" suffix case (used for cmpgeu/cmpltu)
-
- o: print "io" if OP needs volatile access (due to TARGET_BYPASS_CACHE
- or TARGET_BYPASS_CACHE_VOLATILE).
-
- x: print i/hi/ci/chi suffixes for the and instruction,
- when OP is the appropriate immediate operand.
-
- z: prints the third register immediate operand in assembly
- instructions. Outputs const0_rtx as the 'zero' register
- instead of '0'.
-
- y: same as 'z', but for specifically for logical instructions,
- where the processing for immediates are slightly different.
-
- H: for %hiadj
- L: for %lo
- D: for the upper 32-bits of a 64-bit double value
- R: prints reverse condition.
- A: prints (reg) operand for ld[s]ex and st[s]ex.
-
- .: print .n suffix for 16-bit instructions.
- !: print r.n suffix for 16-bit instructions. Used for jmpr.n.
-*/
-static void
-nios2_print_operand (FILE *file, rtx op, int letter)
-{
-
- /* First take care of the format letters that just insert a string
- into the output stream. */
- switch (letter)
- {
- case '.':
- if (current_output_insn && get_attr_length (current_output_insn) == 2)
- fprintf (file, ".n");
- return;
-
- case '!':
- if (current_output_insn && get_attr_length (current_output_insn) == 2)
- fprintf (file, "r.n");
- return;
-
- case 'x':
- if (CONST_INT_P (op))
- {
- HOST_WIDE_INT val = INTVAL (op);
- HOST_WIDE_INT low = val & 0xffff;
- HOST_WIDE_INT high = (val >> 16) & 0xffff;
-
- if (val != 0)
- {
- if (high != 0)
- {
- if (low != 0)
- {
- gcc_assert (TARGET_ARCH_R2);
- if (high == 0xffff)
- fprintf (file, "c");
- else if (low == 0xffff)
- fprintf (file, "ch");
- else
- gcc_unreachable ();
- }
- else
- fprintf (file, "h");
- }
- fprintf (file, "i");
- }
- }
- return;
-
- case 'u':
- case 'i':
- if (CONST_INT_P (op))
- {
- HOST_WIDE_INT val = INTVAL (op);
- HOST_WIDE_INT low = val & 0xffff;
- HOST_WIDE_INT high = (val >> 16) & 0xffff;
- if (val != 0)
- {
- if (low == 0 && high != 0)
- fprintf (file, "h");
- else if (high == 0 && (low & 0x8000) != 0 && letter != 'u')
- fprintf (file, "u");
- }
- }
- if (CONSTANT_P (op) && op != const0_rtx)
- fprintf (file, "i");
- return;
-
- case 'o':
- if (GET_CODE (op) == MEM
- && ((MEM_VOLATILE_P (op) && TARGET_BYPASS_CACHE_VOLATILE)
- || TARGET_BYPASS_CACHE))
- {
- gcc_assert (current_output_insn
- && get_attr_length (current_output_insn) == 4);
- fprintf (file, "io");
- }
- return;
-
- default:
- break;
- }
-
- /* Handle comparison operator names. */
- if (comparison_operator (op, VOIDmode))
- {
- enum rtx_code cond = GET_CODE (op);
- if (letter == 0)
- {
- fprintf (file, "%s", GET_RTX_NAME (cond));
- return;
- }
- if (letter == 'R')
- {
- fprintf (file, "%s", GET_RTX_NAME (reverse_condition (cond)));
- return;
- }
- }
-
- /* Now handle the cases where we actually need to format an operand. */
- switch (GET_CODE (op))
- {
- case REG:
- if (letter == 0 || letter == 'z' || letter == 'y')
- {
- fprintf (file, "%s", reg_names[REGNO (op)]);
- return;
- }
- else if (letter == 'D')
- {
- fprintf (file, "%s", reg_names[REGNO (op)+1]);
- return;
- }
- break;
-
- case CONST_INT:
- {
- rtx int_rtx = op;
- HOST_WIDE_INT val = INTVAL (int_rtx);
- HOST_WIDE_INT low = val & 0xffff;
- HOST_WIDE_INT high = (val >> 16) & 0xffff;
-
- if (letter == 'y')
- {
- if (val == 0)
- fprintf (file, "zero");
- else
- {
- if (high != 0)
- {
- if (low != 0)
- {
- gcc_assert (TARGET_ARCH_R2);
- if (high == 0xffff)
- /* andci. */
- int_rtx = gen_int_mode (low, SImode);
- else if (low == 0xffff)
- /* andchi. */
- int_rtx = gen_int_mode (high, SImode);
- else
- gcc_unreachable ();
- }
- else
- /* andhi. */
- int_rtx = gen_int_mode (high, SImode);
- }
- else
- /* andi. */
- int_rtx = gen_int_mode (low, SImode);
- output_addr_const (file, int_rtx);
- }
- return;
- }
- else if (letter == 'z')
- {
- if (val == 0)
- fprintf (file, "zero");
- else
- {
- if (low == 0 && high != 0)
- int_rtx = gen_int_mode (high, SImode);
- else if (low != 0)
- {
- gcc_assert (high == 0 || high == 0xffff);
- int_rtx = gen_int_mode (low, high == 0 ? SImode : HImode);
- }
- else
- gcc_unreachable ();
- output_addr_const (file, int_rtx);
- }
- return;
- }
- }
-
- /* Else, fall through. */
-
- case CONST:
- case LABEL_REF:
- case SYMBOL_REF:
- case CONST_DOUBLE:
- if (letter == 0 || letter == 'z')
- {
- output_addr_const (file, op);
- return;
- }
- else if (letter == 'H' || letter == 'L')
- {
- fprintf (file, "%%");
- if (GET_CODE (op) == CONST
- && GET_CODE (XEXP (op, 0)) == UNSPEC)
- {
- rtx unspec = XEXP (op, 0);
- int unspec_reloc = XINT (unspec, 1);
- gcc_assert (nios2_large_offset_p (unspec_reloc));
- fprintf (file, "%s_", nios2_unspec_reloc_name (unspec_reloc));
- op = XVECEXP (unspec, 0, 0);
- }
- fprintf (file, letter == 'H' ? "hiadj(" : "lo(");
- output_addr_const (file, op);
- fprintf (file, ")");
- return;
- }
- break;
-
- case SUBREG:
- case MEM:
- if (letter == 'A')
- {
- /* Address of '(reg)' form, with no index. */
- fprintf (file, "(%s)", reg_names[REGNO (XEXP (op, 0))]);
- return;
- }
- if (letter == 0)
- {
- output_address (VOIDmode, op);
- return;
- }
- break;
-
- case CODE_LABEL:
- if (letter == 0)
- {
- output_addr_const (file, op);
- return;
- }
- break;
-
- default:
- break;
- }
-
- debug_rtx (op);
- output_operand_lossage ("Unsupported operand for code '%c'", letter);
- gcc_unreachable ();
-}
-
-/* Return true if this is a GP-relative accessible reference. */
-bool
-gprel_constant_p (rtx op)
-{
- if (GET_CODE (op) == SYMBOL_REF
- && nios2_symbol_ref_in_small_data_p (op))
- return true;
- else if (GET_CODE (op) == CONST
- && GET_CODE (XEXP (op, 0)) == PLUS)
- return gprel_constant_p (XEXP (XEXP (op, 0), 0));
-
- return false;
-}
-
-/* Likewise if this is a zero-relative accessible reference. */
-bool
-r0rel_constant_p (rtx op)
-{
- if (GET_CODE (op) == SYMBOL_REF
- && nios2_symbol_ref_in_r0rel_data_p (op))
- return true;
- else if (GET_CODE (op) == CONST
- && GET_CODE (XEXP (op, 0)) == PLUS)
- return r0rel_constant_p (XEXP (XEXP (op, 0), 0));
- else if (GET_CODE (op) == CONST_INT
- && SMALL_INT (INTVAL (op)))
- return true;
-
- return false;
-}
-
-/* Return the name string for a supported unspec reloc offset. */
-static const char *
-nios2_unspec_reloc_name (int unspec)
-{
- switch (unspec)
- {
- case UNSPEC_PIC_SYM:
- return "got";
- case UNSPEC_PIC_CALL_SYM:
- return "call";
- case UNSPEC_PIC_GOTOFF_SYM:
- return "gotoff";
- case UNSPEC_LOAD_TLS_IE:
- return "tls_ie";
- case UNSPEC_ADD_TLS_LE:
- return "tls_le";
- case UNSPEC_ADD_TLS_GD:
- return "tls_gd";
- case UNSPEC_ADD_TLS_LDM:
- return "tls_ldm";
- case UNSPEC_ADD_TLS_LDO:
- return "tls_ldo";
- default:
- return NULL;
- }
-}
-
-/* Implement TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA. */
-static bool
-nios2_output_addr_const_extra (FILE *file, rtx op)
-{
- const char *name;
- gcc_assert (GET_CODE (op) == UNSPEC);
-
- /* Support for printing out const unspec relocations. */
- name = nios2_unspec_reloc_name (XINT (op, 1));
- if (name)
- {
- fprintf (file, "%%%s(", name);
- output_addr_const (file, XVECEXP (op, 0, 0));
- fprintf (file, ")");
- return true;
- }
- return false;
-}
-
-/* Implement TARGET_PRINT_OPERAND_ADDRESS. */
-static void
-nios2_print_operand_address (FILE *file, machine_mode mode, rtx op)
-{
- switch (GET_CODE (op))
- {
- case CONST:
- case CONST_INT:
- case LABEL_REF:
- case CONST_DOUBLE:
- case SYMBOL_REF:
- if (gprel_constant_p (op))
- {
- fprintf (file, "%%gprel(");
- output_addr_const (file, op);
- fprintf (file, ")(%s)", reg_names[GP_REGNO]);
- return;
- }
- else if (r0rel_constant_p (op))
- {
- if (CONST_INT_P (op))
- {
- output_addr_const (file, op);
- fprintf (file, "(r0)");
- return;
- }
- else
- {
- fprintf (file, "%%lo(");
- output_addr_const (file, op);
- fprintf (file, ")(r0)");
- return;
- }
- }
- break;
-
- case PLUS:
- {
- rtx op0 = XEXP (op, 0);
- rtx op1 = XEXP (op, 1);
-
- if (REG_P (op0) && CONSTANT_P (op1))
- {
- output_addr_const (file, op1);
- fprintf (file, "(%s)", reg_names[REGNO (op0)]);
- return;
- }
- else if (REG_P (op1) && CONSTANT_P (op0))
- {
- output_addr_const (file, op0);
- fprintf (file, "(%s)", reg_names[REGNO (op1)]);
- return;
- }
- }
- break;
-
- case LO_SUM:
- {
- rtx op0 = XEXP (op, 0);
- rtx op1 = XEXP (op, 1);
-
- if (REG_P (op0) && CONSTANT_P (op1))
- {
- nios2_print_operand (file, op1, 'L');
- fprintf (file, "(%s)", reg_names[REGNO (op0)]);
- return;
- }
- }
- break;
-
- case REG:
- fprintf (file, "0(%s)", reg_names[REGNO (op)]);
- return;
-
- case MEM:
- {
- rtx base = XEXP (op, 0);
- nios2_print_operand_address (file, mode, base);
- return;
- }
- default:
- break;
- }
-
- fprintf (stderr, "Missing way to print address\n");
- debug_rtx (op);
- gcc_unreachable ();
-}
-
-/* Implement TARGET_ASM_OUTPUT_DWARF_DTPREL. */
-static void
-nios2_output_dwarf_dtprel (FILE *file, int size, rtx x)
-{
- gcc_assert (size == 4);
- fprintf (file, "\t.4byte\t%%tls_ldo(");
- output_addr_const (file, x);
- fprintf (file, ")");
-}
-
-/* Implemet TARGET_ASM_FILE_END. */
-
-static void
-nios2_asm_file_end (void)
-{
- /* The Nios II Linux stack is mapped non-executable by default, so add a
- .note.GNU-stack section for switching to executable stacks only when
- trampolines are generated. */
- if (TARGET_LINUX_ABI && trampolines_created)
- file_end_indicate_exec_stack ();
-}
-
-/* Implement TARGET_ASM_FUNCTION_PROLOGUE. */
-static void
-nios2_asm_function_prologue (FILE *file)
-{
- if (flag_verbose_asm || flag_debug_asm)
- {
- nios2_compute_frame_layout ();
- nios2_dump_frame_layout (file);
- }
-}
-
-/* Emit assembly of custom FPU instructions. */
-const char *
-nios2_fpu_insn_asm (enum n2fpu_code code)
-{
- static char buf[256];
- const char *op1, *op2, *op3;
- int ln = 256, n = 0;
-
- int N = N2FPU_N (code);
- int num_operands = N2FPU (code).num_operands;
- const char *insn_name = N2FPU_NAME (code);
- tree ftype = nios2_ftype (N2FPU_FTCODE (code));
- machine_mode dst_mode = TYPE_MODE (TREE_TYPE (ftype));
- machine_mode src_mode = TYPE_MODE (TREE_VALUE (TYPE_ARG_TYPES (ftype)));
-
- /* Prepare X register for DF input operands. */
- if (GET_MODE_SIZE (src_mode) == 8 && num_operands == 3)
- n = snprintf (buf, ln, "custom\t%d, zero, %%1, %%D1 # fwrx %%1\n\t",
- N2FPU_N (n2fpu_fwrx));
-
- if (src_mode == SFmode)
- {
- if (dst_mode == VOIDmode)
- {
- /* The fwry case. */
- op1 = op3 = "zero";
- op2 = "%0";
- num_operands -= 1;
- }
- else
- {
- op1 = (dst_mode == DFmode ? "%D0" : "%0");
- op2 = "%1";
- op3 = (num_operands == 2 ? "zero" : "%2");
- }
- }
- else if (src_mode == DFmode)
- {
- if (dst_mode == VOIDmode)
- {
- /* The fwrx case. */
- op1 = "zero";
- op2 = "%0";
- op3 = "%D0";
- num_operands -= 1;
- }
- else
- {
- op1 = (dst_mode == DFmode ? "%D0" : "%0");
- op2 = (num_operands == 2 ? "%1" : "%2");
- op3 = (num_operands == 2 ? "%D1" : "%D2");
- }
- }
- else if (src_mode == VOIDmode)
- {
- /* frdxlo, frdxhi, frdy cases. */
- gcc_assert (dst_mode == SFmode);
- op1 = "%0";
- op2 = op3 = "zero";
- }
- else if (src_mode == SImode)
- {
- /* Conversion operators. */
- gcc_assert (num_operands == 2);
- op1 = (dst_mode == DFmode ? "%D0" : "%0");
- op2 = "%1";
- op3 = "zero";
- }
- else
- gcc_unreachable ();
-
- /* Main instruction string. */
- n += snprintf (buf + n, ln - n, "custom\t%d, %s, %s, %s # %s %%0%s%s",
- N, op1, op2, op3, insn_name,
- (num_operands >= 2 ? ", %1" : ""),
- (num_operands == 3 ? ", %2" : ""));
-
- /* Extraction of Y register for DF results. */
- if (dst_mode == DFmode)
- snprintf (buf + n, ln - n, "\n\tcustom\t%d, %%0, zero, zero # frdy %%0",
- N2FPU_N (n2fpu_frdy));
- return buf;
-}
-
-
-
-/* Function argument related. */
-
-/* Define where to put the arguments to a function. Value is zero to
- push the argument on the stack, or a hard register in which to
- store the argument.
-
- CUM is a variable of type CUMULATIVE_ARGS which gives info about
- the preceding args and about the function being called.
- ARG is a description of the argument. */
-
-static rtx
-nios2_function_arg (cumulative_args_t cum_v, const function_arg_info &arg)
-{
- CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
- rtx return_rtx = NULL_RTX;
-
- if (cum->regs_used < NUM_ARG_REGS)
- return_rtx = gen_rtx_REG (arg.mode, FIRST_ARG_REGNO + cum->regs_used);
-
- return return_rtx;
-}
-
-/* Return number of bytes, at the beginning of the argument, that must be
- put in registers. 0 is the argument is entirely in registers or entirely
- in memory. */
-
-static int
-nios2_arg_partial_bytes (cumulative_args_t cum_v, const function_arg_info &arg)
-{
- CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
- HOST_WIDE_INT param_size = arg.promoted_size_in_bytes ();
- gcc_assert (param_size >= 0);
-
- /* Convert to words (round up). */
- param_size = (UNITS_PER_WORD - 1 + param_size) / UNITS_PER_WORD;
-
- if (cum->regs_used < NUM_ARG_REGS
- && cum->regs_used + param_size > NUM_ARG_REGS)
- return (NUM_ARG_REGS - cum->regs_used) * UNITS_PER_WORD;
-
- return 0;
-}
-
-/* Update the data in CUM to advance over argument ARG. */
-
-static void
-nios2_function_arg_advance (cumulative_args_t cum_v,
- const function_arg_info &arg)
-{
- CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
- HOST_WIDE_INT param_size = arg.promoted_size_in_bytes ();
- gcc_assert (param_size >= 0);
-
- /* Convert to words (round up). */
- param_size = (UNITS_PER_WORD - 1 + param_size) / UNITS_PER_WORD;
-
- if (cum->regs_used + param_size > NUM_ARG_REGS)
- cum->regs_used = NUM_ARG_REGS;
- else
- cum->regs_used += param_size;
-}
-
-static pad_direction
-nios2_function_arg_padding (machine_mode mode, const_tree type)
-{
- /* On little-endian targets, the first byte of every stack argument
- is passed in the first byte of the stack slot. */
- if (!BYTES_BIG_ENDIAN)
- return PAD_UPWARD;
-
- /* Otherwise, integral types are padded downward: the last byte of a
- stack argument is passed in the last byte of the stack slot. */
- if (type != 0
- ? INTEGRAL_TYPE_P (type) || POINTER_TYPE_P (type)
- : GET_MODE_CLASS (mode) == MODE_INT)
- return PAD_DOWNWARD;
-
- /* Arguments smaller than a stack slot are padded downward. */
- if (mode != BLKmode)
- return (GET_MODE_BITSIZE (mode) >= PARM_BOUNDARY
- ? PAD_UPWARD : PAD_DOWNWARD);
-
- return ((int_size_in_bytes (type) >= (PARM_BOUNDARY / BITS_PER_UNIT))
- ? PAD_UPWARD : PAD_DOWNWARD);
-}
-
-pad_direction
-nios2_block_reg_padding (machine_mode mode, tree type,
- int first ATTRIBUTE_UNUSED)
-{
- return nios2_function_arg_padding (mode, type);
-}
-
-/* Emit RTL insns to initialize the variable parts of a trampoline.
- FNADDR is an RTX for the address of the function's pure code.
- CXT is an RTX for the static chain value for the function.
- On Nios II, we handle this by a library call. */
-static void
-nios2_trampoline_init (rtx m_tramp, tree fndecl, rtx cxt)
-{
- rtx fnaddr = XEXP (DECL_RTL (fndecl), 0);
- rtx ctx_reg = force_reg (Pmode, cxt);
- rtx addr = force_reg (Pmode, XEXP (m_tramp, 0));
-
- emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "__trampoline_setup"),
- LCT_NORMAL, VOIDmode, addr, Pmode, fnaddr, Pmode,
- ctx_reg, Pmode);
-}
-
-/* Implement TARGET_FUNCTION_VALUE. */
-static rtx
-nios2_function_value (const_tree ret_type, const_tree fn ATTRIBUTE_UNUSED,
- bool outgoing ATTRIBUTE_UNUSED)
-{
- return gen_rtx_REG (TYPE_MODE (ret_type), FIRST_RETVAL_REGNO);
-}
-
-/* Implement TARGET_LIBCALL_VALUE. */
-static rtx
-nios2_libcall_value (machine_mode mode, const_rtx fun ATTRIBUTE_UNUSED)
-{
- return gen_rtx_REG (mode, FIRST_RETVAL_REGNO);
-}
-
-/* Implement TARGET_FUNCTION_VALUE_REGNO_P. */
-static bool
-nios2_function_value_regno_p (const unsigned int regno)
-{
- return regno == FIRST_RETVAL_REGNO;
-}
-
-/* Implement TARGET_RETURN_IN_MEMORY. */
-static bool
-nios2_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED)
-{
- return (int_size_in_bytes (type) > (2 * UNITS_PER_WORD)
- || int_size_in_bytes (type) == -1);
-}
-
-/* TODO: It may be possible to eliminate the copyback and implement
- own va_arg type. */
-static void
-nios2_setup_incoming_varargs (cumulative_args_t cum_v,
- const function_arg_info &arg,
- int *pretend_size, int second_time)
-{
- CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
- CUMULATIVE_ARGS local_cum;
- cumulative_args_t local_cum_v = pack_cumulative_args (&local_cum);
- int regs_to_push;
- int pret_size;
-
- cfun->machine->uses_anonymous_args = 1;
- local_cum = *cum;
- if (!TYPE_NO_NAMED_ARGS_STDARG_P (TREE_TYPE (current_function_decl))
- || arg.type != NULL_TREE)
- nios2_function_arg_advance (local_cum_v, arg);
-
- regs_to_push = NUM_ARG_REGS - local_cum.regs_used;
-
- /* If we can use CDX stwm to push the arguments on the stack,
- nios2_expand_prologue will do that instead. */
- if (!TARGET_HAS_CDX && !second_time && regs_to_push > 0)
- {
- rtx ptr = virtual_incoming_args_rtx;
- rtx mem = gen_rtx_MEM (BLKmode, ptr);
- emit_insn (gen_blockage ());
- move_block_from_reg (local_cum.regs_used + FIRST_ARG_REGNO, mem,
- regs_to_push);
- emit_insn (gen_blockage ());
- }
-
- pret_size = regs_to_push * UNITS_PER_WORD;
- if (pret_size)
- *pretend_size = pret_size;
-}
-
-
-
-/* Init FPU builtins. */
-static void
-nios2_init_fpu_builtins (int start_code)
-{
- tree fndecl;
- char builtin_name[64] = "__builtin_custom_";
- unsigned int i, n = strlen ("__builtin_custom_");
-
- for (i = 0; i < ARRAY_SIZE (nios2_fpu_insn); i++)
- {
- snprintf (builtin_name + n, sizeof (builtin_name) - n,
- "%s", N2FPU_NAME (i));
- fndecl =
- add_builtin_function (builtin_name, nios2_ftype (N2FPU_FTCODE (i)),
- start_code + i, BUILT_IN_MD, NULL, NULL_TREE);
- nios2_register_builtin_fndecl (start_code + i, fndecl);
- }
-}
-
-/* Helper function for expanding FPU builtins. */
-static rtx
-nios2_expand_fpu_builtin (tree exp, unsigned int code, rtx target)
-{
- struct expand_operand ops[MAX_RECOG_OPERANDS];
- enum insn_code icode = N2FPU_ICODE (code);
- int nargs, argno, opno = 0;
- int num_operands = N2FPU (code).num_operands;
- machine_mode dst_mode = TYPE_MODE (TREE_TYPE (exp));
- bool has_target_p = (dst_mode != VOIDmode);
-
- if (N2FPU_N (code) < 0)
- fatal_error (input_location,
- "cannot call %<__builtin_custom_%s%> without specifying "
- "switch %<-mcustom-%s%>",
- N2FPU_NAME (code), N2FPU_NAME (code));
- if (has_target_p)
- create_output_operand (&ops[opno++], target, dst_mode);
- else
- /* Subtract away the count of the VOID return, mainly for fwrx/fwry. */
- num_operands -= 1;
- nargs = call_expr_nargs (exp);
- for (argno = 0; argno < nargs; argno++)
- {
- tree arg = CALL_EXPR_ARG (exp, argno);
- create_input_operand (&ops[opno++], expand_normal (arg),
- TYPE_MODE (TREE_TYPE (arg)));
- }
- if (!maybe_expand_insn (icode, num_operands, ops))
- {
- error ("invalid argument to built-in function");
- return has_target_p ? gen_reg_rtx (ops[0].mode) : const0_rtx;
- }
- return has_target_p ? ops[0].value : const0_rtx;
-}
-
-/* Nios II has custom instruction built-in functions of the forms:
- __builtin_custom_n
- __builtin_custom_nX
- __builtin_custom_nXX
- __builtin_custom_Xn
- __builtin_custom_XnX
- __builtin_custom_XnXX
-
- where each X could be either 'i' (int), 'f' (float), or 'p' (void*).
- Therefore with 0-1 return values, and 0-2 arguments, we have a
- total of (3 + 1) * (1 + 3 + 9) == 52 custom builtin functions.
-*/
-#define NUM_CUSTOM_BUILTINS ((3 + 1) * (1 + 3 + 9))
-static char custom_builtin_name[NUM_CUSTOM_BUILTINS][5];
-
-static void
-nios2_init_custom_builtins (int start_code)
-{
- tree builtin_ftype, ret_type, fndecl;
- char builtin_name[32] = "__builtin_custom_";
- int n = strlen ("__builtin_custom_");
- int builtin_code = 0;
- int lhs, rhs1, rhs2;
-
- struct { tree type; const char *c; } op[4];
- /* z */ op[0].c = ""; op[0].type = NULL_TREE;
- /* f */ op[1].c = "f"; op[1].type = float_type_node;
- /* i */ op[2].c = "i"; op[2].type = integer_type_node;
- /* p */ op[3].c = "p"; op[3].type = ptr_type_node;
-
- /* We enumerate through the possible operand types to create all the
- __builtin_custom_XnXX function tree types. Note that these may slightly
- overlap with the function types created for other fixed builtins. */
-
- for (lhs = 0; lhs < 4; lhs++)
- for (rhs1 = 0; rhs1 < 4; rhs1++)
- for (rhs2 = 0; rhs2 < 4; rhs2++)
- {
- if (rhs1 == 0 && rhs2 != 0)
- continue;
- ret_type = (op[lhs].type ? op[lhs].type : void_type_node);
- builtin_ftype
- = build_function_type_list (ret_type, integer_type_node,
- op[rhs1].type, op[rhs2].type,
- NULL_TREE);
- /* Save copy of parameter string into custom_builtin_name[]. */
- snprintf (custom_builtin_name[builtin_code], 5, "%sn%s%s",
- op[lhs].c, op[rhs1].c, op[rhs2].c);
- strncpy (builtin_name + n, custom_builtin_name[builtin_code], 5);
- fndecl =
- add_builtin_function (builtin_name, builtin_ftype,
- start_code + builtin_code,
- BUILT_IN_MD, NULL, NULL_TREE);
- nios2_register_builtin_fndecl (start_code + builtin_code, fndecl);
- builtin_code += 1;
- }
-}
-
-/* Helper function for expanding custom builtins. */
-static rtx
-nios2_expand_custom_builtin (tree exp, unsigned int index, rtx target)
-{
- bool has_target_p = (TREE_TYPE (exp) != void_type_node);
- machine_mode tmode = VOIDmode;
- int nargs, argno;
- rtx value, insn, unspec_args[3];
- tree arg;
-
- /* XnXX form. */
- if (has_target_p)
- {
- tmode = TYPE_MODE (TREE_TYPE (exp));
- if (!target || GET_MODE (target) != tmode
- || !REG_P (target))
- target = gen_reg_rtx (tmode);
- }
-
- nargs = call_expr_nargs (exp);
- for (argno = 0; argno < nargs; argno++)
- {
- arg = CALL_EXPR_ARG (exp, argno);
- value = expand_normal (arg);
- unspec_args[argno] = value;
- if (argno == 0)
- {
- if (!custom_insn_opcode (value, VOIDmode))
- error ("custom instruction opcode must be a compile-time "
- "constant in the range 0-255 for %<__builtin_custom_%s%>",
- custom_builtin_name[index]);
- }
- else
- /* For other arguments, force into a register. */
- unspec_args[argno] = force_reg (TYPE_MODE (TREE_TYPE (arg)),
- unspec_args[argno]);
- }
- /* Fill remaining unspec operands with zero. */
- for (; argno < 3; argno++)
- unspec_args[argno] = const0_rtx;
-
- insn = (has_target_p
- ? gen_rtx_SET (target,
- gen_rtx_UNSPEC_VOLATILE (tmode,
- gen_rtvec_v (3, unspec_args),
- UNSPECV_CUSTOM_XNXX))
- : gen_rtx_UNSPEC_VOLATILE (VOIDmode, gen_rtvec_v (3, unspec_args),
- UNSPECV_CUSTOM_NXX));
- emit_insn (insn);
- return has_target_p ? target : const0_rtx;
-}
-
-
-
-
-/* Main definition of built-in functions. Nios II has a small number of fixed
- builtins, plus a large number of FPU insn builtins, and builtins for
- generating custom instructions. */
-
-struct nios2_builtin_desc
-{
- enum insn_code icode;
- enum nios2_arch_type arch;
- enum nios2_ftcode ftype;
- const char *name;
-};
-
-#define N2_BUILTINS \
- N2_BUILTIN_DEF (sync, R1, N2_FTYPE_VOID_VOID) \
- N2_BUILTIN_DEF (ldbio, R1, N2_FTYPE_SI_CVPTR) \
- N2_BUILTIN_DEF (ldbuio, R1, N2_FTYPE_UI_CVPTR) \
- N2_BUILTIN_DEF (ldhio, R1, N2_FTYPE_SI_CVPTR) \
- N2_BUILTIN_DEF (ldhuio, R1, N2_FTYPE_UI_CVPTR) \
- N2_BUILTIN_DEF (ldwio, R1, N2_FTYPE_SI_CVPTR) \
- N2_BUILTIN_DEF (stbio, R1, N2_FTYPE_VOID_VPTR_SI) \
- N2_BUILTIN_DEF (sthio, R1, N2_FTYPE_VOID_VPTR_SI) \
- N2_BUILTIN_DEF (stwio, R1, N2_FTYPE_VOID_VPTR_SI) \
- N2_BUILTIN_DEF (rdctl, R1, N2_FTYPE_SI_SI) \
- N2_BUILTIN_DEF (wrctl, R1, N2_FTYPE_VOID_SI_SI) \
- N2_BUILTIN_DEF (rdprs, R1, N2_FTYPE_SI_SI_SI) \
- N2_BUILTIN_DEF (flushd, R1, N2_FTYPE_VOID_VPTR) \
- N2_BUILTIN_DEF (flushda, R1, N2_FTYPE_VOID_VPTR) \
- N2_BUILTIN_DEF (wrpie, R2, N2_FTYPE_SI_SI) \
- N2_BUILTIN_DEF (eni, R2, N2_FTYPE_VOID_SI) \
- N2_BUILTIN_DEF (ldex, R2, N2_FTYPE_SI_CVPTR) \
- N2_BUILTIN_DEF (ldsex, R2, N2_FTYPE_SI_CVPTR) \
- N2_BUILTIN_DEF (stex, R2, N2_FTYPE_SI_VPTR_SI) \
- N2_BUILTIN_DEF (stsex, R2, N2_FTYPE_SI_VPTR_SI)
-
-enum nios2_builtin_code {
-#define N2_BUILTIN_DEF(name, arch, ftype) NIOS2_BUILTIN_ ## name,
- N2_BUILTINS
-#undef N2_BUILTIN_DEF
- NUM_FIXED_NIOS2_BUILTINS
-};
-
-static const struct nios2_builtin_desc nios2_builtins[] = {
-#define N2_BUILTIN_DEF(name, arch, ftype) \
- { CODE_FOR_ ## name, ARCH_ ## arch, ftype, "__builtin_" #name },
- N2_BUILTINS
-#undef N2_BUILTIN_DEF
-};
-
-/* Start/ends of FPU/custom insn builtin index ranges. */
-static unsigned int nios2_fpu_builtin_base;
-static unsigned int nios2_custom_builtin_base;
-static unsigned int nios2_custom_builtin_end;
-
-/* Implement TARGET_INIT_BUILTINS. */
-static void
-nios2_init_builtins (void)
-{
- unsigned int i;
-
- /* Initialize fixed builtins. */
- for (i = 0; i < ARRAY_SIZE (nios2_builtins); i++)
- {
- const struct nios2_builtin_desc *d = &nios2_builtins[i];
- tree fndecl =
- add_builtin_function (d->name, nios2_ftype (d->ftype), i,
- BUILT_IN_MD, NULL, NULL);
- nios2_register_builtin_fndecl (i, fndecl);
- }
-
- /* Initialize FPU builtins. */
- nios2_fpu_builtin_base = ARRAY_SIZE (nios2_builtins);
- nios2_init_fpu_builtins (nios2_fpu_builtin_base);
-
- /* Initialize custom insn builtins. */
- nios2_custom_builtin_base
- = nios2_fpu_builtin_base + ARRAY_SIZE (nios2_fpu_insn);
- nios2_custom_builtin_end
- = nios2_custom_builtin_base + NUM_CUSTOM_BUILTINS;
- nios2_init_custom_builtins (nios2_custom_builtin_base);
-}
-
-/* Array of fndecls for TARGET_BUILTIN_DECL. */
-#define NIOS2_NUM_BUILTINS \
- (ARRAY_SIZE (nios2_builtins) + ARRAY_SIZE (nios2_fpu_insn) + NUM_CUSTOM_BUILTINS)
-static GTY(()) tree nios2_builtin_decls[NIOS2_NUM_BUILTINS];
-
-static void
-nios2_register_builtin_fndecl (unsigned code, tree fndecl)
-{
- nios2_builtin_decls[code] = fndecl;
-}
-
-/* Implement TARGET_BUILTIN_DECL. */
-static tree
-nios2_builtin_decl (unsigned code, bool initialize_p ATTRIBUTE_UNUSED)
-{
- gcc_assert (nios2_custom_builtin_end == ARRAY_SIZE (nios2_builtin_decls));
-
- if (code >= nios2_custom_builtin_end)
- return error_mark_node;
-
- if (code >= nios2_fpu_builtin_base
- && code < nios2_custom_builtin_base
- && ! N2FPU_ENABLED_P (code - nios2_fpu_builtin_base))
- return error_mark_node;
-
- return nios2_builtin_decls[code];
-}
-
-
-/* Low-level built-in expand routine. */
-static rtx
-nios2_expand_builtin_insn (const struct nios2_builtin_desc *d, int n,
- struct expand_operand *ops, bool has_target_p)
-{
- if (maybe_expand_insn (d->icode, n, ops))
- return has_target_p ? ops[0].value : const0_rtx;
- else
- {
- error ("invalid argument to built-in function %s", d->name);
- return has_target_p ? gen_reg_rtx (ops[0].mode) : const0_rtx;
- }
-}
-
-/* Expand ldio/stio and ldex/ldsex/stex/stsex form load-store
- instruction builtins. */
-static rtx
-nios2_expand_ldst_builtin (tree exp, rtx target,
- const struct nios2_builtin_desc *d)
-{
- bool has_target_p;
- rtx addr, mem, val;
- struct expand_operand ops[MAX_RECOG_OPERANDS];
- machine_mode mode = insn_data[d->icode].operand[0].mode;
-
- addr = expand_normal (CALL_EXPR_ARG (exp, 0));
- mem = gen_rtx_MEM (mode, addr);
-
- if (insn_data[d->icode].operand[0].allows_mem)
- {
- /* stxio/stex/stsex. */
- val = expand_normal (CALL_EXPR_ARG (exp, 1));
- if (CONST_INT_P (val))
- val = force_reg (mode, gen_int_mode (INTVAL (val), mode));
- val = simplify_gen_subreg (mode, val, GET_MODE (val), 0);
- create_output_operand (&ops[0], mem, mode);
- create_input_operand (&ops[1], val, mode);
- if (insn_data[d->icode].n_operands == 3)
- {
- /* stex/stsex status value, returned as result of function. */
- create_output_operand (&ops[2], target, mode);
- has_target_p = true;
- }
- else
- has_target_p = false;
- }
- else
- {
- /* ldxio. */
- create_output_operand (&ops[0], target, mode);
- create_input_operand (&ops[1], mem, mode);
- has_target_p = true;
- }
- return nios2_expand_builtin_insn (d, insn_data[d->icode].n_operands, ops,
- has_target_p);
-}
-
-/* Expand rdctl/wrctl builtins. */
-static rtx
-nios2_expand_rdwrctl_builtin (tree exp, rtx target,
- const struct nios2_builtin_desc *d)
-{
- bool has_target_p = (insn_data[d->icode].operand[0].predicate
- == register_operand);
- rtx ctlcode = expand_normal (CALL_EXPR_ARG (exp, 0));
- struct expand_operand ops[MAX_RECOG_OPERANDS];
- if (!rdwrctl_operand (ctlcode, VOIDmode))
- {
- error ("control register number must be in range 0-31 for %s",
- d->name);
- return has_target_p ? gen_reg_rtx (SImode) : const0_rtx;
- }
- if (has_target_p)
- {
- create_output_operand (&ops[0], target, SImode);
- create_integer_operand (&ops[1], INTVAL (ctlcode));
- }
- else
- {
- rtx val = expand_normal (CALL_EXPR_ARG (exp, 1));
- create_integer_operand (&ops[0], INTVAL (ctlcode));
- create_input_operand (&ops[1], val, SImode);
- }
- return nios2_expand_builtin_insn (d, 2, ops, has_target_p);
-}
-
-static rtx
-nios2_expand_rdprs_builtin (tree exp, rtx target,
- const struct nios2_builtin_desc *d)
-{
- rtx reg = expand_normal (CALL_EXPR_ARG (exp, 0));
- rtx imm = expand_normal (CALL_EXPR_ARG (exp, 1));
- struct expand_operand ops[MAX_RECOG_OPERANDS];
-
- if (!rdwrctl_operand (reg, VOIDmode))
- {
- error ("register number must be in range 0-31 for %s",
- d->name);
- return gen_reg_rtx (SImode);
- }
-
- if (!rdprs_dcache_operand (imm, VOIDmode))
- {
- error ("immediate value must fit into a %d-bit integer for %s",
- (TARGET_ARCH_R2) ? 12 : 16, d->name);
- return gen_reg_rtx (SImode);
- }
-
- create_output_operand (&ops[0], target, SImode);
- create_input_operand (&ops[1], reg, SImode);
- create_integer_operand (&ops[2], INTVAL (imm));
-
- return nios2_expand_builtin_insn (d, 3, ops, true);
-}
-
-static rtx
-nios2_expand_cache_builtin (tree exp, rtx target ATTRIBUTE_UNUSED,
- const struct nios2_builtin_desc *d)
-{
- rtx mem, addr;
- struct expand_operand ops[MAX_RECOG_OPERANDS];
-
- addr = expand_normal (CALL_EXPR_ARG (exp, 0));
- mem = gen_rtx_MEM (SImode, addr);
-
- create_input_operand (&ops[0], mem, SImode);
-
- return nios2_expand_builtin_insn (d, 1, ops, false);
-}
-
-static rtx
-nios2_expand_wrpie_builtin (tree exp, rtx target,
- const struct nios2_builtin_desc *d)
-{
- rtx val;
- struct expand_operand ops[MAX_RECOG_OPERANDS];
-
- val = expand_normal (CALL_EXPR_ARG (exp, 0));
- create_input_operand (&ops[1], val, SImode);
- create_output_operand (&ops[0], target, SImode);
-
- return nios2_expand_builtin_insn (d, 2, ops, true);
-}
-
-static rtx
-nios2_expand_eni_builtin (tree exp, rtx target ATTRIBUTE_UNUSED,
- const struct nios2_builtin_desc *d)
-{
- rtx imm = expand_normal (CALL_EXPR_ARG (exp, 0));
- struct expand_operand ops[MAX_RECOG_OPERANDS];
-
- if (INTVAL (imm) != 0 && INTVAL (imm) != 1)
- {
- error ("the ENI instruction operand must be either 0 or 1");
- return const0_rtx;
- }
- create_integer_operand (&ops[0], INTVAL (imm));
-
- return nios2_expand_builtin_insn (d, 1, ops, false);
-}
-
-/* Implement TARGET_EXPAND_BUILTIN. Expand an expression EXP that calls
- a built-in function, with result going to TARGET if that's convenient
- (and in mode MODE if that's convenient).
- SUBTARGET may be used as the target for computing one of EXP's operands.
- IGNORE is nonzero if the value is to be ignored. */
-
-static rtx
-nios2_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
- machine_mode mode ATTRIBUTE_UNUSED,
- int ignore ATTRIBUTE_UNUSED)
-{
- tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
- unsigned int fcode = DECL_MD_FUNCTION_CODE (fndecl);
-
- if (fcode < nios2_fpu_builtin_base)
- {
- const struct nios2_builtin_desc *d = &nios2_builtins[fcode];
-
- if (d->arch > nios2_arch_option)
- {
- error ("built-in function %s requires Nios II R%d",
- d->name, (int) d->arch);
- /* Given it is invalid, just generate a normal call. */
- return expand_call (exp, target, ignore);
- }
-
- switch (fcode)
- {
- case NIOS2_BUILTIN_sync:
- emit_insn (gen_sync ());
- return const0_rtx;
-
- case NIOS2_BUILTIN_ldbio:
- case NIOS2_BUILTIN_ldbuio:
- case NIOS2_BUILTIN_ldhio:
- case NIOS2_BUILTIN_ldhuio:
- case NIOS2_BUILTIN_ldwio:
- case NIOS2_BUILTIN_stbio:
- case NIOS2_BUILTIN_sthio:
- case NIOS2_BUILTIN_stwio:
- case NIOS2_BUILTIN_ldex:
- case NIOS2_BUILTIN_ldsex:
- case NIOS2_BUILTIN_stex:
- case NIOS2_BUILTIN_stsex:
- return nios2_expand_ldst_builtin (exp, target, d);
-
- case NIOS2_BUILTIN_rdctl:
- case NIOS2_BUILTIN_wrctl:
- return nios2_expand_rdwrctl_builtin (exp, target, d);
-
- case NIOS2_BUILTIN_rdprs:
- return nios2_expand_rdprs_builtin (exp, target, d);
-
- case NIOS2_BUILTIN_flushd:
- case NIOS2_BUILTIN_flushda:
- return nios2_expand_cache_builtin (exp, target, d);
-
- case NIOS2_BUILTIN_wrpie:
- return nios2_expand_wrpie_builtin (exp, target, d);
-
- case NIOS2_BUILTIN_eni:
- return nios2_expand_eni_builtin (exp, target, d);
-
- default:
- gcc_unreachable ();
- }
- }
- else if (fcode < nios2_custom_builtin_base)
- /* FPU builtin range. */
- return nios2_expand_fpu_builtin (exp, fcode - nios2_fpu_builtin_base,
- target);
- else if (fcode < nios2_custom_builtin_end)
- /* Custom insn builtin range. */
- return nios2_expand_custom_builtin (exp, fcode - nios2_custom_builtin_base,
- target);
- else
- gcc_unreachable ();
-}
-
-/* Implement TARGET_INIT_LIBFUNCS. */
-static void ATTRIBUTE_UNUSED
-nios2_init_libfuncs (void)
-{
- init_sync_libfuncs (UNITS_PER_WORD);
-}
-
-
-
-/* Register a custom code use, and signal error if a conflict was found. */
-static void
-nios2_register_custom_code (unsigned int N, enum nios2_ccs_code status,
- int index)
-{
- gcc_assert (N <= 255);
-
- if (status == CCS_FPU)
- {
- if (custom_code_status[N] == CCS_FPU && index != custom_code_index[N])
- {
- custom_code_conflict = true;
- error ("switch %<-mcustom-%s%> conflicts with "
- "switch %<-mcustom-%s%>",
- N2FPU_NAME (custom_code_index[N]), N2FPU_NAME (index));
- }
- else if (custom_code_status[N] == CCS_BUILTIN_CALL)
- {
- custom_code_conflict = true;
- error ("call to %<__builtin_custom_%s%> conflicts with "
- "switch %<-mcustom-%s%>",
- custom_builtin_name[custom_code_index[N]],
- N2FPU_NAME (index));
- }
- }
- else if (status == CCS_BUILTIN_CALL)
- {
- if (custom_code_status[N] == CCS_FPU)
- {
- custom_code_conflict = true;
- error ("call to %<__builtin_custom_%s%> conflicts with "
- "switch %<-mcustom-%s%>",
- custom_builtin_name[index],
- N2FPU_NAME (custom_code_index[N]));
- }
- else
- {
- /* Note that code conflicts between different __builtin_custom_xnxx
- calls are not checked. */
- }
- }
- else
- gcc_unreachable ();
-
- custom_code_status[N] = status;
- custom_code_index[N] = index;
-}
-
-/* Mark a custom code as not in use. */
-static void
-nios2_deregister_custom_code (unsigned int N)
-{
- if (N <= 255)
- {
- custom_code_status[N] = CCS_UNUSED;
- custom_code_index[N] = 0;
- }
-}
-
-/* Target attributes can affect per-function option state, so we need to
- save/restore the custom code tracking info using the
- TARGET_OPTION_SAVE/TARGET_OPTION_RESTORE hooks. */
-
-static void
-nios2_option_save (struct cl_target_option *ptr,
- struct gcc_options *opts ATTRIBUTE_UNUSED,
- struct gcc_options *opts_set ATTRIBUTE_UNUSED)
-{
- unsigned int i;
- for (i = 0; i < ARRAY_SIZE (nios2_fpu_insn); i++)
- ptr->saved_fpu_custom_code[i] = N2FPU_N (i);
- memcpy (ptr->saved_custom_code_status, custom_code_status,
- sizeof (custom_code_status));
- memcpy (ptr->saved_custom_code_index, custom_code_index,
- sizeof (custom_code_index));
-}
-
-static void
-nios2_option_restore (struct gcc_options *opts ATTRIBUTE_UNUSED,
- struct gcc_options *opts_set ATTRIBUTE_UNUSED,
- struct cl_target_option *ptr)
-{
- unsigned int i;
- for (i = 0; i < ARRAY_SIZE (nios2_fpu_insn); i++)
- N2FPU_N (i) = ptr->saved_fpu_custom_code[i];
- memcpy (custom_code_status, ptr->saved_custom_code_status,
- sizeof (custom_code_status));
- memcpy (custom_code_index, ptr->saved_custom_code_index,
- sizeof (custom_code_index));
-}
-
-static bool
-nios2_can_inline_p (tree caller, tree callee)
-{
- tree callee_opts = DECL_FUNCTION_SPECIFIC_TARGET (callee);
- tree caller_opts = DECL_FUNCTION_SPECIFIC_TARGET (caller);
- struct cl_target_option *callee_ptr, *caller_ptr;
- unsigned int i;
-
- if (! callee_opts)
- callee_opts = target_option_default_node;
- if (! caller_opts)
- caller_opts = target_option_default_node;
-
- /* If both caller and callee have attributes, assume that if the
- pointer is different, the two functions have different target
- options since build_target_option_node uses a hash table for the
- options. */
- if (callee_opts == caller_opts)
- return true;
-
- /* The only target options we recognize via function attributes are
- those related to custom instructions. If we failed the above test,
- check that any custom instructions enabled in the callee are also
- enabled with the same value in the caller. */
- callee_ptr = TREE_TARGET_OPTION (callee_opts);
- caller_ptr = TREE_TARGET_OPTION (caller_opts);
- for (i = 0; i < ARRAY_SIZE (nios2_fpu_insn); i++)
- if (callee_ptr->saved_fpu_custom_code[i] != -1
- && (callee_ptr->saved_fpu_custom_code[i]
- != caller_ptr->saved_fpu_custom_code[i]))
- return false;
- return true;
-}
-
-/* Inner function to process the attribute((target(...))), take an argument and
- set the current options from the argument. If we have a list, recursively
- go over the list. */
-
-static bool
-nios2_valid_target_attribute_rec (tree args)
-{
- if (TREE_CODE (args) == TREE_LIST)
- {
- bool ret = true;
- for (; args; args = TREE_CHAIN (args))
- if (TREE_VALUE (args)
- && !nios2_valid_target_attribute_rec (TREE_VALUE (args)))
- ret = false;
- return ret;
- }
- else if (TREE_CODE (args) == STRING_CST)
- {
- char *argstr = ASTRDUP (TREE_STRING_POINTER (args));
- while (argstr && *argstr != '\0')
- {
- bool no_opt = false, end_p = false;
- char *eq = NULL, *p;
- while (ISSPACE (*argstr))
- argstr++;
- p = argstr;
- while (*p != '\0' && *p != ',')
- {
- if (!eq && *p == '=')
- eq = p;
- ++p;
- }
- if (*p == '\0')
- end_p = true;
- else
- *p = '\0';
- if (eq) *eq = '\0';
-
- if (startswith (argstr, "no-"))
- {
- no_opt = true;
- argstr += 3;
- }
- if (startswith (argstr, "custom-fpu-cfg"))
- {
- char *end_eq = p;
- if (no_opt)
- {
- error ("%<custom-fpu-cfg%> option does not support %<no-%>");
- return false;
- }
- if (!eq)
- {
- error ("%<custom-fpu-cfg%> option requires configuration "
- "argument");
- return false;
- }
- /* Increment and skip whitespace. */
- while (ISSPACE (*(++eq))) ;
- /* Decrement and skip to before any trailing whitespace. */
- while (ISSPACE (*(--end_eq))) ;
-
- nios2_handle_custom_fpu_cfg (eq, end_eq + 1, true);
- }
- else if (startswith (argstr, "custom-"))
- {
- int code = -1;
- unsigned int i;
- for (i = 0; i < ARRAY_SIZE (nios2_fpu_insn); i++)
- if (startswith (argstr + 7, N2FPU_NAME (i)))
- {
- /* Found insn. */
- code = i;
- break;
- }
- if (code >= 0)
- {
- if (no_opt)
- {
- if (eq)
- {
- error ("%<no-custom-%s%> does not accept arguments",
- N2FPU_NAME (code));
- return false;
- }
- /* Disable option by setting to -1. */
- nios2_deregister_custom_code (N2FPU_N (code));
- N2FPU_N (code) = -1;
- }
- else
- {
- char *t;
- if (eq)
- while (ISSPACE (*(++eq))) ;
- if (!eq || eq == p)
- {
- error ("%<custom-%s=%> requires argument",
- N2FPU_NAME (code));
- return false;
- }
- for (t = eq; t != p; ++t)
- {
- if (ISSPACE (*t))
- continue;
- if (!ISDIGIT (*t))
- {
- error ("%<custom-%s=%> argument should be "
- "a non-negative integer", N2FPU_NAME (code));
- return false;
- }
- }
- /* Set option to argument. */
- N2FPU_N (code) = atoi (eq);
- nios2_handle_custom_fpu_insn_option (code);
- }
- }
- else
- {
- error ("%<custom-%s=%> is not recognized as FPU instruction",
- argstr + 7);
- return false;
- }
- }
- else
- {
- error ("invalid custom instruction option %qs", argstr);
- return false;
- }
-
- if (end_p)
- break;
- else
- argstr = p + 1;
- }
- return true;
- }
- else
- gcc_unreachable ();
-}
-
-/* Return a TARGET_OPTION_NODE tree of the target options listed or NULL. */
-
-static tree
-nios2_valid_target_attribute_tree (tree args)
-{
- if (!nios2_valid_target_attribute_rec (args))
- return NULL_TREE;
- nios2_custom_check_insns ();
- return build_target_option_node (&global_options, &global_options_set);
-}
-
-/* Hook to validate attribute((target("string"))). */
-
-static bool
-nios2_valid_target_attribute_p (tree fndecl, tree ARG_UNUSED (name),
- tree args, int ARG_UNUSED (flags))
-{
- struct cl_target_option cur_target;
- bool ret = true;
- tree old_optimize
- = build_optimization_node (&global_options, &global_options_set);
- tree new_target, new_optimize;
- tree func_optimize = DECL_FUNCTION_SPECIFIC_OPTIMIZATION (fndecl);
-
- /* If the function changed the optimization levels as well as setting target
- options, start with the optimizations specified. */
- if (func_optimize && func_optimize != old_optimize)
- cl_optimization_restore (&global_options, &global_options_set,
- TREE_OPTIMIZATION (func_optimize));
-
- /* The target attributes may also change some optimization flags, so update
- the optimization options if necessary. */
- cl_target_option_save (&cur_target, &global_options, &global_options_set);
- new_target = nios2_valid_target_attribute_tree (args);
- new_optimize = build_optimization_node (&global_options, &global_options_set);
-
- if (!new_target)
- ret = false;
-
- else if (fndecl)
- {
- DECL_FUNCTION_SPECIFIC_TARGET (fndecl) = new_target;
-
- if (old_optimize != new_optimize)
- DECL_FUNCTION_SPECIFIC_OPTIMIZATION (fndecl) = new_optimize;
- }
-
- cl_target_option_restore (&global_options, &global_options_set, &cur_target);
-
- if (old_optimize != new_optimize)
- cl_optimization_restore (&global_options, &global_options_set,
- TREE_OPTIMIZATION (old_optimize));
- return ret;
-}
-
-/* Remember the last target of nios2_set_current_function. */
-static GTY(()) tree nios2_previous_fndecl;
-
-/* Establish appropriate back-end context for processing the function
- FNDECL. The argument might be NULL to indicate processing at top
- level, outside of any function scope. */
-static void
-nios2_set_current_function (tree fndecl)
-{
- tree old_tree = (nios2_previous_fndecl
- ? DECL_FUNCTION_SPECIFIC_TARGET (nios2_previous_fndecl)
- : NULL_TREE);
-
- tree new_tree = (fndecl
- ? DECL_FUNCTION_SPECIFIC_TARGET (fndecl)
- : NULL_TREE);
-
- if (fndecl && fndecl != nios2_previous_fndecl)
- {
- nios2_previous_fndecl = fndecl;
- if (old_tree == new_tree)
- ;
-
- else if (new_tree)
- {
- cl_target_option_restore (&global_options, &global_options_set,
- TREE_TARGET_OPTION (new_tree));
- target_reinit ();
- }
-
- else if (old_tree)
- {
- struct cl_target_option *def
- = TREE_TARGET_OPTION (target_option_current_node);
-
- cl_target_option_restore (&global_options, &global_options_set, def);
- target_reinit ();
- }
- }
-}
-
-/* Hook to validate the current #pragma GCC target and set the FPU custom
- code option state. If ARGS is NULL, then POP_TARGET is used to reset
- the options. */
-static bool
-nios2_pragma_target_parse (tree args, tree pop_target)
-{
- tree cur_tree;
- if (! args)
- {
- cur_tree = ((pop_target)
- ? pop_target
- : target_option_default_node);
- cl_target_option_restore (&global_options, &global_options_set,
- TREE_TARGET_OPTION (cur_tree));
- }
- else
- {
- cur_tree = nios2_valid_target_attribute_tree (args);
- if (!cur_tree)
- return false;
- }
-
- target_option_current_node = cur_tree;
- return true;
-}
-
-/* Implement TARGET_MERGE_DECL_ATTRIBUTES.
- We are just using this hook to add some additional error checking to
- the default behavior. GCC does not provide a target hook for merging
- the target options, and only correctly handles merging empty vs non-empty
- option data; see merge_decls() in c-decl.cc.
- So here we require either that at least one of the decls has empty
- target options, or that the target options/data be identical. */
-static tree
-nios2_merge_decl_attributes (tree olddecl, tree newdecl)
-{
- tree oldopts = lookup_attribute ("target", DECL_ATTRIBUTES (olddecl));
- tree newopts = lookup_attribute ("target", DECL_ATTRIBUTES (newdecl));
- if (newopts && oldopts && newopts != oldopts)
- {
- tree oldtree = DECL_FUNCTION_SPECIFIC_TARGET (olddecl);
- tree newtree = DECL_FUNCTION_SPECIFIC_TARGET (newdecl);
- if (oldtree && newtree && oldtree != newtree)
- {
- struct cl_target_option *olddata = TREE_TARGET_OPTION (oldtree);
- struct cl_target_option *newdata = TREE_TARGET_OPTION (newtree);
- if (olddata != newdata
- && memcmp (olddata, newdata, sizeof (struct cl_target_option)))
- error ("%qE redeclared with conflicting %qs attributes",
- DECL_NAME (newdecl), "target");
- }
- }
- return merge_attributes (DECL_ATTRIBUTES (olddecl),
- DECL_ATTRIBUTES (newdecl));
-}
-
-/* Implement TARGET_ASM_OUTPUT_MI_THUNK. */
-static void
-nios2_asm_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
- HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
- tree function)
-{
- const char *fnname = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (thunk_fndecl));
- rtx this_rtx, funexp;
- rtx_insn *insn;
-
- /* Pretend to be a post-reload pass while generating rtl. */
- reload_completed = 1;
-
- if (flag_pic)
- nios2_load_pic_register ();
-
- /* Mark the end of the (empty) prologue. */
- emit_note (NOTE_INSN_PROLOGUE_END);
-
- /* Find the "this" pointer. If the function returns a structure,
- the structure return pointer is in $5. */
- if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
- this_rtx = gen_rtx_REG (Pmode, FIRST_ARG_REGNO + 1);
- else
- this_rtx = gen_rtx_REG (Pmode, FIRST_ARG_REGNO);
-
- /* Add DELTA to THIS_RTX. */
- nios2_emit_add_constant (this_rtx, delta);
-
- /* If needed, add *(*THIS_RTX + VCALL_OFFSET) to THIS_RTX. */
- if (vcall_offset)
- {
- rtx tmp;
-
- tmp = gen_rtx_REG (Pmode, 2);
- emit_move_insn (tmp, gen_rtx_MEM (Pmode, this_rtx));
- nios2_emit_add_constant (tmp, vcall_offset);
- emit_move_insn (tmp, gen_rtx_MEM (Pmode, tmp));
- emit_insn (gen_add2_insn (this_rtx, tmp));
- }
-
- /* Generate a tail call to the target function. */
- if (!TREE_USED (function))
- {
- assemble_external (function);
- TREE_USED (function) = 1;
- }
- funexp = XEXP (DECL_RTL (function), 0);
- /* Function address needs to be constructed under PIC,
- provide r2 to use here. */
- nios2_adjust_call_address (&funexp, gen_rtx_REG (Pmode, 2));
- insn = emit_call_insn (gen_sibcall_internal (funexp, const0_rtx));
- SIBLING_CALL_P (insn) = 1;
-
- /* Run just enough of rest_of_compilation to get the insns emitted.
- There's not really enough bulk here to make other passes such as
- instruction scheduling worth while. */
- insn = get_insns ();
- shorten_branches (insn);
- assemble_start_function (thunk_fndecl, fnname);
- final_start_function (insn, file, 1);
- final (insn, file, 1);
- final_end_function ();
- assemble_end_function (thunk_fndecl, fnname);
-
- /* Stop pretending to be a post-reload pass. */
- reload_completed = 0;
-}
-
-
-/* Utility function to break a memory address into
- base register + constant offset. Return false if something
- unexpected is seen. */
-static bool
-split_mem_address (rtx addr, rtx *base_reg, rtx *offset)
-{
- if (REG_P (addr))
- {
- *base_reg = addr;
- *offset = const0_rtx;
- return true;
- }
- else if (GET_CODE (addr) == PLUS)
- {
- *base_reg = XEXP (addr, 0);
- *offset = XEXP (addr, 1);
- return true;
- }
- return false;
-}
-
-/* Splits out the operands of an ALU insn, places them in *LHS, *RHS1, *RHS2. */
-static void
-split_alu_insn (rtx_insn *insn, rtx *lhs, rtx *rhs1, rtx *rhs2)
-{
- rtx pat = PATTERN (insn);
- gcc_assert (GET_CODE (pat) == SET);
- *lhs = SET_DEST (pat);
- *rhs1 = XEXP (SET_SRC (pat), 0);
- if (GET_RTX_CLASS (GET_CODE (SET_SRC (pat))) != RTX_UNARY)
- *rhs2 = XEXP (SET_SRC (pat), 1);
- return;
-}
-
-/* Returns true if OP is a REG and assigned a CDX reg. */
-static bool
-cdxreg (rtx op)
-{
- return REG_P (op) && (!reload_completed || CDX_REG_P (REGNO (op)));
-}
-
-/* Returns true if OP is within range of CDX addi.n immediates. */
-static bool
-cdx_add_immed (rtx op)
-{
- if (CONST_INT_P (op))
- {
- HOST_WIDE_INT ival = INTVAL (op);
- return ival <= 128 && ival > 0 && (ival & (ival - 1)) == 0;
- }
- return false;
-}
-
-/* Returns true if OP is within range of CDX andi.n immediates. */
-static bool
-cdx_and_immed (rtx op)
-{
- if (CONST_INT_P (op))
- {
- HOST_WIDE_INT ival = INTVAL (op);
- return (ival == 1 || ival == 2 || ival == 3 || ival == 4
- || ival == 8 || ival == 0xf || ival == 0x10
- || ival == 0x1f || ival == 0x20
- || ival == 0x3f || ival == 0x7f
- || ival == 0x80 || ival == 0xff || ival == 0x7ff
- || ival == 0xff00 || ival == 0xffff);
- }
- return false;
-}
-
-/* Returns true if OP is within range of CDX movi.n immediates. */
-static bool
-cdx_mov_immed (rtx op)
-{
- if (CONST_INT_P (op))
- {
- HOST_WIDE_INT ival = INTVAL (op);
- return ((ival >= 0 && ival <= 124)
- || ival == 0xff || ival == -2 || ival == -1);
- }
- return false;
-}
-
-/* Returns true if OP is within range of CDX slli.n/srli.n immediates. */
-static bool
-cdx_shift_immed (rtx op)
-{
- if (CONST_INT_P (op))
- {
- HOST_WIDE_INT ival = INTVAL (op);
- return (ival == 1 || ival == 2 || ival == 3 || ival == 8
- || ival == 12 || ival == 16 || ival == 24
- || ival == 31);
- }
- return false;
-}
-
-
-
-/* Classification of different kinds of add instructions. */
-enum nios2_add_insn_kind {
- nios2_add_n_kind,
- nios2_addi_n_kind,
- nios2_subi_n_kind,
- nios2_spaddi_n_kind,
- nios2_spinci_n_kind,
- nios2_spdeci_n_kind,
- nios2_add_kind,
- nios2_addi_kind
-};
-
-static const char *nios2_add_insn_names[] = {
- "add.n", "addi.n", "subi.n", "spaddi.n", "spinci.n", "spdeci.n",
- "add", "addi" };
-static bool nios2_add_insn_narrow[] = {
- true, true, true, true, true, true,
- false, false};
-
-/* Function to classify kinds of add instruction patterns. */
-static enum nios2_add_insn_kind
-nios2_add_insn_classify (rtx_insn *insn ATTRIBUTE_UNUSED,
- rtx lhs, rtx rhs1, rtx rhs2)
-{
- if (TARGET_HAS_CDX)
- {
- if (cdxreg (lhs) && cdxreg (rhs1))
- {
- if (cdxreg (rhs2))
- return nios2_add_n_kind;
- if (CONST_INT_P (rhs2))
- {
- HOST_WIDE_INT ival = INTVAL (rhs2);
- if (ival > 0 && cdx_add_immed (rhs2))
- return nios2_addi_n_kind;
- if (ival < 0 && cdx_add_immed (GEN_INT (-ival)))
- return nios2_subi_n_kind;
- }
- }
- else if (rhs1 == stack_pointer_rtx
- && CONST_INT_P (rhs2))
- {
- HOST_WIDE_INT imm7 = INTVAL (rhs2) >> 2;
- HOST_WIDE_INT rem = INTVAL (rhs2) & 3;
- if (rem == 0 && (imm7 & ~0x7f) == 0)
- {
- if (cdxreg (lhs))
- return nios2_spaddi_n_kind;
- if (lhs == stack_pointer_rtx)
- return nios2_spinci_n_kind;
- }
- imm7 = -INTVAL(rhs2) >> 2;
- rem = -INTVAL (rhs2) & 3;
- if (lhs == stack_pointer_rtx
- && rem == 0 && (imm7 & ~0x7f) == 0)
- return nios2_spdeci_n_kind;
- }
- }
- return ((REG_P (rhs2) || rhs2 == const0_rtx)
- ? nios2_add_kind : nios2_addi_kind);
-}
-
-/* Emit assembly language for the different kinds of add instructions. */
-const char*
-nios2_add_insn_asm (rtx_insn *insn, rtx *operands)
-{
- static char buf[256];
- int ln = 256;
- enum nios2_add_insn_kind kind
- = nios2_add_insn_classify (insn, operands[0], operands[1], operands[2]);
- if (kind == nios2_subi_n_kind)
- snprintf (buf, ln, "subi.n\t%%0, %%1, %d", (int) -INTVAL (operands[2]));
- else if (kind == nios2_spaddi_n_kind)
- snprintf (buf, ln, "spaddi.n\t%%0, %%2");
- else if (kind == nios2_spinci_n_kind)
- snprintf (buf, ln, "spinci.n\t%%2");
- else if (kind == nios2_spdeci_n_kind)
- snprintf (buf, ln, "spdeci.n\t%d", (int) -INTVAL (operands[2]));
- else
- snprintf (buf, ln, "%s\t%%0, %%1, %%z2", nios2_add_insn_names[(int)kind]);
- return buf;
-}
-
-/* This routine, which the default "length" attribute computation is
- based on, encapsulates information about all the cases where CDX
- provides a narrow 2-byte instruction form. */
-bool
-nios2_cdx_narrow_form_p (rtx_insn *insn)
-{
- rtx pat, lhs, rhs1 = NULL_RTX, rhs2 = NULL_RTX;
- enum attr_type type;
- if (!TARGET_HAS_CDX)
- return false;
- type = get_attr_type (insn);
- pat = PATTERN (insn);
- gcc_assert (reload_completed);
- switch (type)
- {
- case TYPE_CONTROL:
- if (GET_CODE (pat) == SIMPLE_RETURN)
- return true;
- if (GET_CODE (pat) == PARALLEL)
- pat = XVECEXP (pat, 0, 0);
- if (GET_CODE (pat) == SET)
- pat = SET_SRC (pat);
- if (GET_CODE (pat) == IF_THEN_ELSE)
- {
- /* Conditional branch patterns; for these we
- only check the comparison to find beqz.n/bnez.n cases.
- For the 'nios2_cbranch' pattern, we cannot also check
- the branch range here. That will be done at the md
- pattern "length" attribute computation. */
- rtx cmp = XEXP (pat, 0);
- return ((GET_CODE (cmp) == EQ || GET_CODE (cmp) == NE)
- && cdxreg (XEXP (cmp, 0))
- && XEXP (cmp, 1) == const0_rtx);
- }
- if (GET_CODE (pat) == TRAP_IF)
- /* trap.n is always usable. */
- return true;
- if (GET_CODE (pat) == CALL)
- pat = XEXP (XEXP (pat, 0), 0);
- if (REG_P (pat))
- /* Control instructions taking a register operand are indirect
- jumps and calls. The CDX instructions have a 5-bit register
- field so any reg is valid. */
- return true;
- else
- {
- gcc_assert (!insn_variable_length_p (insn));
- return false;
- }
- case TYPE_ADD:
- {
- enum nios2_add_insn_kind kind;
- split_alu_insn (insn, &lhs, &rhs1, &rhs2);
- kind = nios2_add_insn_classify (insn, lhs, rhs1, rhs2);
- return nios2_add_insn_narrow[(int)kind];
- }
- case TYPE_LD:
- {
- bool ret;
- HOST_WIDE_INT offset, rem = 0;
- rtx addr, reg = SET_DEST (pat), mem = SET_SRC (pat);
- if (GET_CODE (mem) == SIGN_EXTEND)
- /* No CDX form for sign-extended load. */
- return false;
- if (GET_CODE (mem) == ZERO_EXTEND)
- /* The load alternatives in the zero_extend* patterns. */
- mem = XEXP (mem, 0);
- if (MEM_P (mem))
- {
- /* ldxio. */
- if ((MEM_VOLATILE_P (mem) && TARGET_BYPASS_CACHE_VOLATILE)
- || TARGET_BYPASS_CACHE)
- return false;
- addr = XEXP (mem, 0);
- /* GP-based and R0-based references are never narrow. */
- if (gprel_constant_p (addr) || r0rel_constant_p (addr))
- return false;
- /* %lo requires a 16-bit relocation and is never narrow. */
- if (GET_CODE (addr) == LO_SUM)
- return false;
- ret = split_mem_address (addr, &rhs1, &rhs2);
- gcc_assert (ret);
- }
- else
- return false;
-
- offset = INTVAL (rhs2);
- if (GET_MODE (mem) == SImode)
- {
- rem = offset & 3;
- offset >>= 2;
- /* ldwsp.n case. */
- if (rtx_equal_p (rhs1, stack_pointer_rtx)
- && rem == 0 && (offset & ~0x1f) == 0)
- return true;
- }
- else if (GET_MODE (mem) == HImode)
- {
- rem = offset & 1;
- offset >>= 1;
- }
- /* ldbu.n, ldhu.n, ldw.n cases. */
- return (cdxreg (reg) && cdxreg (rhs1)
- && rem == 0 && (offset & ~0xf) == 0);
- }
- case TYPE_ST:
- if (GET_CODE (pat) == PARALLEL)
- /* stex, stsex. */
- return false;
- else
- {
- bool ret;
- HOST_WIDE_INT offset, rem = 0;
- rtx addr, reg = SET_SRC (pat), mem = SET_DEST (pat);
- if (!MEM_P (mem))
- return false;
- /* stxio. */
- if ((MEM_VOLATILE_P (mem) && TARGET_BYPASS_CACHE_VOLATILE)
- || TARGET_BYPASS_CACHE)
- return false;
- addr = XEXP (mem, 0);
- /* GP-based and r0-based references are never narrow. */
- if (gprel_constant_p (addr) || r0rel_constant_p (addr))
- return false;
- /* %lo requires a 16-bit relocation and is never narrow. */
- if (GET_CODE (addr) == LO_SUM)
- return false;
- ret = split_mem_address (addr, &rhs1, &rhs2);
- gcc_assert (ret);
- offset = INTVAL (rhs2);
- if (GET_MODE (mem) == SImode)
- {
- rem = offset & 3;
- offset >>= 2;
- /* stwsp.n case. */
- if (rtx_equal_p (rhs1, stack_pointer_rtx)
- && rem == 0 && (offset & ~0x1f) == 0)
- return true;
- /* stwz.n case. */
- else if (reg == const0_rtx && cdxreg (rhs1)
- && rem == 0 && (offset & ~0x3f) == 0)
- return true;
- }
- else if (GET_MODE (mem) == HImode)
- {
- rem = offset & 1;
- offset >>= 1;
- }
- else
- {
- gcc_assert (GET_MODE (mem) == QImode);
- /* stbz.n case. */
- if (reg == const0_rtx && cdxreg (rhs1)
- && (offset & ~0x3f) == 0)
- return true;
- }
-
- /* stbu.n, sthu.n, stw.n cases. */
- return (cdxreg (reg) && cdxreg (rhs1)
- && rem == 0 && (offset & ~0xf) == 0);
- }
- case TYPE_MOV:
- lhs = SET_DEST (pat);
- rhs1 = SET_SRC (pat);
- if (CONST_INT_P (rhs1))
- return (cdxreg (lhs) && cdx_mov_immed (rhs1));
- gcc_assert (REG_P (lhs) && REG_P (rhs1));
- return true;
-
- case TYPE_AND:
- /* Some zero_extend* alternatives are and insns. */
- if (GET_CODE (SET_SRC (pat)) == ZERO_EXTEND)
- return (cdxreg (SET_DEST (pat))
- && cdxreg (XEXP (SET_SRC (pat), 0)));
- split_alu_insn (insn, &lhs, &rhs1, &rhs2);
- if (CONST_INT_P (rhs2))
- return (cdxreg (lhs) && cdxreg (rhs1) && cdx_and_immed (rhs2));
- return (cdxreg (lhs) && cdxreg (rhs2)
- && (!reload_completed || rtx_equal_p (lhs, rhs1)));
-
- case TYPE_OR:
- case TYPE_XOR:
- /* Note the two-address limitation for CDX form. */
- split_alu_insn (insn, &lhs, &rhs1, &rhs2);
- return (cdxreg (lhs) && cdxreg (rhs2)
- && (!reload_completed || rtx_equal_p (lhs, rhs1)));
-
- case TYPE_SUB:
- split_alu_insn (insn, &lhs, &rhs1, &rhs2);
- return (cdxreg (lhs) && cdxreg (rhs1) && cdxreg (rhs2));
-
- case TYPE_NEG:
- case TYPE_NOT:
- split_alu_insn (insn, &lhs, &rhs1, NULL);
- return (cdxreg (lhs) && cdxreg (rhs1));
-
- case TYPE_SLL:
- case TYPE_SRL:
- split_alu_insn (insn, &lhs, &rhs1, &rhs2);
- return (cdxreg (lhs)
- && ((cdxreg (rhs1) && cdx_shift_immed (rhs2))
- || (cdxreg (rhs2)
- && (!reload_completed || rtx_equal_p (lhs, rhs1)))));
- case TYPE_NOP:
- case TYPE_PUSH:
- case TYPE_POP:
- return true;
- default:
- break;
- }
- return false;
-}
-
-/* Main function to implement the pop_operation predicate that
- check pop.n insn pattern integrity. The CDX pop.n patterns mostly
- hardcode the restored registers, so the main checking is for the
- SP offsets. */
-bool
-pop_operation_p (rtx op)
-{
- int i;
- HOST_WIDE_INT last_offset = -1, len = XVECLEN (op, 0);
- rtx base_reg, offset;
-
- if (len < 3 /* At least has a return, SP-update, and RA restore. */
- || GET_CODE (XVECEXP (op, 0, 0)) != RETURN
- || !base_reg_adjustment_p (XVECEXP (op, 0, 1), &base_reg, &offset)
- || !rtx_equal_p (base_reg, stack_pointer_rtx)
- || !CONST_INT_P (offset)
- || (INTVAL (offset) & 3) != 0)
- return false;
-
- for (i = len - 1; i > 1; i--)
- {
- rtx set = XVECEXP (op, 0, i);
- rtx curr_base_reg, curr_offset;
-
- if (GET_CODE (set) != SET || !MEM_P (SET_SRC (set))
- || !split_mem_address (XEXP (SET_SRC (set), 0),
- &curr_base_reg, &curr_offset)
- || !rtx_equal_p (base_reg, curr_base_reg)
- || !CONST_INT_P (curr_offset))
- return false;
- if (i == len - 1)
- {
- last_offset = INTVAL (curr_offset);
- if ((last_offset & 3) != 0 || last_offset > 60)
- return false;
- }
- else
- {
- last_offset += 4;
- if (INTVAL (curr_offset) != last_offset)
- return false;
- }
- }
- if (last_offset < 0 || last_offset + 4 != INTVAL (offset))
- return false;
-
- return true;
-}
-
-
-/* Masks of registers that are valid for CDX ldwm/stwm instructions.
- The instruction can encode subsets drawn from either R2-R13 or
- R14-R23 + FP + RA. */
-#define CDX_LDSTWM_VALID_REGS_0 0x00003ffc
-#define CDX_LDSTWM_VALID_REGS_1 0x90ffc000
-
-static bool
-nios2_ldstwm_regset_p (unsigned int regno, unsigned int *regset)
-{
- if (*regset == 0)
- {
- if (CDX_LDSTWM_VALID_REGS_0 & (1 << regno))
- *regset = CDX_LDSTWM_VALID_REGS_0;
- else if (CDX_LDSTWM_VALID_REGS_1 & (1 << regno))
- *regset = CDX_LDSTWM_VALID_REGS_1;
- else
- return false;
- return true;
- }
- else
- return (*regset & (1 << regno)) != 0;
-}
-
-/* Main function to implement ldwm_operation/stwm_operation
- predicates that check ldwm/stwm insn pattern integrity. */
-bool
-ldstwm_operation_p (rtx op, bool load_p)
-{
- int start, i, end = XVECLEN (op, 0) - 1, last_regno = -1;
- unsigned int regset = 0;
- rtx base_reg, offset;
- rtx first_elt = XVECEXP (op, 0, 0);
- bool inc_p = true;
- bool wb_p = base_reg_adjustment_p (first_elt, &base_reg, &offset);
- if (GET_CODE (XVECEXP (op, 0, end)) == RETURN)
- end--;
- start = wb_p ? 1 : 0;
- for (i = start; i <= end; i++)
- {
- int regno;
- rtx reg, mem, elt = XVECEXP (op, 0, i);
- /* Return early if not a SET at all. */
- if (GET_CODE (elt) != SET)
- return false;
- reg = load_p ? SET_DEST (elt) : SET_SRC (elt);
- mem = load_p ? SET_SRC (elt) : SET_DEST (elt);
- if (!REG_P (reg) || !MEM_P (mem))
- return false;
- regno = REGNO (reg);
- if (!nios2_ldstwm_regset_p (regno, ®set))
- return false;
- /* If no writeback to determine direction, use offset of first MEM. */
- if (wb_p)
- inc_p = INTVAL (offset) > 0;
- else if (i == start)
- {
- rtx first_base, first_offset;
- if (!split_mem_address (XEXP (mem, 0),
- &first_base, &first_offset))
- return false;
- if (!REG_P (first_base) || !CONST_INT_P (first_offset))
- return false;
- base_reg = first_base;
- inc_p = INTVAL (first_offset) >= 0;
- }
- /* Ensure that the base register is not loaded into. */
- if (load_p && regno == (int) REGNO (base_reg))
- return false;
- /* Check for register order inc/dec integrity. */
- if (last_regno >= 0)
- {
- if (inc_p && last_regno >= regno)
- return false;
- if (!inc_p && last_regno <= regno)
- return false;
- }
- last_regno = regno;
- }
- return true;
-}
-
-/* Helper for nios2_ldst_parallel, for generating a parallel vector
- SET element. */
-static rtx
-gen_ldst (bool load_p, int regno, rtx base_mem, int offset)
-{
- rtx reg = gen_rtx_REG (SImode, regno);
- rtx mem = adjust_address_nv (base_mem, SImode, offset);
- return gen_rtx_SET (load_p ? reg : mem,
- load_p ? mem : reg);
-}
-
-/* A general routine for creating the body RTL pattern of
- ldwm/stwm/push.n/pop.n insns.
- LOAD_P: true/false for load/store direction.
- REG_INC_P: whether registers are incrementing/decrementing in the
- *RTL vector* (not necessarily the order defined in the ISA specification).
- OFFSET_INC_P: Same as REG_INC_P, but for the memory offset order.
- BASE_MEM: starting MEM.
- BASE_UPDATE: amount to update base register; zero means no writeback.
- REGMASK: register mask to load/store.
- RET_P: true if to tag a (return) element at the end.
-
- Note that this routine does not do any checking. It's the job of the
- caller to do the right thing, and the insn patterns to do the
- safe-guarding. */
-static rtx
-nios2_ldst_parallel (bool load_p, bool reg_inc_p, bool offset_inc_p,
- rtx base_mem, int base_update,
- unsigned HOST_WIDE_INT regmask, bool ret_p)
-{
- rtvec p;
- int regno, b = 0, i = 0, n = 0, len = popcount_hwi (regmask);
- if (ret_p) len++, i++, b++;
- if (base_update != 0) len++, i++;
- p = rtvec_alloc (len);
- for (regno = (reg_inc_p ? 0 : 31);
- regno != (reg_inc_p ? 32 : -1);
- regno += (reg_inc_p ? 1 : -1))
- if ((regmask & (1 << regno)) != 0)
- {
- int offset = (offset_inc_p ? 4 : -4) * n++;
- RTVEC_ELT (p, i++) = gen_ldst (load_p, regno, base_mem, offset);
- }
- if (ret_p)
- RTVEC_ELT (p, 0) = ret_rtx;
- if (base_update != 0)
- {
- rtx reg, offset;
- if (!split_mem_address (XEXP (base_mem, 0), ®, &offset))
- gcc_unreachable ();
- RTVEC_ELT (p, b) =
- gen_rtx_SET (reg, plus_constant (Pmode, reg, base_update));
- }
- return gen_rtx_PARALLEL (VOIDmode, p);
-}
-
-/* CDX ldwm/stwm peephole optimization pattern related routines. */
-
-/* Data structure and sorting function for ldwm/stwm peephole optimizers. */
-struct ldstwm_operand
-{
- int offset; /* Offset from base register. */
- rtx reg; /* Register to store at this offset. */
- rtx mem; /* Original mem. */
- bool bad; /* True if this load/store can't be combined. */
- bool rewrite; /* True if we should rewrite using scratch. */
-};
-
-static int
-compare_ldstwm_operands (const void *arg1, const void *arg2)
-{
- const struct ldstwm_operand *op1 = (const struct ldstwm_operand *) arg1;
- const struct ldstwm_operand *op2 = (const struct ldstwm_operand *) arg2;
- if (op1->bad)
- return op2->bad ? 0 : 1;
- else if (op2->bad)
- return -1;
- else
- return op1->offset - op2->offset;
-}
-
-/* Helper function: return true if a load/store using REGNO with address
- BASEREG and offset OFFSET meets the constraints for a 2-byte CDX ldw.n,
- stw.n, ldwsp.n, or stwsp.n instruction. */
-static bool
-can_use_cdx_ldstw (int regno, int basereg, int offset)
-{
- if (CDX_REG_P (regno) && CDX_REG_P (basereg)
- && (offset & 0x3) == 0 && offset >= 0 && offset < 0x40)
- return true;
- else if (basereg == SP_REGNO
- && offset >= 0 && offset < 0x80 && (offset & 0x3) == 0)
- return true;
- return false;
-}
-
-/* This function is called from peephole2 optimizers to try to merge
- a series of individual loads and stores into a ldwm or stwm. It
- can also rewrite addresses inside the individual loads and stores
- using a common base register using a scratch register and smaller
- offsets if that allows them to use CDX ldw.n or stw.n instructions
- instead of 4-byte loads or stores.
- N is the number of insns we are trying to merge. SCRATCH is non-null
- if there is a scratch register available. The OPERANDS array contains
- alternating REG (even) and MEM (odd) operands. */
-bool
-gen_ldstwm_peep (bool load_p, int n, rtx scratch, rtx *operands)
-{
- /* CDX ldwm/stwm instructions allow a maximum of 12 registers to be
- specified. */
-#define MAX_LDSTWM_OPS 12
- struct ldstwm_operand sort[MAX_LDSTWM_OPS];
- int basereg = -1;
- int baseoffset;
- int i, m, lastoffset, lastreg;
- unsigned int regmask = 0, usemask = 0, regset;
- bool needscratch;
- int newbasereg;
- int nbytes;
-
- if (!TARGET_HAS_CDX)
- return false;
- if (n < 2 || n > MAX_LDSTWM_OPS)
- return false;
-
- /* Check all the operands for validity and initialize the sort array.
- The places where we return false here are all situations that aren't
- expected to ever happen -- invalid patterns, invalid registers, etc. */
- for (i = 0; i < n; i++)
- {
- rtx base, offset;
- rtx reg = operands[i];
- rtx mem = operands[i + n];
- int r, o, regno;
- bool bad = false;
-
- if (!REG_P (reg) || !MEM_P (mem))
- return false;
-
- regno = REGNO (reg);
- if (regno > 31)
- return false;
- if (load_p && (regmask & (1 << regno)) != 0)
- return false;
- regmask |= 1 << regno;
-
- if (!split_mem_address (XEXP (mem, 0), &base, &offset))
- return false;
- r = REGNO (base);
- o = INTVAL (offset);
-
- if (basereg == -1)
- basereg = r;
- else if (r != basereg)
- bad = true;
- usemask |= 1 << r;
-
- sort[i].bad = bad;
- sort[i].rewrite = false;
- sort[i].offset = o;
- sort[i].reg = reg;
- sort[i].mem = mem;
- }
-
- /* If we are doing a series of register loads, we can't safely reorder
- them if any of the regs used in addr expressions are also being set. */
- if (load_p && (regmask & usemask))
- return false;
-
- /* Sort the array by increasing mem offset order, then check that
- offsets are valid and register order matches mem order. At the
- end of this loop, m is the number of loads/stores we will try to
- combine; the rest are leftovers. */
- qsort (sort, n, sizeof (struct ldstwm_operand), compare_ldstwm_operands);
-
- baseoffset = sort[0].offset;
- needscratch = baseoffset != 0;
- if (needscratch && !scratch)
- return false;
-
- lastreg = regmask = regset = 0;
- lastoffset = baseoffset;
- for (m = 0; m < n && !sort[m].bad; m++)
- {
- int thisreg = REGNO (sort[m].reg);
- if (sort[m].offset != lastoffset
- || (m > 0 && lastreg >= thisreg)
- || !nios2_ldstwm_regset_p (thisreg, ®set))
- break;
- lastoffset += 4;
- lastreg = thisreg;
- regmask |= (1 << thisreg);
- }
-
- /* For loads, make sure we are not overwriting the scratch reg.
- The peephole2 pattern isn't supposed to match unless the register is
- unused all the way through, so this isn't supposed to happen anyway. */
- if (load_p
- && needscratch
- && ((1 << REGNO (scratch)) & regmask) != 0)
- return false;
- newbasereg = needscratch ? (int) REGNO (scratch) : basereg;
-
- /* We may be able to combine only the first m of the n total loads/stores
- into a single instruction. If m < 2, there's no point in emitting
- a ldwm/stwm at all, but we might be able to do further optimizations
- if we have a scratch. We will count the instruction lengths of the
- old and new patterns and store the savings in nbytes. */
- if (m < 2)
- {
- if (!needscratch)
- return false;
- m = 0;
- nbytes = 0;
- }
- else
- nbytes = -4; /* Size of ldwm/stwm. */
- if (needscratch)
- {
- int bo = baseoffset > 0 ? baseoffset : -baseoffset;
- if (CDX_REG_P (newbasereg)
- && CDX_REG_P (basereg)
- && bo <= 128 && bo > 0 && (bo & (bo - 1)) == 0)
- nbytes -= 2; /* Size of addi.n/subi.n. */
- else
- nbytes -= 4; /* Size of non-CDX addi. */
- }
-
- /* Count the size of the input load/store instructions being replaced. */
- for (i = 0; i < m; i++)
- if (can_use_cdx_ldstw (REGNO (sort[i].reg), basereg, sort[i].offset))
- nbytes += 2;
- else
- nbytes += 4;
-
- /* We may also be able to save a bit if we can rewrite non-CDX
- load/stores that can't be combined into the ldwm/stwm into CDX
- load/stores using the scratch reg. For example, this might happen
- if baseoffset is large, by bringing in the offsets in the load/store
- instructions within the range that fits in the CDX instruction. */
- if (needscratch && CDX_REG_P (newbasereg))
- for (i = m; i < n && !sort[i].bad; i++)
- if (!can_use_cdx_ldstw (REGNO (sort[i].reg), basereg, sort[i].offset)
- && can_use_cdx_ldstw (REGNO (sort[i].reg), newbasereg,
- sort[i].offset - baseoffset))
- {
- sort[i].rewrite = true;
- nbytes += 2;
- }
-
- /* Are we good to go? */
- if (nbytes <= 0)
- return false;
-
- /* Emit the scratch load. */
- if (needscratch)
- emit_insn (gen_rtx_SET (scratch, XEXP (sort[0].mem, 0)));
-
- /* Emit the ldwm/stwm insn. */
- if (m > 0)
- {
- rtvec p = rtvec_alloc (m);
- for (i = 0; i < m; i++)
- {
- int offset = sort[i].offset;
- rtx mem, reg = sort[i].reg;
- rtx base_reg = gen_rtx_REG (Pmode, newbasereg);
- if (needscratch)
- offset -= baseoffset;
- mem = gen_rtx_MEM (SImode, plus_constant (Pmode, base_reg, offset));
- if (load_p)
- RTVEC_ELT (p, i) = gen_rtx_SET (reg, mem);
- else
- RTVEC_ELT (p, i) = gen_rtx_SET (mem, reg);
- }
- emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
- }
-
- /* Emit any leftover load/stores as individual instructions, doing
- the previously-noted rewrites to use the scratch reg. */
- for (i = m; i < n; i++)
- {
- rtx reg = sort[i].reg;
- rtx mem = sort[i].mem;
- if (sort[i].rewrite)
- {
- int offset = sort[i].offset - baseoffset;
- mem = gen_rtx_MEM (SImode, plus_constant (Pmode, scratch, offset));
- }
- if (load_p)
- emit_move_insn (reg, mem);
- else
- emit_move_insn (mem, reg);
- }
- return true;
-}
-
-/* Implement TARGET_MACHINE_DEPENDENT_REORG:
- We use this hook when emitting CDX code to enforce the 4-byte
- alignment requirement for labels that are used as the targets of
- jmpi instructions. CDX code can otherwise contain a mix of 16-bit
- and 32-bit instructions aligned on any 16-bit boundary, but functions
- and jmpi labels have to be 32-bit aligned because of the way the address
- is encoded in the instruction. */
-
-static unsigned char *label_align;
-static int min_labelno, max_labelno;
-
-static void
-nios2_reorg (void)
-{
- bool changed = true;
- rtx_insn *insn;
-
- if (!TARGET_HAS_CDX)
- return;
-
- /* Initialize the data structures. */
- if (label_align)
- free (label_align);
- max_labelno = max_label_num ();
- min_labelno = get_first_label_num ();
- label_align = XCNEWVEC (unsigned char, max_labelno - min_labelno + 1);
-
- /* Iterate on inserting alignment and adjusting branch lengths until
- no more changes. */
- while (changed)
- {
- changed = false;
- shorten_branches (get_insns ());
-
- for (insn = get_insns (); insn != 0; insn = NEXT_INSN (insn))
- if (JUMP_P (insn) && insn_variable_length_p (insn))
- {
- rtx label = JUMP_LABEL (insn);
- /* We use the current fact that all cases of 'jmpi'
- doing the actual branch in the machine description
- has a computed length of 6 or 8. Length 4 and below
- are all PC-relative 'br' branches without the jump-align
- problem. */
- if (label && LABEL_P (label) && get_attr_length (insn) > 4)
- {
- int index = CODE_LABEL_NUMBER (label) - min_labelno;
- if (label_align[index] != 2)
- {
- label_align[index] = 2;
- changed = true;
- }
- }
- }
- }
-}
-
-/* Implement LABEL_ALIGN, using the information gathered in nios2_reorg. */
-int
-nios2_label_align (rtx label)
-{
- int n = CODE_LABEL_NUMBER (label);
-
- if (label_align && n >= min_labelno && n <= max_labelno)
- return MAX (label_align[n - min_labelno], align_labels.levels[0].log);
- return align_labels.levels[0].log;
-}
-
-/* Implement ADJUST_REG_ALLOC_ORDER. We use the default ordering
- for R1 and non-CDX R2 code; for CDX we tweak thing to prefer
- the registers that can be used as operands to instructions that
- have 3-bit register fields. */
-void
-nios2_adjust_reg_alloc_order (void)
-{
- const int cdx_reg_alloc_order[] =
- {
- /* Call-clobbered GPRs within CDX 3-bit encoded range. */
- 2, 3, 4, 5, 6, 7,
- /* Call-saved GPRs within CDX 3-bit encoded range. */
- 16, 17,
- /* Other call-clobbered GPRs. */
- 8, 9, 10, 11, 12, 13, 14, 15,
- /* Other call-saved GPRs. RA placed first since it is always saved. */
- 31, 18, 19, 20, 21, 22, 23, 28,
- /* Fixed GPRs, not used by the register allocator. */
- 0, 1, 24, 25, 26, 27, 29, 30, 32, 33, 34, 35, 36, 37, 38, 39
- };
-
- if (TARGET_HAS_CDX)
- memcpy (reg_alloc_order, cdx_reg_alloc_order,
- sizeof (int) * FIRST_PSEUDO_REGISTER);
-}
-
-
-/* Initialize the GCC target structure. */
-#undef TARGET_ASM_FUNCTION_PROLOGUE
-#define TARGET_ASM_FUNCTION_PROLOGUE nios2_asm_function_prologue
-
-#undef TARGET_IN_SMALL_DATA_P
-#define TARGET_IN_SMALL_DATA_P nios2_in_small_data_p
-
-#undef TARGET_SECTION_TYPE_FLAGS
-#define TARGET_SECTION_TYPE_FLAGS nios2_section_type_flags
-
-#undef TARGET_INIT_BUILTINS
-#define TARGET_INIT_BUILTINS nios2_init_builtins
-#undef TARGET_EXPAND_BUILTIN
-#define TARGET_EXPAND_BUILTIN nios2_expand_builtin
-#undef TARGET_BUILTIN_DECL
-#define TARGET_BUILTIN_DECL nios2_builtin_decl
-
-#undef TARGET_FUNCTION_OK_FOR_SIBCALL
-#define TARGET_FUNCTION_OK_FOR_SIBCALL hook_bool_tree_tree_true
-
-#undef TARGET_CAN_ELIMINATE
-#define TARGET_CAN_ELIMINATE nios2_can_eliminate
-
-#undef TARGET_FUNCTION_ARG
-#define TARGET_FUNCTION_ARG nios2_function_arg
-
-#undef TARGET_FUNCTION_ARG_ADVANCE
-#define TARGET_FUNCTION_ARG_ADVANCE nios2_function_arg_advance
-
-#undef TARGET_FUNCTION_ARG_PADDING
-#define TARGET_FUNCTION_ARG_PADDING nios2_function_arg_padding
-
-#undef TARGET_ARG_PARTIAL_BYTES
-#define TARGET_ARG_PARTIAL_BYTES nios2_arg_partial_bytes
-
-#undef TARGET_TRAMPOLINE_INIT
-#define TARGET_TRAMPOLINE_INIT nios2_trampoline_init
-
-#undef TARGET_FUNCTION_VALUE
-#define TARGET_FUNCTION_VALUE nios2_function_value
-
-#undef TARGET_LIBCALL_VALUE
-#define TARGET_LIBCALL_VALUE nios2_libcall_value
-
-#undef TARGET_FUNCTION_VALUE_REGNO_P
-#define TARGET_FUNCTION_VALUE_REGNO_P nios2_function_value_regno_p
-
-#undef TARGET_RETURN_IN_MEMORY
-#define TARGET_RETURN_IN_MEMORY nios2_return_in_memory
-
-#undef TARGET_PROMOTE_PROTOTYPES
-#define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
-
-#undef TARGET_SETUP_INCOMING_VARARGS
-#define TARGET_SETUP_INCOMING_VARARGS nios2_setup_incoming_varargs
-
-#undef TARGET_MUST_PASS_IN_STACK
-#define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
-
-#undef TARGET_LEGITIMATE_CONSTANT_P
-#define TARGET_LEGITIMATE_CONSTANT_P nios2_legitimate_constant_p
-
-#undef TARGET_LEGITIMIZE_ADDRESS
-#define TARGET_LEGITIMIZE_ADDRESS nios2_legitimize_address
-
-#undef TARGET_DELEGITIMIZE_ADDRESS
-#define TARGET_DELEGITIMIZE_ADDRESS nios2_delegitimize_address
-
-#undef TARGET_LEGITIMATE_ADDRESS_P
-#define TARGET_LEGITIMATE_ADDRESS_P nios2_legitimate_address_p
-
-#undef TARGET_PREFERRED_RELOAD_CLASS
-#define TARGET_PREFERRED_RELOAD_CLASS nios2_preferred_reload_class
-
-#undef TARGET_RTX_COSTS
-#define TARGET_RTX_COSTS nios2_rtx_costs
-
-#undef TARGET_ADDRESS_COST
-#define TARGET_ADDRESS_COST nios2_address_cost
-
-#undef TARGET_HAVE_TLS
-#define TARGET_HAVE_TLS TARGET_LINUX_ABI
-
-#undef TARGET_CANNOT_FORCE_CONST_MEM
-#define TARGET_CANNOT_FORCE_CONST_MEM nios2_cannot_force_const_mem
-
-#undef TARGET_ASM_OUTPUT_DWARF_DTPREL
-#define TARGET_ASM_OUTPUT_DWARF_DTPREL nios2_output_dwarf_dtprel
-
-#undef TARGET_PRINT_OPERAND_PUNCT_VALID_P
-#define TARGET_PRINT_OPERAND_PUNCT_VALID_P nios2_print_operand_punct_valid_p
-
-#undef TARGET_PRINT_OPERAND
-#define TARGET_PRINT_OPERAND nios2_print_operand
-
-#undef TARGET_PRINT_OPERAND_ADDRESS
-#define TARGET_PRINT_OPERAND_ADDRESS nios2_print_operand_address
-
-#undef TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA
-#define TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA nios2_output_addr_const_extra
-
-#undef TARGET_ASM_FILE_END
-#define TARGET_ASM_FILE_END nios2_asm_file_end
-
-#undef TARGET_OPTION_OVERRIDE
-#define TARGET_OPTION_OVERRIDE nios2_option_override
-
-#undef TARGET_OPTION_SAVE
-#define TARGET_OPTION_SAVE nios2_option_save
-
-#undef TARGET_OPTION_RESTORE
-#define TARGET_OPTION_RESTORE nios2_option_restore
-
-#undef TARGET_CAN_INLINE_P
-#define TARGET_CAN_INLINE_P nios2_can_inline_p
-
-#undef TARGET_SET_CURRENT_FUNCTION
-#define TARGET_SET_CURRENT_FUNCTION nios2_set_current_function
-
-#undef TARGET_OPTION_VALID_ATTRIBUTE_P
-#define TARGET_OPTION_VALID_ATTRIBUTE_P nios2_valid_target_attribute_p
-
-#undef TARGET_OPTION_PRAGMA_PARSE
-#define TARGET_OPTION_PRAGMA_PARSE nios2_pragma_target_parse
-
-#undef TARGET_MERGE_DECL_ATTRIBUTES
-#define TARGET_MERGE_DECL_ATTRIBUTES nios2_merge_decl_attributes
-
-#undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
-#define TARGET_ASM_CAN_OUTPUT_MI_THUNK \
- hook_bool_const_tree_hwi_hwi_const_tree_true
-
-#undef TARGET_ASM_OUTPUT_MI_THUNK
-#define TARGET_ASM_OUTPUT_MI_THUNK nios2_asm_output_mi_thunk
-
-#undef TARGET_MACHINE_DEPENDENT_REORG
-#define TARGET_MACHINE_DEPENDENT_REORG nios2_reorg
-
-#undef TARGET_CONSTANT_ALIGNMENT
-#define TARGET_CONSTANT_ALIGNMENT constant_alignment_word_strings
-
-#undef TARGET_HAVE_SPECULATION_SAFE_VALUE
-#define TARGET_HAVE_SPECULATION_SAFE_VALUE speculation_safe_value_not_needed
-
-struct gcc_target targetm = TARGET_INITIALIZER;
-
-#include "gt-nios2.h"
diff --git a/gcc/config/nios2/nios2.h b/gcc/config/nios2/nios2.h
deleted file mode 100644
index 88ad1667bc25..000000000000
--- a/gcc/config/nios2/nios2.h
+++ /dev/null
@@ -1,540 +0,0 @@
-/* Definitions of target machine for Altera Nios II.
- Copyright (C) 2012-2024 Free Software Foundation, Inc.
- Contributed by Jonah Graham (jgraham@altera.com),
- Will Reece (wreece@altera.com), and Jeff DaSilva (jdasilva@altera.com).
- Contributed by Mentor Graphics, Inc.
-
- This file is part of GCC.
-
- GCC is free software; you can redistribute it and/or modify it
- under the terms of the GNU General Public License as published
- by the Free Software Foundation; either version 3, or (at your
- option) any later version.
-
- GCC is distributed in the hope that it will be useful, but WITHOUT
- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
- License for more details.
-
- You should have received a copy of the GNU General Public License
- along with GCC; see the file COPYING3. If not see
- <http://www.gnu.org/licenses/>. */
-
-#ifndef GCC_NIOS2_H
-#define GCC_NIOS2_H
-
-/* Indicate R2 ISA level support. */
-#define TARGET_ARCH_R2 (nios2_arch_option == ARCH_R2)
-
-/* FPU insn codes declared here. */
-#include "config/nios2/nios2-opts.h"
-
-/* Define built-in preprocessor macros. */
-#define TARGET_CPU_CPP_BUILTINS() \
- do \
- { \
- builtin_define_std ("NIOS2"); \
- builtin_define_std ("nios2"); \
- if (TARGET_BIG_ENDIAN) \
- builtin_define_std ("nios2_big_endian"); \
- else \
- builtin_define_std ("nios2_little_endian"); \
- builtin_define_with_int_value ( \
- "__nios2_arch__", (int) nios2_arch_option); \
- } \
- while (0)
-
-/* We're little endian, unless otherwise specified by defining
- BIG_ENDIAN_FLAG. */
-#ifndef TARGET_ENDIAN_DEFAULT
-# define TARGET_ENDIAN_DEFAULT 0
-#endif
-
-/* Default target_flags if no switches specified. */
-#ifndef TARGET_DEFAULT
-# define TARGET_DEFAULT (MASK_HAS_MUL | TARGET_ENDIAN_DEFAULT)
-#endif
-
-#define OPTION_DEFAULT_SPECS \
- {"arch", "%{!march=*:%{!mcpu=*:-march=%(VALUE)}}" }
-
-#define CC1_SPEC "%{G*}"
-
-#if TARGET_ENDIAN_DEFAULT == 0
-# define ASM_SPEC "%{!meb:-EL} %{meb:-EB} %{march=*:-march=%*}"
-# define LINK_SPEC_ENDIAN "%{!meb:-EL} %{meb:-EB}"
-# define MULTILIB_DEFAULTS { "EL" }
-#else
-# define ASM_SPEC "%{!mel:-EB} %{mel:-EL} %{march=*:-march=%*}"
-# define LINK_SPEC_ENDIAN "%{!mel:-EB} %{mel:-EL}"
-# define MULTILIB_DEFAULTS { "EB" }
-#endif
-
-#define LINK_SPEC LINK_SPEC_ENDIAN \
- " %{shared:-shared} \
- %{static:-Bstatic}"
-
-
-/* Storage layout. */
-
-#define DEFAULT_SIGNED_CHAR 1
-#define BITS_BIG_ENDIAN 0
-#define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
-#define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
-#define BITS_PER_WORD 32
-#define UNITS_PER_WORD 4
-#define POINTER_SIZE 32
-#define BIGGEST_ALIGNMENT 32
-#define STRICT_ALIGNMENT 1
-#define FUNCTION_BOUNDARY 32
-#define PARM_BOUNDARY 32
-#define STACK_BOUNDARY 32
-#define PREFERRED_STACK_BOUNDARY 32
-#define MAX_FIXED_MODE_SIZE 64
-
-#define LABEL_ALIGN(LABEL) nios2_label_align (LABEL)
-
-/* Layout of source language data types. */
-
-#define INT_TYPE_SIZE 32
-#define SHORT_TYPE_SIZE 16
-#define LONG_TYPE_SIZE 32
-#define LONG_LONG_TYPE_SIZE 64
-
-#undef SIZE_TYPE
-#define SIZE_TYPE "unsigned int"
-
-#undef PTRDIFF_TYPE
-#define PTRDIFF_TYPE "int"
-
-
-/* Basic characteristics of Nios II registers:
-
- Regno Name
- 0 r0 zero always zero
- 1 r1 at Assembler Temporary
- 2-3 r2-r3 Return Location
- 4-7 r4-r7 Register Arguments
- 8-15 r8-r15 Caller Saved Registers
- 16-22 r16-r22 Callee Saved Registers
- 22 r22 Global Offset Table pointer (Linux ABI only)
- 23 r23 Thread pointer (Linux ABI only)
- 24 r24 et Exception Temporary
- 25 r25 bt Breakpoint Temporary
- 26 r26 gp Global Pointer
- 27 r27 sp Stack Pointer
- 28 r28 fp Frame Pointer
- 29 r29 ea Exception Return Address
- 30 r30 ba Breakpoint Return Address
- 31 r31 ra Return Address
-
- 32 ctl0 status
- 33 ctl1 estatus STATUS saved by exception
- 34 ctl2 bstatus STATUS saved by break
- 35 ctl3 ipri Interrupt Priority Mask
- 36 ctl4 ecause Exception Cause
-
- 37 pc Not an actual register
-
- 38 fake_fp Fake Frame Pointer (always eliminated)
- 39 fake_ap Fake Argument Pointer (always eliminated)
- 40 First Pseudo Register
-
- In addition, r12 is used as the static chain register and r13, r14, and r15
- are clobbered by PLT code sequences.
-
- The definitions for all the hard register numbers are located in nios2.md.
-*/
-
-#define FIXED_REGISTERS \
- { \
-/* +0 1 2 3 4 5 6 7 8 9 */ \
-/* 0 */ 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, \
-/* 10 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-/* 20 */ 0, 0, TARGET_LINUX_ABI, TARGET_LINUX_ABI, 1, 1, 1, 1, 0, 1, \
-/* 30 */ 1, 0, 1, 1, 1, 1, 1, 1, 1, 1, \
- }
-
-/* Call used == caller saved + fixed regs + args + ret vals. */
-#define CALL_USED_REGISTERS \
- { \
-/* +0 1 2 3 4 5 6 7 8 9 */ \
-/* 0 */ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
-/* 10 */ 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, \
-/* 20 */ 0, 0, TARGET_LINUX_ABI, TARGET_LINUX_ABI, 1, 1, 1, 1, 0, 1, \
-/* 30 */ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
- }
-
-/* Order in which to allocate registers. Each register must be
- listed once. This is the default ordering for R1 and non-CDX R2
- code. For CDX, we overwrite this in ADJUST_REG_ALLOC_ORDER. */
-#define REG_ALLOC_ORDER \
- { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, \
- 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, \
- 37, 38, 39 }
-
-#define ADJUST_REG_ALLOC_ORDER nios2_adjust_reg_alloc_order ()
-
-/* Caller-save costs can be less emphasized under R2 CDX, where we can
- use push.n/pop.n. */
-#define HONOR_REG_ALLOC_ORDER (TARGET_HAS_CDX)
-
-/* Register Classes. */
-
-enum reg_class
-{
- NO_REGS,
- SIB_REGS,
- IJMP_REGS,
- GP_REGS,
- ALL_REGS,
- LIM_REG_CLASSES
-};
-
-#define N_REG_CLASSES (int) LIM_REG_CLASSES
-
-#define REG_CLASS_NAMES \
- { "NO_REGS", \
- "SIB_REGS", \
- "IJMP_REGS", \
- "GP_REGS", \
- "ALL_REGS" }
-
-#define GENERAL_REGS ALL_REGS
-
-#define REG_CLASS_CONTENTS \
- { \
- /* NO_REGS */ { 0, 0}, \
- /* SIB_REGS */ { 0xfe0c, 0}, \
- /* IJMP_REGS */ { 0x7fffffff, 0}, \
- /* GP_REGS */ {~0, 0}, \
- /* ALL_REGS */ {~0,~0} \
- }
-
-
-#define GP_REG_P(REGNO) ((unsigned)(REGNO) <= LAST_GP_REG)
-#define REGNO_REG_CLASS(REGNO) (GP_REG_P (REGNO) ? GP_REGS : ALL_REGS)
-#define CLASS_MAX_NREGS(CLASS, MODE) \
- ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
-
-#define CDX_REG_P(REGNO) \
- ((REGNO) == 16 || (REGNO) == 17 || ((REGNO) >= 2 && (REGNO) <= 7))
-
-/* Tests for various kinds of constants used in the Nios II port. */
-
-#define SMALL_INT(X) ((unsigned HOST_WIDE_INT)(X) + 0x8000 < 0x10000)
-#define SMALL_INT12(X) ((unsigned HOST_WIDE_INT)(X) + 0x800 < 0x1000)
-#define SMALL_INT_UNSIGNED(X) ((X) >= 0 && (X) < 0x10000)
-#define UPPER16_INT(X) (((X) & 0xffff) == 0)
-#define SHIFT_INT(X) ((X) >= 0 && (X) <= 31)
-#define RDWRCTL_INT(X) ((X) >= 0 && (X) <= 31)
-#define CUSTOM_INSN_OPCODE(X) ((X) >= 0 && (X) <= 255)
-#define ANDCLEAR_INT(X) \
- (((X) & 0xffff) == 0xffff || (((X) >> 16) & 0xffff) == 0xffff)
-
-/* Say that the epilogue uses the return address register. Note that
- in the case of sibcalls, the values "used by the epilogue" are
- considered live at the start of the called function. */
-#define EPILOGUE_USES(REGNO) (epilogue_completed && (REGNO) == RA_REGNO)
-
-/* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
- the stack pointer does not matter. The value is tested only in
- functions that have frame pointers.
- No definition is equivalent to always zero. */
-
-#define EXIT_IGNORE_STACK 1
-
-/* Trampolines use a 5-instruction sequence. */
-#define TRAMPOLINE_SIZE 20
-
-/* Stack layout. */
-#define STACK_GROWS_DOWNWARD 1
-#define FRAME_GROWS_DOWNWARD 1
-#define FIRST_PARM_OFFSET(FUNDECL) 0
-
-/* Before the prologue, RA lives in r31. */
-#define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, RA_REGNO)
-#define RETURN_ADDR_RTX(C,F) nios2_get_return_address (C)
-
-#define DWARF_FRAME_RETURN_COLUMN RA_REGNO
-
-/* The CFA includes the pretend args. */
-#define ARG_POINTER_CFA_OFFSET(FNDECL) \
- (gcc_assert ((FNDECL) == current_function_decl), \
- FIRST_PARM_OFFSET (FNDECL) + crtl->args.pretend_args_size)
-
-/* Frame/arg pointer elimination settings. */
-#define ELIMINABLE_REGS \
-{{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
- { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
- { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
- { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}}
-
-#define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
- (OFFSET) = nios2_initial_elimination_offset ((FROM), (TO))
-
-/* Calling convention definitions. */
-typedef struct nios2_args
-{
- int regs_used;
-} CUMULATIVE_ARGS;
-
-#define NUM_ARG_REGS (LAST_ARG_REGNO - FIRST_ARG_REGNO + 1)
-
-#define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \
- do { (CUM).regs_used = 0; } while (0)
-
-#define PAD_VARARGS_DOWN \
- (targetm.calls.function_arg_padding (TYPE_MODE (type), type) == PAD_DOWNWARD)
-
-#define BLOCK_REG_PADDING(MODE, TYPE, FIRST) \
- (nios2_block_reg_padding ((MODE), (TYPE), (FIRST)))
-
-#define FUNCTION_ARG_REGNO_P(REGNO) \
- ((REGNO) >= FIRST_ARG_REGNO && (REGNO) <= LAST_ARG_REGNO)
-
-/* Passing function arguments on stack. */
-#define ACCUMULATE_OUTGOING_ARGS 1
-
-/* We define TARGET_RETURN_IN_MEMORY, so set to zero. */
-#define DEFAULT_PCC_STRUCT_RETURN 0
-
-/* Profiling. */
-#define PROFILE_BEFORE_PROLOGUE
-#define NO_PROFILE_COUNTERS 1
-#define FUNCTION_PROFILER(FILE, LABELNO) \
- nios2_function_profiler ((FILE), (LABELNO))
-
-/* Addressing modes. */
-
-#define CONSTANT_ADDRESS_P(X) \
- (CONSTANT_P (X) && memory_address_p (SImode, X))
-
-#define MAX_REGS_PER_ADDRESS 1
-#define BASE_REG_CLASS ALL_REGS
-#define INDEX_REG_CLASS NO_REGS
-
-#define REGNO_OK_FOR_BASE_P(REGNO) nios2_regno_ok_for_base_p ((REGNO), true)
-#define REGNO_OK_FOR_INDEX_P(REGNO) 0
-
-/* Describing Relative Costs of Operations. */
-#define MOVE_MAX 4
-#define SLOW_BYTE_ACCESS 1
-
-/* It is as good to call a constant function address as to call an address
- kept in a register. */
-#define NO_FUNCTION_CSE 1
-
-/* Position independent code. */
-
-#define PIC_OFFSET_TABLE_REGNUM 22
-#define LEGITIMATE_PIC_OPERAND_P(X) nios2_legitimate_pic_operand_p (X)
-
-/* Define output assembler language. */
-
-#define ASM_APP_ON "#APP\n"
-#define ASM_APP_OFF "#NO_APP\n"
-
-#define ASM_COMMENT_START "# "
-
-#define GLOBAL_ASM_OP "\t.global\t"
-
-#define REGISTER_NAMES \
- { \
- "zero", \
- "at", \
- "r2", \
- "r3", \
- "r4", \
- "r5", \
- "r6", \
- "r7", \
- "r8", \
- "r9", \
- "r10", \
- "r11", \
- "r12", \
- "r13", \
- "r14", \
- "r15", \
- "r16", \
- "r17", \
- "r18", \
- "r19", \
- "r20", \
- "r21", \
- "r22", \
- "r23", \
- "et", \
- "bt", \
- "gp", \
- "sp", \
- "fp", \
- "ta", \
- "ba", \
- "ra", \
- "status", \
- "estatus", \
- "bstatus", \
- "ipri", \
- "ecause", \
- "pc", \
- "fake_fp", \
- "fake_ap", \
-}
-
-#define ADDITIONAL_REGISTER_NAMES \
-{ \
- {"r0", 0}, \
- {"r1", 1}, \
- {"r24", 24}, \
- {"r25", 25}, \
- {"r26", 26}, \
- {"r27", 27}, \
- {"r28", 28}, \
- {"r29", 29}, \
- {"r30", 30}, \
- {"r31", 31} \
-}
-
-#define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
- do \
- { \
- fputs (integer_asm_op (POINTER_SIZE / BITS_PER_UNIT, TRUE), FILE); \
- fprintf (FILE, ".L%u\n", (unsigned) (VALUE)); \
- } \
- while (0)
-
-#define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL)\
- do \
- { \
- fputs (integer_asm_op (POINTER_SIZE / BITS_PER_UNIT, TRUE), STREAM); \
- fprintf (STREAM, ".L%u-.L%u\n", (unsigned) (VALUE), (unsigned) (REL)); \
- } \
- while (0)
-
-/* Section directives. */
-
-/* Output before read-only data. */
-#define TEXT_SECTION_ASM_OP "\t.section\t.text"
-
-/* Output before writable data. */
-#define DATA_SECTION_ASM_OP "\t.section\t.data"
-
-/* Output before uninitialized data. */
-#define BSS_SECTION_ASM_OP "\t.section\t.bss"
-
-/* Output before 'small' uninitialized data. */
-#define SBSS_SECTION_ASM_OP "\t.section\t.sbss"
-
-#ifndef USED_FOR_TARGET
-/* Default the definition of "small data" to 8 bytes. */
-extern unsigned HOST_WIDE_INT nios2_section_threshold;
-#endif
-
-#define NIOS2_DEFAULT_GVALUE 8
-
-/* This says how to output assembler code to declare an
- uninitialized external linkage data object. Under SVR4,
- the linker seems to want the alignment of data objects
- to depend on their types. We do exactly that here. */
-#undef COMMON_ASM_OP
-#define COMMON_ASM_OP "\t.comm\t"
-
-#define ASM_OUTPUT_ALIGN(FILE, LOG) \
- do { \
- fprintf ((FILE), "%s%d\n", ALIGN_ASM_OP, (LOG)); \
- } while (0)
-
-#undef ASM_OUTPUT_ALIGNED_COMMON
-#define ASM_OUTPUT_ALIGNED_COMMON(FILE, NAME, SIZE, ALIGN) \
-do \
- { \
- fprintf ((FILE), "%s", COMMON_ASM_OP); \
- assemble_name ((FILE), (NAME)); \
- fprintf ((FILE), "," HOST_WIDE_INT_PRINT_UNSIGNED",%u\n", (SIZE), \
- (ALIGN) / BITS_PER_UNIT); \
- } \
-while (0)
-
-
-/* This says how to output assembler code to declare an
- uninitialized internal linkage data object. Under SVR4,
- the linker seems to want the alignment of data objects
- to depend on their types. We do exactly that here. */
-
-#undef ASM_OUTPUT_ALIGNED_DECL_LOCAL
-#define ASM_OUTPUT_ALIGNED_DECL_LOCAL(FILE, DECL, NAME, SIZE, ALIGN) \
-do { \
- if (targetm.in_small_data_p (DECL)) \
- switch_to_section (sbss_section); \
- else \
- switch_to_section (bss_section); \
- ASM_OUTPUT_TYPE_DIRECTIVE (FILE, NAME, "object"); \
- if (!flag_inhibit_size_directive) \
- ASM_OUTPUT_SIZE_DIRECTIVE (FILE, NAME, SIZE); \
- ASM_OUTPUT_ALIGN ((FILE), exact_log2((ALIGN) / BITS_PER_UNIT)); \
- ASM_OUTPUT_LABEL(FILE, NAME); \
- ASM_OUTPUT_SKIP((FILE), (SIZE) ? (SIZE) : 1); \
-} while (0)
-
-/* Put the jump tables in .text because when using position-independent code,
- Nios II elf has no relocation that can represent arbitrary differences
- between symbols in different sections. */
-#define JUMP_TABLES_IN_TEXT_SECTION 1
-
-/* Exception handling. */
-
-/* Describe __builtin_eh_return. */
-#define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, LAST_RETVAL_REGNO)
-#define EH_RETURN_DATA_REGNO(N) ((N) <= (LAST_ARG_REGNO - FIRST_ARG_REGNO) \
- ? (N) + FIRST_ARG_REGNO : INVALID_REGNUM)
-
-/* For PIC, use indirect for global references; it'll end up using a dynamic
- relocation, which we want to keep out of read-only EH sections.
- For local references, we want to use GOT-relative offsets provided
- the assembler supports them. For non-PIC, use an absolute encoding. */
-#ifdef HAVE_AS_NIOS2_GOTOFF_RELOCATION
-#define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \
- (flag_pic \
- ? ((GLOBAL) \
- ? DW_EH_PE_indirect | DW_EH_PE_absptr \
- : DW_EH_PE_datarel | DW_EH_PE_sdata4) \
- : DW_EH_PE_absptr)
-
-#define ASM_MAYBE_OUTPUT_ENCODED_ADDR_RTX(FILE, ENCODING, SIZE, ADDR, DONE) \
- do { \
- if (((ENCODING) & 0xf0) == DW_EH_PE_datarel) \
- { \
- fputs ("\t.4byte %gotoff(", FILE); \
- output_addr_const (FILE, ADDR); \
- fputs (")", FILE); \
- goto DONE; \
- } \
- } while (0)
-
-#else
-/* We don't have %gotoff support in the assembler. Fall back to the encoding
- it used to use instead before the assembler was fixed. This has known
- bugs but mostly works. */
-#define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \
- (flag_pic \
- ? ((GLOBAL) \
- ? DW_EH_PE_indirect | DW_EH_PE_absptr \
- : DW_EH_PE_aligned) \
- : DW_EH_PE_absptr)
-#endif
-
-/* Misc. parameters. */
-
-#define STORE_FLAG_VALUE 1
-#define Pmode SImode
-#define FUNCTION_MODE QImode
-
-#define CASE_VECTOR_MODE Pmode
-
-#define LOAD_EXTEND_OP(MODE) (ZERO_EXTEND)
-
-#define WORD_REGISTER_OPERATIONS 1
-
-#endif /* GCC_NIOS2_H */
diff --git a/gcc/config/nios2/nios2.md b/gcc/config/nios2/nios2.md
deleted file mode 100644
index 2a064946fe05..000000000000
--- a/gcc/config/nios2/nios2.md
+++ /dev/null
@@ -1,1311 +0,0 @@
-;; Machine Description for Altera Nios II.
-;; Copyright (C) 2012-2024 Free Software Foundation, Inc.
-;; Contributed by Jonah Graham (jgraham@altera.com) and
-;; Will Reece (wreece@altera.com).
-;; Contributed by Mentor Graphics, Inc.
-;;
-;; This file is part of GCC.
-;;
-;; GCC is free software; you can redistribute it and/or modify
-;; it under the terms of the GNU General Public License as published by
-;; the Free Software Foundation; either version 3, or (at your option)
-;; any later version.
-;;
-;; GCC is distributed in the hope that it will be useful,
-;; but WITHOUT ANY WARRANTY; without even the implied warranty of
-;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-;; GNU General Public License for more details.
-;;
-;; You should have received a copy of the GNU General Public License
-;; along with GCC; see the file COPYING3. If not see
-;; <http://www.gnu.org/licenses/>.
-
-;; Register numbers
-(define_constants
- [
- (FIRST_RETVAL_REGNO 2) ; Return value registers
- (LAST_RETVAL_REGNO 3) ;
- (FIRST_ARG_REGNO 4) ; Argument registers
- (LAST_ARG_REGNO 7) ;
-
- (TP_REGNO 23) ; Thread pointer register
- (GP_REGNO 26) ; Global pointer register
- (SP_REGNO 27) ; Stack pointer register
- (FP_REGNO 28) ; Frame pointer register
- (EA_REGNO 29) ; Exception return address register
- (RA_REGNO 31) ; Return address register
- (LAST_GP_REG 31) ; Last general purpose register
-
- ;; Target register definitions
- (STATIC_CHAIN_REGNUM 12)
- (STACK_POINTER_REGNUM 27)
- (HARD_FRAME_POINTER_REGNUM 28)
- (PC_REGNUM 37)
- (FRAME_POINTER_REGNUM 38)
- (ARG_POINTER_REGNUM 39)
- (FIRST_PSEUDO_REGISTER 40)
- ]
-)
-
-;; Enumeration of UNSPECs
-
-(define_c_enum "unspecv" [
- UNSPECV_BLOCKAGE
- UNSPECV_WRCTL
- UNSPECV_RDCTL
- UNSPECV_FWRX
- UNSPECV_FWRY
- UNSPECV_FRDXLO
- UNSPECV_FRDXHI
- UNSPECV_FRDY
- UNSPECV_CUSTOM_NXX
- UNSPECV_CUSTOM_XNXX
- UNSPECV_LDXIO
- UNSPECV_STXIO
- UNSPECV_RDPRS
- UNSPECV_FLUSHD
- UNSPECV_FLUSHDA
- UNSPECV_WRPIE
- UNSPECV_ENI
- UNSPECV_LDEX
- UNSPECV_LDSEX
- UNSPECV_STEX
- UNSPECV_STSEX
-])
-
-(define_c_enum "unspec" [
- UNSPEC_FCOS
- UNSPEC_FSIN
- UNSPEC_FTAN
- UNSPEC_FATAN
- UNSPEC_FEXP
- UNSPEC_FLOG
- UNSPEC_ROUND
- UNSPEC_LOAD_GOT_REGISTER
- UNSPEC_PIC_SYM
- UNSPEC_PIC_CALL_SYM
- UNSPEC_PIC_GOTOFF_SYM
- UNSPEC_LOAD_TLS_IE
- UNSPEC_ADD_TLS_LE
- UNSPEC_ADD_TLS_GD
- UNSPEC_ADD_TLS_LDM
- UNSPEC_ADD_TLS_LDO
- UNSPEC_EH_RETURN
- UNSPEC_SYNC
-])
-
-
-;; Instruction scheduler
-
-; No schedule info is currently available, using an assumption that no
-; instruction can use the results of the previous instruction without
-; incuring a stall.
-
-; length of an instruction (in bytes)
-(define_attr "length" ""
- (if_then_else (match_test "nios2_cdx_narrow_form_p (insn)")
- (const_int 2)
- (const_int 4)))
-
-(define_attr "type"
- "unknown,complex,control,alu,cond_alu,st,ld,stwm,ldwm,push,pop,mul,div,\
- custom,add,sub,mov,and,or,xor,neg,not,sll,srl,sra,rol,ror,nop"
- (const_string "complex"))
-
-(define_asm_attributes
- [(set_attr "length" "4")
- (set_attr "type" "complex")])
-
-(define_automaton "nios2")
-(automata_option "v")
-;(automata_option "no-minimization")
-(automata_option "ndfa")
-
-; The nios2 pipeline is fairly straightforward for the fast model.
-; Every alu operation is pipelined so that an instruction can
-; be issued every cycle. However, there are still potential
-; stalls which this description tries to deal with.
-
-(define_cpu_unit "cpu" "nios2")
-
-(define_insn_reservation "complex" 1
- (eq_attr "type" "complex")
- "cpu")
-
-(define_insn_reservation "control" 1
- (eq_attr "type" "control,pop")
- "cpu")
-
-(define_insn_reservation "alu" 1
- (eq_attr "type" "alu,add,sub,mov,and,or,xor,neg,not")
- "cpu")
-
-(define_insn_reservation "cond_alu" 1
- (eq_attr "type" "cond_alu")
- "cpu")
-
-(define_insn_reservation "st" 1
- (eq_attr "type" "st,stwm,push")
- "cpu")
-
-(define_insn_reservation "custom" 1
- (eq_attr "type" "custom")
- "cpu")
-
-; shifts, muls and lds have three cycle latency
-(define_insn_reservation "ld" 3
- (eq_attr "type" "ld,ldwm")
- "cpu")
-
-(define_insn_reservation "shift" 3
- (eq_attr "type" "sll,srl,sra,rol,ror")
- "cpu")
-
-(define_insn_reservation "mul" 3
- (eq_attr "type" "mul")
- "cpu")
-
-(define_insn_reservation "div" 1
- (eq_attr "type" "div")
- "cpu")
-
-(include "predicates.md")
-(include "constraints.md")
-
-
-;; Move instructions
-
-(define_mode_iterator M [QI HI SI])
-
-(define_expand "mov<mode>"
- [(set (match_operand:M 0 "nonimmediate_operand" "")
- (match_operand:M 1 "general_operand" ""))]
- ""
-{
- if (nios2_emit_move_sequence (operands, <MODE>mode))
- DONE;
-})
-
-(define_insn "*high"
- [(set (match_operand:SI 0 "register_operand" "=r")
- (high:SI (match_operand:SI 1 "immediate_operand" "i")))]
- ""
- "movhi\\t%0, %H1"
- [(set_attr "type" "alu")])
-
-(define_insn "*lo_sum"
- [(set (match_operand:SI 0 "register_operand" "=r")
- (lo_sum:SI (match_operand:SI 1 "register_operand" "r")
- (match_operand:SI 2 "immediate_operand" "i")))]
- ""
- "addi\\t%0, %1, %L2"
- [(set_attr "type" "alu")])
-
-(define_insn_and_split "movqi_internal"
- [(set (match_operand:QI 0 "nonimmediate_operand" "=m, r,r")
- (match_operand:QI 1 "general_operand" "rM,m,rI"))]
- "(register_operand (operands[0], QImode)
- || reg_or_0_operand (operands[1], QImode))"
- {
- switch (which_alternative)
- {
- case 0:
- if (get_attr_length (insn) != 2)
- return "stb%o0\\t%z1, %0";
- else if (const_0_operand (operands[1], QImode))
- return "stbz.n\\t%z1, %0";
- else
- return "stb.n\\t%z1, %0";
- case 1:
- return "ldbu%o1%.\\t%0, %1";
- case 2:
- return "mov%i1%.\\t%0, %z1";
- default:
- gcc_unreachable ();
- }
- }
- "(nios2_large_constant_memory_operand_p (operands[0])
- || nios2_large_constant_memory_operand_p (operands[1]))"
- [(set (match_dup 0) (match_dup 1))]
- {
- if (nios2_large_constant_memory_operand_p (operands[0]))
- operands[0] = nios2_split_large_constant_memory_operand (operands[0]);
- else
- operands[1] = nios2_split_large_constant_memory_operand (operands[1]);
- }
- [(set_attr "type" "st,ld,mov")])
-
-(define_insn_and_split "movhi_internal"
- [(set (match_operand:HI 0 "nonimmediate_operand" "=m, r,r")
- (match_operand:HI 1 "general_operand" "rM,m,rI"))]
- "(register_operand (operands[0], HImode)
- || reg_or_0_operand (operands[1], HImode))"
- {
- switch (which_alternative)
- {
- case 0:
- return "sth%o0%.\\t%z1, %0";
- case 1:
- return "ldhu%o1%.\\t%0, %1";
- case 2:
- return "mov%i1%.\\t%0, %z1";
- default:
- gcc_unreachable ();
- }
- }
- "(nios2_large_constant_memory_operand_p (operands[0])
- || nios2_large_constant_memory_operand_p (operands[1]))"
- [(set (match_dup 0) (match_dup 1))]
- {
- if (nios2_large_constant_memory_operand_p (operands[0]))
- operands[0] = nios2_split_large_constant_memory_operand (operands[0]);
- else
- operands[1] = nios2_split_large_constant_memory_operand (operands[1]);
- }
- [(set_attr "type" "st,ld,mov")])
-
-(define_insn_and_split "movsi_internal"
- [(set (match_operand:SI 0 "nonimmediate_operand" "=m, r,r, r")
- (match_operand:SI 1 "general_operand" "rM,m,rIJK,S"))]
- "(register_operand (operands[0], SImode)
- || reg_or_0_operand (operands[1], SImode))"
- {
- switch (which_alternative)
- {
- case 0:
- if (get_attr_length (insn) != 2)
- return "stw%o0\\t%z1, %0";
- else if (stack_memory_operand (operands[0], SImode))
- return "stwsp.n\\t%z1, %0";
- else if (const_0_operand (operands[1], SImode))
- return "stwz.n\\t%z1, %0";
- else
- return "stw.n\\t%z1, %0";
- case 1:
- if (get_attr_length (insn) != 2)
- return "ldw%o1\\t%0, %1";
- else if (stack_memory_operand (operands[1], SImode))
- return "ldwsp.n\\t%0, %1";
- else
- return "ldw.n\\t%0, %1";
- case 2:
- return "mov%i1%.\\t%0, %z1";
- case 3:
- return "addi\\t%0, gp, %%gprel(%1)";
- default:
- gcc_unreachable ();
- }
- }
- "(nios2_large_constant_memory_operand_p (operands[0])
- || nios2_large_constant_memory_operand_p (operands[1])
- || (nios2_large_constant_p (operands[1])
- && !(CONST_INT_P (operands[1])
- && (SMALL_INT_UNSIGNED (INTVAL (operands[1]))
- || UPPER16_INT (INTVAL (operands[1]))))))"
- [(set (match_dup 0) (match_dup 1))]
- {
- if (nios2_large_constant_memory_operand_p (operands[0]))
- operands[0] = nios2_split_large_constant_memory_operand (operands[0]);
- else if (nios2_large_constant_memory_operand_p (operands[1]))
- operands[1] = nios2_split_large_constant_memory_operand (operands[1]);
- else
- operands[1] = nios2_split_large_constant (operands[1], operands[0]);
- }
- [(set_attr "type" "st,ld,mov,alu")])
-
-(define_mode_iterator BH [QI HI])
-(define_mode_iterator BHW [QI HI SI])
-(define_mode_attr bh [(QI "b") (HI "h")])
-(define_mode_attr bhw [(QI "b") (HI "h") (SI "w")])
-(define_mode_attr bhw_uns [(QI "bu") (HI "hu") (SI "w")])
-
-(define_insn_and_split "ld<bhw_uns>io"
- [(set (match_operand:BHW 0 "register_operand" "=r")
- (unspec_volatile:BHW
- [(match_operand:BHW 1 "ldstio_memory_operand" "w")] UNSPECV_LDXIO))]
- ""
- "ld<bhw_uns>io\\t%0, %1"
- "nios2_large_constant_memory_operand_p (operands[1])"
- [(set (match_dup 0)
- (unspec_volatile:BHW [(match_dup 1)] UNSPECV_LDXIO))]
- {
- operands[1] = nios2_split_large_constant_memory_operand (operands[1]);
- }
- [(set_attr "type" "ld")])
-
-(define_expand "ld<bh>io"
- [(set (match_operand:BH 0 "register_operand" "=r")
- (match_operand:BH 1 "ldstio_memory_operand" "w"))]
- ""
-{
- rtx tmp = gen_reg_rtx (SImode);
- emit_insn (gen_ld<bh>io_signed (tmp, operands[1]));
- emit_insn (gen_mov<mode> (operands[0], gen_lowpart (<MODE>mode, tmp)));
- DONE;
-})
-
-(define_insn_and_split "ld<bh>io_signed"
- [(set (match_operand:SI 0 "register_operand" "=r")
- (sign_extend:SI
- (unspec_volatile:BH
- [(match_operand:BH 1 "ldstio_memory_operand" "w")] UNSPECV_LDXIO)))]
- ""
- "ld<bh>io\\t%0, %1"
- "nios2_large_constant_memory_operand_p (operands[1])"
- [(set (match_dup 0)
- (sign_extend:SI (unspec_volatile:BH [(match_dup 1)] UNSPECV_LDXIO)))]
- {
- operands[1] = nios2_split_large_constant_memory_operand (operands[1]);
- }
- [(set_attr "type" "ld")])
-
-(define_insn_and_split "st<bhw>io"
- [(set (match_operand:BHW 0 "ldstio_memory_operand" "=w")
- (unspec_volatile:BHW
- [(match_operand:BHW 1 "reg_or_0_operand" "rM")] UNSPECV_STXIO))]
- ""
- "st<bhw>io\\t%z1, %0"
- "nios2_large_constant_memory_operand_p (operands[0])"
- [(set (match_dup 0) (unspec_volatile:BHW [(match_dup 1)] UNSPECV_STXIO))]
- {
- operands[0] = nios2_split_large_constant_memory_operand (operands[0]);
- }
- [(set_attr "type" "st")])
-
-
-;; QI to [HI, SI] extension patterns are collected together
-(define_mode_iterator QX [HI SI])
-
-;; Zero extension patterns
-(define_insn_and_split "zero_extendhisi2"
- [(set (match_operand:SI 0 "register_operand" "=r,r")
- (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "r,m")))]
- ""
- "@
- andi%.\\t%0, %1, 0xffff
- ldhu%o1%.\\t%0, %1"
- "nios2_large_constant_memory_operand_p (operands[1])"
- [(set (match_dup 0) (zero_extend:SI (match_dup 1)))]
- {
- operands[1] = nios2_split_large_constant_memory_operand (operands[1]);
- }
- [(set_attr "type" "and,ld")])
-
-(define_insn_and_split "zero_extendqi<mode>2"
- [(set (match_operand:QX 0 "register_operand" "=r,r")
- (zero_extend:QX (match_operand:QI 1 "nonimmediate_operand" "r,m")))]
- ""
- "@
- andi%.\\t%0, %1, 0xff
- ldbu%o1%.\\t%0, %1"
- "nios2_large_constant_memory_operand_p (operands[1])"
- [(set (match_dup 0) (zero_extend:QX (match_dup 1)))]
- {
- operands[1] = nios2_split_large_constant_memory_operand (operands[1]);
- }
- [(set_attr "type" "and,ld")])
-
-;; Sign extension patterns
-
-(define_insn_and_split "extendhisi2"
- [(set (match_operand:SI 0 "register_operand" "=r,r")
- (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "r,m")))]
- ""
- "@
- #
- ldh%o1%.\\t%0, %1"
- "nios2_large_constant_memory_operand_p (operands[1])"
- [(set (match_dup 0) (sign_extend:SI (match_dup 1)))]
- {
- operands[1] = nios2_split_large_constant_memory_operand (operands[1]);
- }
- [(set_attr "type" "alu,ld")])
-
-(define_insn_and_split "extendqi<mode>2"
- [(set (match_operand:QX 0 "register_operand" "=r,r")
- (sign_extend:QX (match_operand:QI 1 "nonimmediate_operand" "r,m")))]
- ""
- "@
- #
- ldb%o1%.\\t%0, %1"
- "nios2_large_constant_memory_operand_p (operands[1])"
- [(set (match_dup 0) (sign_extend:QX (match_dup 1)))]
- {
- operands[1] = nios2_split_large_constant_memory_operand (operands[1]);
- }
- [(set_attr "type" "alu,ld")])
-
-;; Split patterns for register alternative cases.
-(define_split
- [(set (match_operand:SI 0 "register_operand" "")
- (sign_extend:SI (match_operand:HI 1 "register_operand" "")))]
- "reload_completed"
- [(set (match_dup 0)
- (and:SI (match_dup 1) (const_int 65535)))
- (set (match_dup 0)
- (xor:SI (match_dup 0) (const_int 32768)))
- (set (match_dup 0)
- (plus:SI (match_dup 0) (const_int -32768)))]
- "operands[1] = gen_lowpart (SImode, operands[1]);")
-
-(define_split
- [(set (match_operand:QX 0 "register_operand" "")
- (sign_extend:QX (match_operand:QI 1 "register_operand" "")))]
- "reload_completed"
- [(set (match_dup 0)
- (and:SI (match_dup 1) (const_int 255)))
- (set (match_dup 0)
- (xor:SI (match_dup 0) (const_int 128)))
- (set (match_dup 0)
- (plus:SI (match_dup 0) (const_int -128)))]
- "operands[0] = gen_lowpart (SImode, operands[0]);
- operands[1] = gen_lowpart (SImode, operands[1]);")
-
-
-;; Arithmetic Operations
-
-(define_insn "addsi3"
- [(set (match_operand:SI 0 "register_operand" "=r")
- (plus:SI (match_operand:SI 1 "register_operand" "%r")
- (match_operand:SI 2 "add_regimm_operand" "rIT")))]
- ""
-{
- return nios2_add_insn_asm (insn, operands);
-}
- [(set_attr "type" "add")])
-
-(define_insn "subsi3"
- [(set (match_operand:SI 0 "register_operand" "=r")
- (minus:SI (match_operand:SI 1 "reg_or_0_operand" "rM")
- (match_operand:SI 2 "register_operand" "r")))]
- ""
- "sub%.\\t%0, %z1, %2"
- [(set_attr "type" "sub")])
-
-(define_insn "mulsi3"
- [(set (match_operand:SI 0 "register_operand" "=r")
- (mult:SI (match_operand:SI 1 "register_operand" "%r")
- (match_operand:SI 2 "arith_operand" "rI")))]
- "TARGET_HAS_MUL"
- "mul%i2\\t%0, %1, %z2"
- [(set_attr "type" "mul")])
-
-(define_expand "divsi3"
- [(set (match_operand:SI 0 "register_operand" "=r")
- (div:SI (match_operand:SI 1 "register_operand" "r")
- (match_operand:SI 2 "register_operand" "r")))]
- ""
-{
- if (!TARGET_HAS_DIV)
- {
- if (TARGET_FAST_SW_DIV)
- {
- nios2_emit_expensive_div (operands, SImode);
- DONE;
- }
- else
- FAIL;
- }
-})
-
-(define_insn "divsi3_insn"
- [(set (match_operand:SI 0 "register_operand" "=r")
- (div:SI (match_operand:SI 1 "register_operand" "r")
- (match_operand:SI 2 "register_operand" "r")))]
- "TARGET_HAS_DIV"
- "div\\t%0, %1, %2"
- [(set_attr "type" "div")])
-
-(define_insn "udivsi3"
- [(set (match_operand:SI 0 "register_operand" "=r")
- (udiv:SI (match_operand:SI 1 "register_operand" "r")
- (match_operand:SI 2 "register_operand" "r")))]
- "TARGET_HAS_DIV"
- "divu\\t%0, %1, %2"
- [(set_attr "type" "div")])
-
-(define_code_iterator EXTEND [sign_extend zero_extend])
-(define_code_attr us [(sign_extend "s") (zero_extend "u")])
-(define_code_attr mul [(sign_extend "mul") (zero_extend "umul")])
-
-(define_insn "<us>mulsi3_highpart"
- [(set (match_operand:SI 0 "register_operand" "=r")
- (truncate:SI
- (lshiftrt:DI
- (mult:DI (EXTEND:DI (match_operand:SI 1 "register_operand" "r"))
- (EXTEND:DI (match_operand:SI 2 "register_operand" "r")))
- (const_int 32))))]
- "TARGET_HAS_MULX"
- "mulx<us><us>\\t%0, %1, %2"
- [(set_attr "type" "mul")])
-
-(define_expand "<mul>sidi3"
- [(set (match_operand:DI 0 "register_operand" "")
- (mult:DI (EXTEND:DI (match_operand:SI 1 "register_operand" ""))
- (EXTEND:DI (match_operand:SI 2 "register_operand" ""))))]
- "TARGET_HAS_MULX"
-{
- rtx hi = gen_reg_rtx (SImode);
- rtx lo = gen_reg_rtx (SImode);
-
- emit_insn (gen_<us>mulsi3_highpart (hi, operands[1], operands[2]));
- emit_insn (gen_mulsi3 (lo, operands[1], operands[2]));
- emit_move_insn (gen_lowpart (SImode, operands[0]), lo);
- emit_move_insn (gen_highpart (SImode, operands[0]), hi);
- DONE;
-})
-
-
-;; Negate and ones complement
-
-(define_insn "negsi2"
- [(set (match_operand:SI 0 "register_operand" "=r")
- (neg:SI (match_operand:SI 1 "register_operand" "r")))]
- ""
-{
- if (get_attr_length (insn) == 2)
- return "neg.n\\t%0, %1";
- else
- return "sub\\t%0, zero, %1";
-}
- [(set_attr "type" "neg")])
-
-(define_insn "one_cmplsi2"
- [(set (match_operand:SI 0 "register_operand" "=r")
- (not:SI (match_operand:SI 1 "register_operand" "r")))]
- ""
-{
- if (get_attr_length (insn) == 2)
- return "not.n\\t%0, %1";
- else
- return "nor\\t%0, zero, %1";
-}
- [(set_attr "type" "not")])
-
-
-;; Integer logical Operations
-
-(define_insn "andsi3"
- [(set (match_operand:SI 0 "register_operand" "=r")
- (and:SI (match_operand:SI 1 "register_operand" "%r")
- (match_operand:SI 2 "and_operand" "rJKP")))]
- ""
- "and%x2%.\\t%0, %1, %y2"
- [(set_attr "type" "and")])
-
-(define_code_iterator LOGICAL [ior xor])
-(define_code_attr logical_asm [(ior "or") (xor "xor")])
-
-(define_insn "<code>si3"
- [(set (match_operand:SI 0 "register_operand" "=r")
- (LOGICAL:SI (match_operand:SI 1 "register_operand" "%r")
- (match_operand:SI 2 "logical_operand" "rJK")))]
- ""
- "<logical_asm>%x2%.\\t%0, %1, %y2"
- [(set_attr "type" "<logical_asm>")])
-
-(define_insn "*norsi3"
- [(set (match_operand:SI 0 "register_operand" "=r")
- (and:SI (not:SI (match_operand:SI 1 "register_operand" "%r"))
- (not:SI (match_operand:SI 2 "register_operand" "r"))))]
- ""
- "nor\\t%0, %1, %2"
- [(set_attr "type" "alu")])
-
-
-;; Shift instructions
-
-(define_code_iterator SHIFT [ashift ashiftrt lshiftrt rotate])
-(define_code_attr shift_op [(ashift "ashl") (ashiftrt "ashr")
- (lshiftrt "lshr") (rotate "rotl")])
-(define_code_attr shift_asm [(ashift "sll") (ashiftrt "sra")
- (lshiftrt "srl") (rotate "rol")])
-
-(define_insn "<shift_op>si3"
- [(set (match_operand:SI 0 "register_operand" "=r")
- (SHIFT:SI (match_operand:SI 1 "register_operand" "r")
- (match_operand:SI 2 "shift_operand" "rL")))]
- ""
- "<shift_asm>%i2%.\\t%0, %1, %z2"
- [(set_attr "type" "<shift_asm>")])
-
-(define_insn "rotrsi3"
- [(set (match_operand:SI 0 "register_operand" "=r")
- (rotatert:SI (match_operand:SI 1 "register_operand" "r")
- (match_operand:SI 2 "register_operand" "r")))]
- ""
- "ror\\t%0, %1, %2"
- [(set_attr "type" "ror")])
-
-;; Nios II R2 Bit Manipulation Extension (BMX), provides
-;; bit merge/insertion/extraction instructions.
-
-(define_insn "*merge"
- [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
- (match_operand:SI 1 "const_shift_operand" "L")
- (match_operand:SI 2 "const_shift_operand" "L"))
- (zero_extract:SI (match_operand:SI 3 "register_operand" "r")
- (match_dup 1) (match_dup 2)))]
- "TARGET_HAS_BMX"
-{
- operands[4] = GEN_INT (INTVAL (operands[1]) + INTVAL (operands[2]) - 1);
- return "merge\\t%0, %3, %4, %2";
-}
- [(set_attr "type" "alu")])
-
-(define_insn "extzv"
- [(set (match_operand:SI 0 "register_operand" "=r")
- (zero_extract:SI (match_operand:SI 1 "register_operand" "r")
- (match_operand:SI 2 "const_shift_operand" "L")
- (match_operand:SI 3 "const_shift_operand" "L")))]
- "TARGET_HAS_BMX"
-{
- operands[4] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[3]) - 1);
- return "extract\\t%0, %1, %4, %3";
-}
- [(set_attr "type" "alu")])
-
-(define_insn "insv"
- [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
- (match_operand:SI 1 "const_shift_operand" "L")
- (match_operand:SI 2 "const_shift_operand" "L"))
- (match_operand:SI 3 "reg_or_0_operand" "rM"))]
- "TARGET_HAS_BMX"
-{
- operands[4] = GEN_INT (INTVAL (operands[1]) + INTVAL (operands[2]) - 1);
- return "insert\\t%0, %z3, %4, %2";
-}
- [(set_attr "type" "alu")])
-
-
-
-;; Floating point instructions
-
-;; Mode iterator for single/double float
-(define_mode_iterator F [SF DF])
-(define_mode_attr f [(SF "s") (DF "d")])
-
-;; Basic arithmetic instructions
-(define_code_iterator FOP3 [plus minus mult div])
-(define_code_attr fop3 [(plus "add") (minus "sub") (mult "mul") (div "div")])
-
-(define_insn "<fop3><mode>3"
- [(set (match_operand:F 0 "register_operand" "=r")
- (FOP3:F (match_operand:F 1 "register_operand" "r")
- (match_operand:F 2 "register_operand" "r")))]
- "nios2_fpu_insn_enabled (n2fpu_f<fop3><f>)"
- { return nios2_fpu_insn_asm (n2fpu_f<fop3><f>); }
- [(set_attr "type" "custom")])
-
-;; Floating point min/max operations
-(define_code_iterator SMINMAX [smin smax])
-(define_code_attr minmax [(smin "min") (smax "max")])
-(define_insn "<code><mode>3"
- [(set (match_operand:F 0 "register_operand" "=r")
- (SMINMAX:F (match_operand:F 1 "register_operand" "r")
- (match_operand:F 2 "register_operand" "r")))]
- "nios2_fpu_insn_enabled (n2fpu_f<minmax><f>)"
- { return nios2_fpu_insn_asm (n2fpu_f<minmax><f>); }
- [(set_attr "type" "custom")])
-
-;; These 2-operand FP operations can be collected together
-(define_code_iterator FOP2 [abs neg sqrt])
-(define_insn "<code><mode>2"
- [(set (match_operand:F 0 "register_operand" "=r")
- (FOP2:F (match_operand:F 1 "register_operand" "r")))]
- "nios2_fpu_insn_enabled (n2fpu_f<code><f>)"
- { return nios2_fpu_insn_asm (n2fpu_f<code><f>); }
- [(set_attr "type" "custom")])
-
-;; X, Y register access instructions
-(define_insn "nios2_fwrx"
- [(unspec_volatile [(match_operand:DF 0 "register_operand" "r")] UNSPECV_FWRX)]
- "nios2_fpu_insn_enabled (n2fpu_fwrx)"
- { return nios2_fpu_insn_asm (n2fpu_fwrx); }
- [(set_attr "type" "custom")])
-
-(define_insn "nios2_fwry"
- [(unspec_volatile [(match_operand:SF 0 "register_operand" "r")] UNSPECV_FWRY)]
- "nios2_fpu_insn_enabled (n2fpu_fwry)"
- { return nios2_fpu_insn_asm (n2fpu_fwry); }
- [(set_attr "type" "custom")])
-
-;; The X, Y read insns uses an int iterator
-(define_int_iterator UNSPEC_READ_XY [UNSPECV_FRDXLO UNSPECV_FRDXHI
- UNSPECV_FRDY])
-(define_int_attr read_xy [(UNSPECV_FRDXLO "frdxlo") (UNSPECV_FRDXHI "frdxhi")
- (UNSPECV_FRDY "frdy")])
-(define_insn "nios2_<read_xy>"
- [(set (match_operand:SF 0 "register_operand" "=r")
- (unspec_volatile:SF [(const_int 0)] UNSPEC_READ_XY))]
- "nios2_fpu_insn_enabled (n2fpu_<read_xy>)"
- { return nios2_fpu_insn_asm (n2fpu_<read_xy>); }
- [(set_attr "type" "custom")])
-
-;; Various math functions
-(define_int_iterator MATHFUNC
- [UNSPEC_FCOS UNSPEC_FSIN UNSPEC_FTAN UNSPEC_FATAN UNSPEC_FEXP UNSPEC_FLOG])
-(define_int_attr mathfunc [(UNSPEC_FCOS "cos") (UNSPEC_FSIN "sin")
- (UNSPEC_FTAN "tan") (UNSPEC_FATAN "atan")
- (UNSPEC_FEXP "exp") (UNSPEC_FLOG "log")])
-
-(define_insn "<mathfunc><mode>2"
- [(set (match_operand:F 0 "register_operand" "=r")
- (unspec:F [(match_operand:F 1 "register_operand" "r")] MATHFUNC))]
- "nios2_fpu_insn_enabled (n2fpu_f<mathfunc><f>)"
- { return nios2_fpu_insn_asm (n2fpu_f<mathfunc><f>); }
- [(set_attr "type" "custom")])
-
-;; Converting between floating point and fixed point
-
-(define_code_iterator FLOAT [float unsigned_float])
-(define_code_iterator FIX [fix unsigned_fix])
-
-(define_code_attr conv_op [(float "float") (unsigned_float "floatuns")
- (fix "fix") (unsigned_fix "fixuns")])
-(define_code_attr i [(float "i") (unsigned_float "u")
- (fix "i") (unsigned_fix "u")])
-
-;; Integer to float conversions
-(define_insn "<conv_op>si<mode>2"
- [(set (match_operand:F 0 "register_operand" "=r")
- (FLOAT:F (match_operand:SI 1 "register_operand" "r")))]
- "nios2_fpu_insn_enabled (n2fpu_float<i><f>)"
- { return nios2_fpu_insn_asm (n2fpu_float<i><f>); }
- [(set_attr "type" "custom")])
-
-;; Float to integer conversions
-(define_insn "<conv_op>_trunc<mode>si2"
- [(set (match_operand:SI 0 "register_operand" "=r")
- (FIX:SI (match_operand:F 1 "general_operand" "r")))]
- "nios2_fpu_insn_enabled (n2fpu_fix<f><i>)"
- { return nios2_fpu_insn_asm (n2fpu_fix<f><i>); }
- [(set_attr "type" "custom")])
-
-(define_insn "lroundsfsi2"
- [(set (match_operand:SI 0 "register_operand" "=r")
- (unspec:SI [(match_operand:SF 1 "general_operand" "r")] UNSPEC_ROUND))]
- "nios2_fpu_insn_enabled (n2fpu_round)"
- { return nios2_fpu_insn_asm (n2fpu_round); }
- [(set_attr "type" "custom")])
-
-(define_insn "extendsfdf2"
- [(set (match_operand:DF 0 "register_operand" "=r")
- (float_extend:DF (match_operand:SF 1 "general_operand" "r")))]
- "nios2_fpu_insn_enabled (n2fpu_fextsd)"
- { return nios2_fpu_insn_asm (n2fpu_fextsd); }
- [(set_attr "type" "custom")])
-
-(define_insn "truncdfsf2"
- [(set (match_operand:SF 0 "register_operand" "=r")
- (float_truncate:SF (match_operand:DF 1 "general_operand" "r")))]
- "nios2_fpu_insn_enabled (n2fpu_ftruncds)"
- { return nios2_fpu_insn_asm (n2fpu_ftruncds); }
- [(set_attr "type" "custom")])
-
-
-
-;; Prologue, Epilogue and Return
-
-(define_expand "prologue"
- [(const_int 1)]
- ""
-{
- nios2_expand_prologue ();
- DONE;
-})
-
-(define_expand "epilogue"
- [(return)]
- ""
-{
- nios2_expand_epilogue (false);
- DONE;
-})
-
-(define_expand "sibcall_epilogue"
- [(return)]
- ""
-{
- nios2_expand_epilogue (true);
- DONE;
-})
-
-(define_expand "return"
- [(simple_return)]
- "nios2_can_use_return_insn ()"
-{
- if (nios2_expand_return ())
- DONE;
-})
-
-(define_insn "simple_return"
- [(simple_return)]
- ""
- "ret%."
- [(set_attr "type" "control")])
-
-;; Block any insns from being moved before this point, since the
-;; profiling call to mcount can use various registers that aren't
-;; saved or used to pass arguments.
-
-(define_insn "blockage"
- [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)]
- ""
- ""
- [(set_attr "type" "unknown")
- (set_attr "length" "0")])
-
-;; This is used in compiling the unwind routines.
-(define_expand "eh_return"
- [(use (match_operand 0 "general_operand"))]
- ""
-{
- if (GET_MODE (operands[0]) != Pmode)
- operands[0] = convert_to_mode (Pmode, operands[0], 0);
- emit_insn (gen_eh_set_ra (operands[0]));
- DONE;
-})
-
-;; Modify the return address for EH return. We can't expand this
-;; until we know where it will be put in the stack frame.
-
-(define_insn_and_split "eh_set_ra"
- [(unspec [(match_operand:SI 0 "register_operand" "r")] UNSPEC_EH_RETURN)
- (clobber (match_scratch:SI 1 "=&r"))]
- ""
- "#"
- "reload_completed"
- [(const_int 0)]
-{
- nios2_set_return_address (operands[0], operands[1]);
- DONE;
-})
-
-
-;; Jumps and calls
-
-; Note that the assembler fixes up any out-of-range branch instructions not
-; caught by the compiler branch shortening code. The sequence emitted by
-; the assembler can be very inefficient, but it is correct for PIC code.
-; For non-PIC we are better off converting to an absolute JMPI.
-;
-; Direct calls and sibcalls use the CALL and JMPI instructions, respectively.
-; These instructions have an immediate operand that specifies the low 28 bits
-; of the PC, effectively allowing direct calls within a 256MB memory segment.
-; Per the Nios II Processor Reference Handbook, the linker is not required to
-; check or adjust for overflow.
-
-(define_insn "indirect_jump"
- [(set (pc) (match_operand:SI 0 "register_operand" "c"))]
- ""
- "jmp%!\\t%0"
- [(set_attr "type" "control")])
-
-(define_insn "jump"
- [(set (pc)
- (label_ref (match_operand 0 "" "")))]
- ""
- {
- if (get_attr_length (insn) == 2)
- return "br.n\\t%0";
- else if (get_attr_length (insn) == 4)
- return "br\\t%0";
- else
- return "jmpi\\t%0";
- }
- [(set_attr "type" "control")
- (set (attr "length")
- (if_then_else
- (and (match_test "TARGET_HAS_CDX")
- (and (ge (minus (match_dup 0) (pc)) (const_int -1022))
- (le (minus (match_dup 0) (pc)) (const_int 1022))))
- (const_int 2)
- (if_then_else
- (ior (match_test "flag_pic")
- (and (ge (minus (match_dup 0) (pc)) (const_int -32764))
- (le (minus (match_dup 0) (pc)) (const_int 32764))))
- (const_int 4)
- (const_int 8))))])
-
-(define_expand "call"
- [(parallel [(call (match_operand 0 "" "")
- (match_operand 1 "" ""))
- (clobber (reg:SI RA_REGNO))])]
- ""
- "nios2_adjust_call_address (&operands[0], NULL_RTX);")
-
-(define_expand "call_value"
- [(parallel [(set (match_operand 0 "" "")
- (call (match_operand 1 "" "")
- (match_operand 2 "" "")))
- (clobber (reg:SI RA_REGNO))])]
- ""
- "nios2_adjust_call_address (&operands[1], NULL_RTX);")
-
-(define_insn "*call"
- [(call (mem:QI (match_operand:SI 0 "call_operand" "i,r"))
- (match_operand 1 "" ""))
- (clobber (reg:SI RA_REGNO))]
- ""
- "@
- call\\t%0
- callr%.\\t%0"
- [(set_attr "type" "control")])
-
-(define_insn "*call_value"
- [(set (match_operand 0 "" "")
- (call (mem:QI (match_operand:SI 1 "call_operand" "i,r"))
- (match_operand 2 "" "")))
- (clobber (reg:SI RA_REGNO))]
- ""
- "@
- call\\t%1
- callr%.\\t%1"
- [(set_attr "type" "control")])
-
-(define_expand "sibcall"
- [(parallel [(call (match_operand 0 "" "")
- (match_operand 1 "" ""))
- (return)])]
- ""
- "nios2_adjust_call_address (&operands[0], NULL_RTX);")
-
-(define_expand "sibcall_value"
- [(parallel [(set (match_operand 0 "" "")
- (call (match_operand 1 "" "")
- (match_operand 2 "" "")))
- (return)])]
- ""
- "nios2_adjust_call_address (&operands[1], NULL_RTX);")
-
-(define_insn "sibcall_internal"
- [(call (mem:QI (match_operand:SI 0 "call_operand" "i,j"))
- (match_operand 1 "" ""))
- (return)]
- ""
- "@
- jmpi\\t%0
- jmp%!\\t%0"
- [(set_attr "type" "control")])
-
-(define_insn "sibcall_value_internal"
- [(set (match_operand 0 "register_operand" "")
- (call (mem:QI (match_operand:SI 1 "call_operand" "i,j"))
- (match_operand 2 "" "")))
- (return)]
- ""
- "@
- jmpi\\t%1
- jmp%!\\t%1"
- [(set_attr "type" "control")])
-
-(define_expand "tablejump"
- [(parallel [(set (pc) (match_operand 0 "register_operand" "r"))
- (use (label_ref (match_operand 1 "" "")))])]
- ""
-{
- if (flag_pic)
- {
- /* Hopefully, CSE will eliminate this copy. */
- rtx reg1 = copy_addr_to_reg (gen_rtx_LABEL_REF (Pmode, operands[1]));
- rtx reg2 = gen_reg_rtx (SImode);
-
- emit_insn (gen_addsi3 (reg2, operands[0], reg1));
- operands[0] = reg2;
- }
-})
-
-(define_insn "*tablejump"
- [(set (pc)
- (match_operand:SI 0 "register_operand" "c"))
- (use (label_ref (match_operand 1 "" "")))]
- ""
- "jmp%!\\t%0"
- [(set_attr "type" "control")])
-
-
-;; cstore, cbranch patterns
-
-(define_mode_iterator CM [SI SF DF])
-
-(define_expand "cstore<mode>4"
- [(set (match_operand:SI 0 "register_operand" "=r")
- (match_operator:SI 1 "expandable_comparison_operator"
- [(match_operand:CM 2 "register_operand")
- (match_operand:CM 3 "nonmemory_operand")]))]
- ""
-{
- if (!nios2_validate_compare (<MODE>mode, &operands[1], &operands[2],
- &operands[3]))
- FAIL;
-})
-
-(define_expand "cbranch<mode>4"
- [(set (pc)
- (if_then_else
- (match_operator 0 "expandable_comparison_operator"
- [(match_operand:CM 1 "register_operand")
- (match_operand:CM 2 "nonmemory_operand")])
- (label_ref (match_operand 3 ""))
- (pc)))]
- ""
-{
- if (!nios2_validate_compare (<MODE>mode, &operands[0], &operands[1],
- &operands[2]))
- FAIL;
- if (GET_MODE_CLASS (<MODE>mode) == MODE_FLOAT
- || !reg_or_0_operand (operands[2], <MODE>mode))
- {
- rtx condreg = gen_reg_rtx (SImode);
- emit_insn (gen_cstore<mode>4
- (condreg, operands[0], operands[1], operands[2]));
- operands[1] = condreg;
- operands[2] = const0_rtx;
- operands[0] = gen_rtx_fmt_ee (NE, VOIDmode, condreg, const0_rtx);
- }
-})
-
-(define_insn "nios2_cbranch"
- [(set (pc)
- (if_then_else
- (match_operator 0 "ordered_comparison_operator"
- [(match_operand:SI 1 "reg_or_0_operand" "rM")
- (match_operand:SI 2 "reg_or_0_operand" "rM")])
- (label_ref (match_operand 3 "" ""))
- (pc)))]
- ""
-{
- if (get_attr_length (insn) == 2)
- return "b%0z.n\t%z1, %l3";
- else if (get_attr_length (insn) == 4)
- return "b%0\t%z1, %z2, %l3";
- else if (get_attr_length (insn) == 6)
- return "b%R0z.n\t%z1, .+6;jmpi\t%l3";
- else
- return "b%R0\t%z1, %z2, .+8;jmpi\t%l3";
-}
- [(set_attr "type" "control")
- (set (attr "length")
- (cond
- [(and (match_test "nios2_cdx_narrow_form_p (insn)")
- (ge (minus (match_dup 3) (pc)) (const_int -126))
- (le (minus (match_dup 3) (pc)) (const_int 126)))
- (const_int 2)
- (ior (match_test "flag_pic")
- (and (ge (minus (match_dup 3) (pc)) (const_int -32764))
- (le (minus (match_dup 3) (pc)) (const_int 32764))))
- (const_int 4)
- (match_test "nios2_cdx_narrow_form_p (insn)")
- (const_int 6)]
- (const_int 8)))])
-
-;; Floating point comparisons
-(define_code_iterator FCMP [eq ne gt ge le lt])
-(define_insn "nios2_s<code><mode>"
- [(set (match_operand:SI 0 "register_operand" "=r")
- (FCMP:SI (match_operand:F 1 "register_operand" "r")
- (match_operand:F 2 "register_operand" "r")))]
- "nios2_fpu_insn_enabled (n2fpu_fcmp<code><f>)"
- { return nios2_fpu_insn_asm (n2fpu_fcmp<code><f>); }
- [(set_attr "type" "custom")])
-
-;; Integer comparisons
-
-(define_code_iterator EQNE [eq ne])
-(define_insn "nios2_cmp<code>"
- [(set (match_operand:SI 0 "register_operand" "=r")
- (EQNE:SI (match_operand:SI 1 "register_operand" "%r")
- (match_operand:SI 2 "arith_operand" "rI")))]
- ""
- "cmp<code>%i2\\t%0, %1, %z2"
- [(set_attr "type" "alu")])
-
-(define_code_iterator SCMP [ge lt])
-(define_insn "nios2_cmp<code>"
- [(set (match_operand:SI 0 "register_operand" "=r")
- (SCMP:SI (match_operand:SI 1 "reg_or_0_operand" "rM")
- (match_operand:SI 2 "arith_operand" "rI")))]
- ""
- "cmp<code>%i2\\t%0, %z1, %z2"
- [(set_attr "type" "alu")])
-
-(define_code_iterator UCMP [geu ltu])
-(define_insn "nios2_cmp<code>"
- [(set (match_operand:SI 0 "register_operand" "=r")
- (UCMP:SI (match_operand:SI 1 "reg_or_0_operand" "rM")
- (match_operand:SI 2 "uns_arith_operand" "rJ")))]
- ""
- "cmp<code>%u2\\t%0, %z1, %z2"
- [(set_attr "type" "alu")])
-
-
-
-;; Custom instruction patterns. The operands are intentionally
-;; mode-less, to serve as generic carriers of all Altera defined
-;; built-in instruction/function types.
-
-(define_insn "custom_nxx"
- [(unspec_volatile [(match_operand 0 "custom_insn_opcode" "N")
- (match_operand 1 "reg_or_0_operand" "rM")
- (match_operand 2 "reg_or_0_operand" "rM")]
- UNSPECV_CUSTOM_NXX)]
- ""
- "custom\\t%0, zero, %z1, %z2"
- [(set_attr "type" "custom")])
-
-(define_insn "custom_xnxx"
- [(set (match_operand 0 "register_operand" "=r")
- (unspec_volatile [(match_operand 1 "custom_insn_opcode" "N")
- (match_operand 2 "reg_or_0_operand" "rM")
- (match_operand 3 "reg_or_0_operand" "rM")]
- UNSPECV_CUSTOM_XNXX))]
- ""
- "custom\\t%1, %0, %z2, %z3"
- [(set_attr "type" "custom")])
-
-
-;; Misc. patterns
-
-(define_insn "nop"
- [(const_int 0)]
- ""
- "nop%."
- [(set_attr "type" "nop")])
-
-;; Connect 'sync' to 'memory_barrier' standard expand name
-(define_expand "memory_barrier"
- [(const_int 0)]
- ""
-{
- emit_insn (gen_sync ());
- DONE;
-})
-
-;; For the nios2 __builtin_sync built-in function
-(define_expand "sync"
- [(set (match_dup 0)
- (unspec:BLK [(match_dup 0)] UNSPEC_SYNC))]
- ""
-{
- operands[0] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
- MEM_VOLATILE_P (operands[0]) = 1;
-})
-
-(define_insn "*sync_insn"
- [(set (match_operand:BLK 0 "" "")
- (unspec:BLK [(match_dup 0)] UNSPEC_SYNC))]
- ""
- "sync"
- [(set_attr "type" "control")])
-
-(define_insn "rdctl"
- [(set (match_operand:SI 0 "register_operand" "=r")
- (unspec_volatile:SI [(match_operand:SI 1 "rdwrctl_operand" "O")]
- UNSPECV_RDCTL))]
- ""
- "rdctl\\t%0, ctl%1"
- [(set_attr "type" "control")])
-
-(define_insn "wrctl"
- [(unspec_volatile:SI [(match_operand:SI 0 "rdwrctl_operand" "O")
- (match_operand:SI 1 "reg_or_0_operand" "rM")]
- UNSPECV_WRCTL)]
- ""
- "wrctl\\tctl%0, %z1"
- [(set_attr "type" "control")])
-
-(define_insn "rdprs"
- [(set (match_operand:SI 0 "register_operand" "=r")
- (unspec_volatile:SI [(match_operand:SI 1 "rdwrctl_operand" "O")
- (match_operand:SI 2 "arith_operand" "U")]
- UNSPECV_RDPRS))]
- ""
- "rdprs\\t%0, %1, %2"
- [(set_attr "type" "control")])
-
-;; Cache Instructions
-
-(define_insn "flushd"
- [(unspec_volatile:SI [(match_operand:SI 0 "ldstio_memory_operand" "w")]
- UNSPECV_FLUSHD)]
- ""
- "flushd\\t%0"
- [(set_attr "type" "control")])
-
-(define_insn "flushda"
- [(unspec_volatile:SI [(match_operand:SI 0 "ldstio_memory_operand" "w")]
- UNSPECV_FLUSHDA)]
- ""
- "flushda\\t%0"
- [(set_attr "type" "control")])
-
-;; R2 Instructions
-
-(define_insn "wrpie"
- [(set (match_operand:SI 0 "register_operand" "=r")
- (unspec_volatile:SI [(match_operand:SI 1 "register_operand" "r")]
- UNSPECV_WRPIE))]
- "TARGET_ARCH_R2"
- "wrpie\\t%0, %1"
- [(set_attr "type" "control")])
-
-(define_insn "eni"
- [(unspec:VOID [(match_operand 0 "const_int_operand" "i")]
- UNSPECV_ENI)]
- "TARGET_ARCH_R2"
- "eni\\t%0"
- [(set_attr "type" "control")])
-
-;; Trap patterns
-(define_insn "trap"
- [(trap_if (const_int 1) (const_int 3))]
- ""
- "trap%.\\t3"
- [(set_attr "type" "control")])
-
-(define_insn "ctrapsi4"
- [(trap_if (match_operator 0 "ordered_comparison_operator"
- [(match_operand:SI 1 "reg_or_0_operand" "rM")
- (match_operand:SI 2 "reg_or_0_operand" "rM")])
- (match_operand 3 "const_int_operand" "i"))]
- ""
-{
- if (get_attr_length (insn) == 6)
- return "b%R0\\t%z1, %z2, 1f\;trap.n\\t%3\;1:";
- else
- return "b%R0\\t%z1, %z2, 1f\;trap\\t%3\;1:";
-}
- [(set_attr "type" "control")
- (set (attr "length")
- (if_then_else (match_test "nios2_cdx_narrow_form_p (insn)")
- (const_int 6) (const_int 8)))])
-
-;; Load the GOT register.
-(define_insn "load_got_register"
- [(set (match_operand:SI 0 "register_operand" "=&r")
- (unspec:SI [(const_int 0)] UNSPEC_LOAD_GOT_REGISTER))
- (set (match_operand:SI 1 "register_operand" "=r")
- (unspec:SI [(const_int 0)] UNSPEC_LOAD_GOT_REGISTER))]
- ""
- "nextpc\\t%0
-\\t1:
-\\tmovhi\\t%1, %%hiadj(_gp_got - 1b)
-\\taddi\\t%1, %1, %%lo(_gp_got - 1b)"
- [(set_attr "length" "12")])
-
-;; Read thread pointer register
-(define_expand "get_thread_pointersi"
- [(match_operand:SI 0 "register_operand" "=r")]
- "TARGET_LINUX_ABI"
-{
- emit_move_insn (operands[0], gen_rtx_REG (Pmode, TP_REGNO));
- DONE;
-})
-
-;; Synchronization Primitives
-(include "sync.md")
-
-;; Include the ldwm/stwm/push.n/pop.n patterns and peepholes.
-(include "ldstwm.md")
-
diff --git a/gcc/config/nios2/nios2.opt b/gcc/config/nios2/nios2.opt
deleted file mode 100644
index 53df5b764774..000000000000
--- a/gcc/config/nios2/nios2.opt
+++ /dev/null
@@ -1,596 +0,0 @@
-; Options for the Altera Nios II port of the compiler.
-; Copyright (C) 2012-2024 Free Software Foundation, Inc.
-; Contributed by Altera and Mentor Graphics, Inc.
-;
-; This file is part of GCC.
-;
-; GCC is free software; you can redistribute it and/or modify
-; it under the terms of the GNU General Public License as published by
-; the Free Software Foundation; either version 3, or (at your option)
-; any later version.
-;
-; GCC is distributed in the hope that it will be useful,
-; but WITHOUT ANY WARRANTY; without even the implied warranty of
-; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-; GNU General Public License for more details.
-;
-; You should have received a copy of the GNU General Public License
-; along with GCC; see the file COPYING3. If not see
-; <http://www.gnu.org/licenses/>.
-
-HeaderInclude
-config/nios2/nios2-opts.h
-
-TargetSave
-int saved_fpu_custom_code[n2fpu_code_num]
-
-TargetSave
-enum nios2_ccs_code saved_custom_code_status[256]
-
-TargetSave
-int saved_custom_code_index[256]
-
-mhw-div
-Target Mask(HAS_DIV)
-Enable DIV, DIVU.
-
-mhw-mul
-Target Mask(HAS_MUL)
-Enable MUL instructions.
-
-mhw-mulx
-Target Mask(HAS_MULX)
-Enable MULX instructions, assume fast shifter.
-
-mfast-sw-div
-Target Mask(FAST_SW_DIV)
-Use table based fast divide (default at -O3).
-
-mbypass-cache
-Target Mask(BYPASS_CACHE)
-All memory accesses use I/O load/store instructions.
-
-mno-cache-volatile
-Target RejectNegative Mask(BYPASS_CACHE_VOLATILE)
-Volatile memory accesses use I/O load/store instructions.
-
-mcache-volatile
-Target RejectNegative Undocumented InverseMask(BYPASS_CACHE_VOLATILE)
-Volatile memory accesses do not use I/O load/store instructions.
-
-mgpopt=
-Target RejectNegative Joined Enum(nios2_gpopt_type) Var(nios2_gpopt_option) Init(gpopt_unspecified)
-Enable/disable GP-relative addressing.
-
-Enum
-Name(nios2_gpopt_type) Type(enum nios2_gpopt_type)
-Valid options for GP-relative addressing (for -mgpopt):
-
-EnumValue
-Enum(nios2_gpopt_type) String(none) Value(gpopt_none)
-
-EnumValue
-Enum(nios2_gpopt_type) String(local) Value(gpopt_local)
-
-EnumValue
-Enum(nios2_gpopt_type) String(global) Value(gpopt_global)
-
-EnumValue
-Enum(nios2_gpopt_type) String(data) Value(gpopt_data)
-
-EnumValue
-Enum(nios2_gpopt_type) String(all) Value(gpopt_all)
-
-mgpopt
-Target RejectNegative Var(nios2_gpopt_option, gpopt_local)
-Equivalent to -mgpopt=local.
-
-mno-gpopt
-Target RejectNegative Var(nios2_gpopt_option, gpopt_none)
-Equivalent to -mgpopt=none.
-
-meb
-Target RejectNegative Mask(BIG_ENDIAN)
-Use big-endian byte order.
-
-mel
-Target RejectNegative InverseMask(BIG_ENDIAN)
-Use little-endian byte order.
-
-mcustom-fpu-cfg=
-Target RejectNegative Joined Var(nios2_custom_fpu_cfg_string)
-Floating point custom instruction configuration name.
-
-mno-custom-ftruncds
-Target RejectNegative Var(nios2_custom_ftruncds, -1)
-Do not use the ftruncds custom instruction.
-
-mcustom-ftruncds=
-Target RejectNegative Joined UInteger Var(nios2_custom_ftruncds) Init(-1)
-Integer id (N) of ftruncds custom instruction.
-
-mno-custom-fextsd
-Target RejectNegative Var(nios2_custom_fextsd, -1)
-Do not use the fextsd custom instruction.
-
-mcustom-fextsd=
-Target RejectNegative Joined UInteger Var(nios2_custom_fextsd) Init(-1)
-Integer id (N) of fextsd custom instruction.
-
-mno-custom-fixdu
-Target RejectNegative Var(nios2_custom_fixdu, -1)
-Do not use the fixdu custom instruction.
-
-mcustom-fixdu=
-Target RejectNegative Joined UInteger Var(nios2_custom_fixdu) Init(-1)
-Integer id (N) of fixdu custom instruction.
-
-mno-custom-fixdi
-Target RejectNegative Var(nios2_custom_fixdi, -1)
-Do not use the fixdi custom instruction.
-
-mcustom-fixdi=
-Target RejectNegative Joined UInteger Var(nios2_custom_fixdi) Init(-1)
-Integer id (N) of fixdi custom instruction.
-
-mno-custom-fixsu
-Target RejectNegative Var(nios2_custom_fixsu, -1)
-Do not use the fixsu custom instruction.
-
-mcustom-fixsu=
-Target RejectNegative Joined UInteger Var(nios2_custom_fixsu) Init(-1)
-Integer id (N) of fixsu custom instruction.
-
-mno-custom-fixsi
-Target RejectNegative Var(nios2_custom_fixsi, -1)
-Do not use the fixsi custom instruction.
-
-mcustom-fixsi=
-Target RejectNegative Joined UInteger Var(nios2_custom_fixsi) Init(-1)
-Integer id (N) of fixsi custom instruction.
-
-mno-custom-floatud
-Target RejectNegative Var(nios2_custom_floatud, -1)
-Do not use the floatud custom instruction.
-
-mcustom-floatud=
-Target RejectNegative Joined UInteger Var(nios2_custom_floatud) Init(-1)
-Integer id (N) of floatud custom instruction.
-
-mno-custom-floatid
-Target RejectNegative Var(nios2_custom_floatid, -1)
-Do not use the floatid custom instruction.
-
-mcustom-floatid=
-Target RejectNegative Joined UInteger Var(nios2_custom_floatid) Init(-1)
-Integer id (N) of floatid custom instruction.
-
-mno-custom-floatus
-Target RejectNegative Var(nios2_custom_floatus, -1)
-Do not use the floatus custom instruction.
-
-mcustom-floatus=
-Target RejectNegative Joined UInteger Var(nios2_custom_floatus) Init(-1)
-Integer id (N) of floatus custom instruction.
-
-mno-custom-floatis
-Target RejectNegative Var(nios2_custom_floatis, -1)
-Do not use the floatis custom instruction.
-
-mcustom-floatis=
-Target RejectNegative Joined UInteger Var(nios2_custom_floatis) Init(-1)
-Integer id (N) of floatis custom instruction.
-
-mno-custom-fcmpned
-Target RejectNegative Var(nios2_custom_fcmpned, -1)
-Do not use the fcmpned custom instruction.
-
-mcustom-fcmpned=
-Target RejectNegative Joined UInteger Var(nios2_custom_fcmpned) Init(-1)
-Integer id (N) of fcmpned custom instruction.
-
-mno-custom-fcmpeqd
-Target RejectNegative Var(nios2_custom_fcmpeqd, -1)
-Do not use the fcmpeqd custom instruction.
-
-mcustom-fcmpeqd=
-Target RejectNegative Joined UInteger Var(nios2_custom_fcmpeqd) Init(-1)
-Integer id (N) of fcmpeqd custom instruction.
-
-mno-custom-fcmpged
-Target RejectNegative Var(nios2_custom_fcmpged, -1)
-Do not use the fcmpged custom instruction.
-
-mcustom-fcmpged=
-Target RejectNegative Joined UInteger Var(nios2_custom_fcmpged) Init(-1)
-Integer id (N) of fcmpged custom instruction.
-
-mno-custom-fcmpgtd
-Target RejectNegative Var(nios2_custom_fcmpgtd, -1)
-Do not use the fcmpgtd custom instruction.
-
-mcustom-fcmpgtd=
-Target RejectNegative Joined UInteger Var(nios2_custom_fcmpgtd) Init(-1)
-Integer id (N) of fcmpgtd custom instruction.
-
-mno-custom-fcmpled
-Target RejectNegative Var(nios2_custom_fcmpled, -1)
-Do not use the fcmpled custom instruction.
-
-mcustom-fcmpled=
-Target RejectNegative Joined UInteger Var(nios2_custom_fcmpled) Init(-1)
-Integer id (N) of fcmpled custom instruction.
-
-mno-custom-fcmpltd
-Target RejectNegative Var(nios2_custom_fcmpltd, -1)
-Do not use the fcmpltd custom instruction.
-
-mcustom-fcmpltd=
-Target RejectNegative Joined UInteger Var(nios2_custom_fcmpltd) Init(-1)
-Integer id (N) of fcmpltd custom instruction.
-
-mno-custom-flogd
-Target RejectNegative Var(nios2_custom_flogd, -1)
-Do not use the flogd custom instruction.
-
-mcustom-flogd=
-Target RejectNegative Joined UInteger Var(nios2_custom_flogd) Init(-1)
-Integer id (N) of flogd custom instruction.
-
-mno-custom-fexpd
-Target RejectNegative Var(nios2_custom_fexpd, -1)
-Do not use the fexpd custom instruction.
-
-mcustom-fexpd=
-Target RejectNegative Joined UInteger Var(nios2_custom_fexpd) Init(-1)
-Integer id (N) of fexpd custom instruction.
-
-mno-custom-fatand
-Target RejectNegative Var(nios2_custom_fatand, -1)
-Do not use the fatand custom instruction.
-
-mcustom-fatand=
-Target RejectNegative Joined UInteger Var(nios2_custom_fatand) Init(-1)
-Integer id (N) of fatand custom instruction.
-
-mno-custom-ftand
-Target RejectNegative Var(nios2_custom_ftand, -1)
-Do not use the ftand custom instruction.
-
-mcustom-ftand=
-Target RejectNegative Joined UInteger Var(nios2_custom_ftand) Init(-1)
-Integer id (N) of ftand custom instruction.
-
-mno-custom-fsind
-Target RejectNegative Var(nios2_custom_fsind, -1)
-Do not use the fsind custom instruction.
-
-mcustom-fsind=
-Target RejectNegative Joined UInteger Var(nios2_custom_fsind) Init(-1)
-Integer id (N) of fsind custom instruction.
-
-mno-custom-fcosd
-Target RejectNegative Var(nios2_custom_fcosd, -1)
-Do not use the fcosd custom instruction.
-
-mcustom-fcosd=
-Target RejectNegative Joined UInteger Var(nios2_custom_fcosd) Init(-1)
-Integer id (N) of fcosd custom instruction.
-
-mno-custom-fsqrtd
-Target RejectNegative Var(nios2_custom_fsqrtd, -1)
-Do not use the fsqrtd custom instruction.
-
-mcustom-fsqrtd=
-Target RejectNegative Joined UInteger Var(nios2_custom_fsqrtd) Init(-1)
-Integer id (N) of fsqrtd custom instruction.
-
-mno-custom-fabsd
-Target RejectNegative Var(nios2_custom_fabsd, -1)
-Do not use the fabsd custom instruction.
-
-mcustom-fabsd=
-Target RejectNegative Joined UInteger Var(nios2_custom_fabsd) Init(-1)
-Integer id (N) of fabsd custom instruction.
-
-mno-custom-fnegd
-Target RejectNegative Var(nios2_custom_fnegd, -1)
-Do not use the fnegd custom instruction.
-
-mcustom-fnegd=
-Target RejectNegative Joined UInteger Var(nios2_custom_fnegd) Init(-1)
-Integer id (N) of fnegd custom instruction.
-
-mno-custom-fmaxd
-Target RejectNegative Var(nios2_custom_fmaxd, -1)
-Do not use the fmaxd custom instruction.
-
-mcustom-fmaxd=
-Target RejectNegative Joined UInteger Var(nios2_custom_fmaxd) Init(-1)
-Integer id (N) of fmaxd custom instruction.
-
-mno-custom-fmind
-Target RejectNegative Var(nios2_custom_fmind, -1)
-Do not use the fmind custom instruction.
-
-mcustom-fmind=
-Target RejectNegative Joined UInteger Var(nios2_custom_fmind) Init(-1)
-Integer id (N) of fmind custom instruction.
-
-mno-custom-fdivd
-Target RejectNegative Var(nios2_custom_fdivd, -1)
-Do not use the fdivd custom instruction.
-
-mcustom-fdivd=
-Target RejectNegative Joined UInteger Var(nios2_custom_fdivd) Init(-1)
-Integer id (N) of fdivd custom instruction.
-
-mno-custom-fmuld
-Target RejectNegative Var(nios2_custom_fmuld, -1)
-Do not use the fmuld custom instruction.
-
-mcustom-fmuld=
-Target RejectNegative Joined UInteger Var(nios2_custom_fmuld) Init(-1)
-Integer id (N) of fmuld custom instruction.
-
-mno-custom-fsubd
-Target RejectNegative Var(nios2_custom_fsubd, -1)
-Do not use the fsubd custom instruction.
-
-mcustom-fsubd=
-Target RejectNegative Joined UInteger Var(nios2_custom_fsubd) Init(-1)
-Integer id (N) of fsubd custom instruction.
-
-mno-custom-faddd
-Target RejectNegative Var(nios2_custom_faddd, -1)
-Do not use the faddd custom instruction.
-
-mcustom-faddd=
-Target RejectNegative Joined UInteger Var(nios2_custom_faddd) Init(-1)
-Integer id (N) of faddd custom instruction.
-
-mno-custom-fcmpnes
-Target RejectNegative Var(nios2_custom_fcmpnes, -1)
-Do not use the fcmpnes custom instruction.
-
-mcustom-fcmpnes=
-Target RejectNegative Joined UInteger Var(nios2_custom_fcmpnes) Init(-1)
-Integer id (N) of fcmpnes custom instruction.
-
-mno-custom-fcmpeqs
-Target RejectNegative Var(nios2_custom_fcmpeqs, -1)
-Do not use the fcmpeqs custom instruction.
-
-mcustom-fcmpeqs=
-Target RejectNegative Joined UInteger Var(nios2_custom_fcmpeqs) Init(-1)
-Integer id (N) of fcmpeqs custom instruction.
-
-mno-custom-fcmpges
-Target RejectNegative Var(nios2_custom_fcmpges, -1)
-Do not use the fcmpges custom instruction.
-
-mcustom-fcmpges=
-Target RejectNegative Joined UInteger Var(nios2_custom_fcmpges) Init(-1)
-Integer id (N) of fcmpges custom instruction.
-
-mno-custom-fcmpgts
-Target RejectNegative Var(nios2_custom_fcmpgts, -1)
-Do not use the fcmpgts custom instruction.
-
-mcustom-fcmpgts=
-Target RejectNegative Joined UInteger Var(nios2_custom_fcmpgts) Init(-1)
-Integer id (N) of fcmpgts custom instruction.
-
-mno-custom-fcmples
-Target RejectNegative Var(nios2_custom_fcmples, -1)
-Do not use the fcmples custom instruction.
-
-mcustom-fcmples=
-Target RejectNegative Joined UInteger Var(nios2_custom_fcmples) Init(-1)
-Integer id (N) of fcmples custom instruction.
-
-mno-custom-fcmplts
-Target RejectNegative Var(nios2_custom_fcmplts, -1)
-Do not use the fcmplts custom instruction.
-
-mcustom-fcmplts=
-Target RejectNegative Joined UInteger Var(nios2_custom_fcmplts) Init(-1)
-Integer id (N) of fcmplts custom instruction.
-
-mno-custom-flogs
-Target RejectNegative Var(nios2_custom_flogs, -1)
-Do not use the flogs custom instruction.
-
-mcustom-flogs=
-Target RejectNegative Joined UInteger Var(nios2_custom_flogs) Init(-1)
-Integer id (N) of flogs custom instruction.
-
-mno-custom-fexps
-Target RejectNegative Var(nios2_custom_fexps, -1)
-Do not use the fexps custom instruction.
-
-mcustom-fexps=
-Target RejectNegative Joined UInteger Var(nios2_custom_fexps) Init(-1)
-Integer id (N) of fexps custom instruction.
-
-mno-custom-fatans
-Target RejectNegative Var(nios2_custom_fatans, -1)
-Do not use the fatans custom instruction.
-
-mcustom-fatans=
-Target RejectNegative Joined UInteger Var(nios2_custom_fatans) Init(-1)
-Integer id (N) of fatans custom instruction.
-
-mno-custom-ftans
-Target RejectNegative Var(nios2_custom_ftans, -1)
-Do not use the ftans custom instruction.
-
-mcustom-ftans=
-Target RejectNegative Joined UInteger Var(nios2_custom_ftans) Init(-1)
-Integer id (N) of ftans custom instruction.
-
-mno-custom-fsins
-Target RejectNegative Var(nios2_custom_fsins, -1)
-Do not use the fsins custom instruction.
-
-mcustom-fsins=
-Target RejectNegative Joined UInteger Var(nios2_custom_fsins) Init(-1)
-Integer id (N) of fsins custom instruction.
-
-mno-custom-fcoss
-Target RejectNegative Var(nios2_custom_fcoss, -1)
-Do not use the fcoss custom instruction.
-
-mcustom-fcoss=
-Target RejectNegative Joined UInteger Var(nios2_custom_fcoss) Init(-1)
-Integer id (N) of fcoss custom instruction.
-
-mno-custom-fsqrts
-Target RejectNegative Var(nios2_custom_fsqrts, -1)
-Do not use the fsqrts custom instruction.
-
-mcustom-fsqrts=
-Target RejectNegative Joined UInteger Var(nios2_custom_fsqrts) Init(-1)
-Integer id (N) of fsqrts custom instruction.
-
-mno-custom-fabss
-Target RejectNegative Var(nios2_custom_fabss, -1)
-Do not use the fabss custom instr.
-
-mcustom-fabss=
-Target RejectNegative Joined UInteger Var(nios2_custom_fabss) Init(-1)
-Integer id (N) of fabss custom instruction.
-
-mno-custom-fnegs
-Target RejectNegative Var(nios2_custom_fnegs, -1)
-Do not use the fnegs custom instruction.
-
-mcustom-fnegs=
-Target RejectNegative Joined UInteger Var(nios2_custom_fnegs) Init(-1)
-Integer id (N) of fnegs custom instruction.
-
-mno-custom-fmaxs
-Target RejectNegative Var(nios2_custom_fmaxs, -1)
-Do not use the fmaxs custom instruction.
-
-mcustom-fmaxs=
-Target RejectNegative Joined UInteger Var(nios2_custom_fmaxs) Init(-1)
-Integer id (N) of fmaxs custom instruction.
-
-mno-custom-fmins
-Target RejectNegative Var(nios2_custom_fmins, -1)
-Do not use the fmins custom instruction.
-
-mcustom-fmins=
-Target RejectNegative Joined UInteger Var(nios2_custom_fmins) Init(-1)
-Integer id (N) of fmins custom instruction.
-
-mno-custom-fdivs
-Target RejectNegative Var(nios2_custom_fdivs, -1)
-Do not use the fdivs custom instruction.
-
-mcustom-fdivs=
-Target RejectNegative Joined UInteger Var(nios2_custom_fdivs) Init(-1)
-Integer id (N) of fdivs custom instruction.
-
-mno-custom-fmuls
-Target RejectNegative Var(nios2_custom_fmuls, -1)
-Do not use the fmuls custom instruction.
-
-mcustom-fmuls=
-Target RejectNegative Joined UInteger Var(nios2_custom_fmuls) Init(-1)
-Integer id (N) of fmuls custom instruction.
-
-mno-custom-fsubs
-Target RejectNegative Var(nios2_custom_fsubs, -1)
-Do not use the fsubs custom instruction.
-
-mcustom-fsubs=
-Target RejectNegative Joined UInteger Var(nios2_custom_fsubs) Init(-1)
-Integer id (N) of fsubs custom instruction.
-
-mno-custom-fadds
-Target RejectNegative Var(nios2_custom_fadds, -1)
-Do not use the fadds custom instruction.
-
-mcustom-fadds=
-Target RejectNegative Joined UInteger Var(nios2_custom_fadds) Init(-1)
-Integer id (N) of fadds custom instruction.
-
-mno-custom-frdy
-Target RejectNegative Var(nios2_custom_frdy, -1)
-Do not use the frdy custom instruction.
-
-mcustom-frdy=
-Target RejectNegative Joined UInteger Var(nios2_custom_frdy) Init(-1)
-Integer id (N) of frdy custom instruction.
-
-mno-custom-frdxhi
-Target RejectNegative Var(nios2_custom_frdxhi, -1)
-Do not use the frdxhi custom instruction.
-
-mcustom-frdxhi=
-Target RejectNegative Joined UInteger Var(nios2_custom_frdxhi) Init(-1)
-Integer id (N) of frdxhi custom instruction.
-
-mno-custom-frdxlo
-Target RejectNegative Var(nios2_custom_frdxlo, -1)
-Do not use the frdxlo custom instruction.
-
-mcustom-frdxlo=
-Target RejectNegative Joined UInteger Var(nios2_custom_frdxlo) Init(-1)
-Integer id (N) of frdxlo custom instruction.
-
-mno-custom-fwry
-Target RejectNegative Var(nios2_custom_fwry, -1)
-Do not use the fwry custom instruction.
-
-mcustom-fwry=
-Target RejectNegative Joined UInteger Var(nios2_custom_fwry) Init(-1)
-Integer id (N) of fwry custom instruction.
-
-mno-custom-fwrx
-Target RejectNegative Var(nios2_custom_fwrx, -1)
-Do not use the fwrx custom instruction.
-
-mcustom-fwrx=
-Target RejectNegative Joined UInteger Var(nios2_custom_fwrx) Init(-1)
-Integer id (N) of fwrx custom instruction.
-
-mno-custom-round
-Target RejectNegative Var(nios2_custom_round, -1)
-Do not use the round custom instruction.
-
-mcustom-round=
-Target RejectNegative Joined UInteger Var(nios2_custom_round) Init(-1)
-Integer id (N) of round custom instruction.
-
-march=
-Target RejectNegative Joined Enum(nios2_arch_type) Var(nios2_arch_option) Init(ARCH_R1)
-Specify the name of the target architecture.
-
-Enum
-Name(nios2_arch_type) Type(enum nios2_arch_type)
-Valid Nios II ISA levels (for -march):
-
-EnumValue
-Enum(nios2_arch_type) String(r1) Value(ARCH_R1)
-
-EnumValue
-Enum(nios2_arch_type) String(r2) Value(ARCH_R2)
-
-mbmx
-Target Mask(HAS_BMX)
-Enable generation of R2 BMX instructions.
-
-mcdx
-Target Mask(HAS_CDX)
-Enable generation of R2 CDX instructions.
-
-mgprel-sec=
-Target RejectNegative Joined Var(nios2_gprel_sec) Init(NULL)
-Regular expression matching additional GP-addressible section names.
-
-mr0rel-sec=
-Target RejectNegative Joined Var(nios2_r0rel_sec) Init(NULL)
-Regular expression matching section names for r0-relative addressing.
diff --git a/gcc/config/nios2/nios2.opt.urls b/gcc/config/nios2/nios2.opt.urls
deleted file mode 100644
index a38ea285a6e2..000000000000
--- a/gcc/config/nios2/nios2.opt.urls
+++ /dev/null
@@ -1,50 +0,0 @@
-; Autogenerated by regenerate-opt-urls.py from gcc/config/nios2/nios2.opt and generated HTML
-
-mhw-div
-UrlSuffix(gcc/Nios-II-Options.html#index-mhw-div)
-
-mhw-mul
-UrlSuffix(gcc/Nios-II-Options.html#index-mhw-mul)
-
-mhw-mulx
-UrlSuffix(gcc/Nios-II-Options.html#index-mhw-mulx)
-
-mfast-sw-div
-UrlSuffix(gcc/Nios-II-Options.html#index-mfast-sw-div)
-
-mbypass-cache
-UrlSuffix(gcc/Nios-II-Options.html#index-mbypass-cache)
-
-mno-cache-volatile
-UrlSuffix(gcc/Nios-II-Options.html#index-mno-cache-volatile)
-
-mcache-volatile
-UrlSuffix(gcc/Nios-II-Options.html#index-mcache-volatile)
-
-mgpopt=
-UrlSuffix(gcc/Nios-II-Options.html#index-mgpopt-1)
-
-mgpopt
-UrlSuffix(gcc/Nios-II-Options.html#index-mgpopt-1)
-
-mno-gpopt
-UrlSuffix(gcc/Nios-II-Options.html#index-mno-gpopt-1)
-
-meb
-UrlSuffix(gcc/Nios-II-Options.html#index-meb-1)
-
-mel
-UrlSuffix(gcc/Nios-II-Options.html#index-mel-1)
-
-mcustom-fpu-cfg=
-UrlSuffix(gcc/Nios-II-Options.html#index-mcustom-fpu-cfg)
-
-march=
-UrlSuffix(gcc/Nios-II-Options.html#index-march-11)
-
-mgprel-sec=
-UrlSuffix(gcc/Nios-II-Options.html#index-mgprel-sec)
-
-mr0rel-sec=
-UrlSuffix(gcc/Nios-II-Options.html#index-mr0rel-sec)
-
diff --git a/gcc/config/nios2/predicates.md b/gcc/config/nios2/predicates.md
deleted file mode 100644
index 2b138ded5b9d..000000000000
--- a/gcc/config/nios2/predicates.md
+++ /dev/null
@@ -1,161 +0,0 @@
-;; Predicate definitions for Altera Nios II.
-;; Copyright (C) 2012-2024 Free Software Foundation, Inc.
-;; Contributed by Chung-Lin Tang <cltang@codesourcery.com>
-;;
-;; This file is part of GCC.
-;;
-;; GCC is free software; you can redistribute it and/or modify
-;; it under the terms of the GNU General Public License as published by
-;; the Free Software Foundation; either version 3, or (at your option)
-;; any later version.
-;;
-;; GCC is distributed in the hope that it will be useful,
-;; but WITHOUT ANY WARRANTY; without even the implied warranty of
-;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-;; GNU General Public License for more details.
-;;
-;; You should have received a copy of the GNU General Public License
-;; along with GCC; see the file COPYING3. If not see
-;; <http://www.gnu.org/licenses/>.
-
-(define_predicate "const_0_operand"
- (and (match_code "const_int,const_double,const_vector")
- (match_test "op == CONST0_RTX (GET_MODE (op))")))
-
-(define_predicate "reg_or_0_operand"
- (ior (match_operand 0 "const_0_operand")
- (match_operand 0 "register_operand")))
-
-(define_predicate "const_uns_arith_operand"
- (and (match_code "const_int")
- (match_test "SMALL_INT_UNSIGNED (INTVAL (op))")))
-
-(define_predicate "uns_arith_operand"
- (ior (match_operand 0 "const_uns_arith_operand")
- (match_operand 0 "register_operand")))
-
-(define_predicate "const_arith_operand"
- (and (match_code "const_int")
- (match_test "SMALL_INT (INTVAL (op))")))
-
-(define_predicate "arith_operand"
- (ior (match_operand 0 "const_arith_operand")
- (match_operand 0 "register_operand")))
-
-(define_predicate "add_regimm_operand"
- (ior (match_operand 0 "arith_operand")
- (match_test "nios2_unspec_reloc_p (op)")))
-
-(define_predicate "const_logical_operand"
- (and (match_code "const_int")
- (match_test "(INTVAL (op) & 0xffff) == 0
- || (INTVAL (op) & 0xffff0000) == 0")))
-
-(define_predicate "logical_operand"
- (ior (match_operand 0 "const_logical_operand")
- (match_operand 0 "register_operand")))
-
-(define_predicate "const_and_operand"
- (and (match_code "const_int")
- (match_test "SMALL_INT_UNSIGNED (INTVAL (op))
- || UPPER16_INT (INTVAL (op))
- || (TARGET_ARCH_R2 && ANDCLEAR_INT (INTVAL (op)))")))
-
-(define_predicate "and_operand"
- (ior (match_operand 0 "const_and_operand")
- (match_operand 0 "register_operand")))
-
-(define_predicate "const_shift_operand"
- (and (match_code "const_int")
- (match_test "SHIFT_INT (INTVAL (op))")))
-
-(define_predicate "shift_operand"
- (ior (match_operand 0 "const_shift_operand")
- (match_operand 0 "register_operand")))
-
-(define_predicate "call_operand"
- (ior (match_operand 0 "immediate_operand")
- (match_operand 0 "register_operand")))
-
-(define_predicate "rdwrctl_operand"
- (and (match_code "const_int")
- (match_test "RDWRCTL_INT (INTVAL (op))")))
-
-(define_predicate "rdprs_dcache_operand"
- (and (match_code "const_int")
- (if_then_else (match_test "TARGET_ARCH_R2")
- (match_test "SMALL_INT12 (INTVAL (op))")
- (match_test "SMALL_INT (INTVAL (op))"))))
-
-(define_predicate "custom_insn_opcode"
- (and (match_code "const_int")
- (match_test "CUSTOM_INSN_OPCODE (INTVAL (op))")))
-
-(define_special_predicate "expandable_comparison_operator"
- (match_operand 0 "ordered_comparison_operator")
-{
- return (GET_MODE_CLASS (GET_MODE (XEXP (op, 0))) != MODE_FLOAT
- || nios2_validate_fpu_compare (GET_MODE (XEXP (op, 0)), &op,
- &XEXP (op, 0), &XEXP (op, 1),
- false));
-})
-
-(define_special_predicate "pop_operation"
- (match_code "parallel")
-{
- return pop_operation_p (op);
-})
-
-(define_special_predicate "ldwm_operation"
- (match_code "parallel")
-{
- return ldstwm_operation_p (op, /*load_p=*/true);
-})
-
-(define_special_predicate "stwm_operation"
- (match_code "parallel")
-{
- return ldstwm_operation_p (op, /*load_p=*/false);
-})
-
-(define_predicate "nios2_hard_register_operand"
- (match_code "reg")
-{
- return GP_REG_P (REGNO (op));
-})
-
-(define_predicate "stack_memory_operand"
- (match_code "mem")
-{
- rtx addr = XEXP (op, 0);
- return ((REG_P (addr) && REGNO (addr) == SP_REGNO)
- || (GET_CODE (addr) == PLUS
- && REG_P (XEXP (addr, 0)) && REGNO (XEXP (addr, 0)) == SP_REGNO
- && CONST_INT_P (XEXP (addr, 1))));
-})
-
-(define_predicate "ldstio_memory_operand"
- (match_code "mem")
-{
- if (TARGET_ARCH_R2)
- {
- rtx addr = XEXP (op, 0);
- if (REG_P (addr))
- return true;
- else if (GET_CODE (addr) == PLUS)
- return (REG_P (XEXP (addr, 0))
- && CONST_INT_P (XEXP (addr, 1))
- && SMALL_INT12 (INTVAL (XEXP (addr, 1))));
- else if (CONST_INT_P (addr))
- return SMALL_INT12 (INTVAL (addr));
- return false;
- }
- return memory_operand (op, mode);
-})
-
-(define_predicate "ldstex_memory_operand"
- (match_code "mem")
-{
- /* ldex/ldsex/stex/stsex cannot handle memory addresses with offsets. */
- return GET_CODE (XEXP (op, 0)) == REG;
-})
diff --git a/gcc/config/nios2/rtems.h b/gcc/config/nios2/rtems.h
deleted file mode 100644
index fed9d42127fc..000000000000
--- a/gcc/config/nios2/rtems.h
+++ /dev/null
@@ -1,39 +0,0 @@
-/* Definitions for rtems targeting a NIOS2 using ELF.
- Copyright (C) 2011-2024 Free Software Foundation, Inc.
-
- Contributed by Chris Johns (chrisj@rtems.org).
-
- This file is part of GCC.
-
- GCC is free software; you can redistribute it and/or modify it
- under the terms of the GNU General Public License as published
- by the Free Software Foundation; either version 3, or (at your
- option) any later version.
-
- GCC is distributed in the hope that it will be useful, but WITHOUT
- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
- License for more details.
-
- Under Section 7 of GPL version 3, you are granted additional
- permissions described in the GCC Runtime Library Exception, version
- 3.1, as published by the Free Software Foundation.
-
- You should have received a copy of the GNU General Public License and
- a copy of the GCC Runtime Library Exception along with this program;
- see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
- <http://www.gnu.org/licenses/>. */
-
-/* Specify predefined symbols in preprocessor. */
-#define TARGET_OS_CPP_BUILTINS() \
-do { \
- builtin_define ("__rtems__"); \
- builtin_define ("__USE_INIT_FINI__"); \
- builtin_assert ("system=rtems"); \
-} while (0)
-
-/* This toolchain implements the ABI for Linux Systems documented in the
- Nios II Processor Reference Handbook.
-
- This is done so RTEMS targets have Thread Local Storage like Linux. */
-#define TARGET_LINUX_ABI 1
diff --git a/gcc/config/nios2/sync.md b/gcc/config/nios2/sync.md
deleted file mode 100644
index e919af7a4e34..000000000000
--- a/gcc/config/nios2/sync.md
+++ /dev/null
@@ -1,45 +0,0 @@
-;; Machine Description for Altera Nios II synchronization primitives.
-;; Copyright (C) 2014-2024 Free Software Foundation, Inc.
-;; Contributed by Mentor Graphics, Inc.
-;;
-;; This file is part of GCC.
-;;
-;; GCC is free software; you can redistribute it and/or modify
-;; it under the terms of the GNU General Public License as published by
-;; the Free Software Foundation; either version 3, or (at your option)
-;; any later version.
-;;
-;; GCC is distributed in the hope that it will be useful,
-;; but WITHOUT ANY WARRANTY; without even the implied warranty of
-;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-;; GNU General Public License for more details.
-;;
-;; You should have received a copy of the GNU General Public License
-;; along with GCC; see the file COPYING3. If not see
-;; <http://www.gnu.org/licenses/>.
-
-(define_int_iterator UNSPECV_LOAD_EXCLUSIVE [UNSPECV_LDEX UNSPECV_LDSEX])
-(define_int_attr load_exclusive [(UNSPECV_LDEX "ldex")
- (UNSPECV_LDSEX "ldsex")])
-(define_insn "<load_exclusive>"
- [(set (match_operand:SI 0 "register_operand" "=r")
- (unspec_volatile:SI
- [(match_operand:SI 1 "ldstex_memory_operand" "v")]
- UNSPECV_LOAD_EXCLUSIVE))]
- "TARGET_ARCH_R2"
- "<load_exclusive>\\t%0, %A1"
- [(set_attr "type" "ld")])
-
-(define_int_iterator UNSPECV_STORE_EXCLUSIVE [UNSPECV_STEX UNSPECV_STSEX])
-(define_int_attr store_exclusive [(UNSPECV_STEX "stex")
- (UNSPECV_STSEX "stsex")])
-(define_insn "<store_exclusive>"
- [(set (match_operand:SI 2 "register_operand" "=r")
- (unspec_volatile:SI [(const_int 0)] UNSPECV_STORE_EXCLUSIVE))
- (set (match_operand:SI 0 "ldstex_memory_operand" "=v")
- (unspec_volatile:SI
- [(match_operand:SI 1 "reg_or_0_operand" "rM")]
- UNSPECV_STORE_EXCLUSIVE))]
- "TARGET_ARCH_R2"
- "<store_exclusive>\\t%2, %z1, %A0"
- [(set_attr "type" "st")])
diff --git a/gcc/config/nios2/t-nios2 b/gcc/config/nios2/t-nios2
deleted file mode 100644
index 6c76c57d76cb..000000000000
--- a/gcc/config/nios2/t-nios2
+++ /dev/null
@@ -1,27 +0,0 @@
-# Target Makefile Fragment for Altera Nios II.
-# Copyright (C) 2013-2024 Free Software Foundation, Inc.
-# Contributed by Altera and Mentor Graphics, Inc.
-#
-# This file is part of GCC.
-#
-# GCC is free software; you can redistribute it and/or modify it
-# under the terms of the GNU General Public License as published
-# by the Free Software Foundation; either version 3, or (at your
-# option) any later version.
-#
-# GCC is distributed in the hope that it will be useful, but WITHOUT
-# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
-# or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
-# License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with GCC; see the file COPYING3. If not see
-# <http://www.gnu.org/licenses/>.
-
-# MULTILIB_OPTIONS = mno-hw-mul/mhw-mulx mcustom-fpu-cfg=60-1/mcustom-fpu-cfg=60-2
-# MULTILIB_DIRNAMES = nomul mulx fpu-60-1 fpu-60-2
-# MULTILIB_EXCEPTIONS =
-
-# MULTILIB_OPTIONS += EL/EB
-# MULTILIB_DIRNAMES += le be
-# MULTILIB_MATCHES += EL=mel EB=meb
diff --git a/gcc/config/nios2/t-rtems b/gcc/config/nios2/t-rtems
deleted file mode 100644
index beda8328bd21..000000000000
--- a/gcc/config/nios2/t-rtems
+++ /dev/null
@@ -1,23 +0,0 @@
-# Custom RTEMS multilibs
-
-# Reset all MULTILIB variables
-
-MULTILIB_OPTIONS =
-MULTILIB_DIRNAMES =
-MULTILIB_EXCEPTIONS =
-MULTILIB_REUSE =
-MULTILIB_MATCHES =
-MULTILIB_REQUIRED =
-
-# Enumeration of multilibs
-
-MULTILIB_OPTIONS += mhw-mul mhw-mulx mhw-div
-MULTILIB_DIRNAMES += mul mulx div
-
-MULTILIB_OPTIONS += mcustom-fadds=253 mcustom-fdivs=255 mcustom-fmuls=252 mcustom-fsubs=254 mcustom-fpu-cfg=fph2
-MULTILIB_DIRNAMES += fadds fdivs fmuls fsubs fph2
-
-MULTILIB_REQUIRED += mhw-mul
-MULTILIB_REQUIRED += mhw-mul/mhw-mulx/mhw-div
-MULTILIB_REQUIRED += mhw-mul/mhw-mulx/mhw-div/mcustom-fadds=253/mcustom-fdivs=255/mcustom-fmuls=252/mcustom-fsubs=254
-MULTILIB_REQUIRED += mhw-mul/mhw-mulx/mhw-div/mcustom-fpu-cfg=fph2
diff --git a/gcc/configure b/gcc/configure
index 70d6e37796db..019ded4ca5c5 100755
--- a/gcc/configure
+++ b/gcc/configure
@@ -27497,11 +27497,6 @@ foo:
move.l x@TLSLE(%a5),%a0'
tls_as_opt='--fatal-warnings'
;;
- nios2-*-*)
- conftest_s='
- .section ".tdata","awT",@progbits'
- tls_as_opt="--fatal-warnings"
- ;;
aarch64*-*-*)
conftest_s='
.section ".tdata","awT",%progbits
@@ -30776,43 +30771,6 @@ $as_echo "#define HAVE_NEWLIB_NANO_FORMATTED_IO 1" >>confdefs.h
fi
;;
- nios2-*-*)
- # Versions 2.33 and earlier lacked support for the %gotoff relocation
- # syntax that is documented in the ABI specification.
- { $as_echo "$as_me:${as_lineno-$LINENO}: checking assembler for support for %gotoff relocations in constant data" >&5
-$as_echo_n "checking assembler for support for %gotoff relocations in constant data... " >&6; }
-if ${gcc_cv_as_nios2_gotoff_relocation+:} false; then :
- $as_echo_n "(cached) " >&6
-else
- gcc_cv_as_nios2_gotoff_relocation=no
- if test x$gcc_cv_as != x; then
- $as_echo ' .extern foo
- .data
- .long %gotoff(foo)' > conftest.s
- if { ac_try='$gcc_cv_as $gcc_cv_as_flags -o conftest.o conftest.s >&5'
- { { eval echo "\"\$as_me\":${as_lineno-$LINENO}: \"$ac_try\""; } >&5
- (eval $ac_try) 2>&5
- ac_status=$?
- $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5
- test $ac_status = 0; }; }
- then
- gcc_cv_as_nios2_gotoff_relocation=yes
- else
- echo "configure: failed program was" >&5
- cat conftest.s >&5
- fi
- rm -f conftest.o conftest.s
- fi
-fi
-{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $gcc_cv_as_nios2_gotoff_relocation" >&5
-$as_echo "$gcc_cv_as_nios2_gotoff_relocation" >&6; }
-if test $gcc_cv_as_nios2_gotoff_relocation = yes; then
-
-$as_echo "#define HAVE_AS_NIOS2_GOTOFF_RELOCATION 1" >>confdefs.h
-
-fi
-
- ;;
riscv*-*-*)
{ $as_echo "$as_me:${as_lineno-$LINENO}: checking assembler for .attribute support" >&5
$as_echo_n "checking assembler for .attribute support... " >&6; }
@@ -31451,7 +31409,7 @@ esac
# version to the per-target configury.
case "$cpu_type" in
aarch64 | alpha | arc | arm | avr | bfin | cris | csky | i386 | loongarch | m32c \
- | m68k | microblaze | mips | nds32 | nios2 | pa | riscv | rs6000 | score | sparc \
+ | m68k | microblaze | mips | nds32 | pa | riscv | rs6000 | score | sparc \
| visium | xstormy16 | xtensa | ft32)
insn="nop"
;;
diff --git a/gcc/configure.ac b/gcc/configure.ac
index 00ff770d56b8..c546432b2775 100644
--- a/gcc/configure.ac
+++ b/gcc/configure.ac
@@ -3952,11 +3952,6 @@ foo:
move.l x@TLSLE(%a5),%a0'
tls_as_opt='--fatal-warnings'
;;
- nios2-*-*)
- conftest_s='
- .section ".tdata","awT",@progbits'
- tls_as_opt="--fatal-warnings"
- ;;
aarch64*-*-*)
conftest_s='
.section ".tdata","awT",%progbits
@@ -5438,17 +5433,6 @@ pointers into PC-relative form.])
configured with --enable-newlib-nano-formatted-io.])
fi
;;
- nios2-*-*)
- # Versions 2.33 and earlier lacked support for the %gotoff relocation
- # syntax that is documented in the ABI specification.
- gcc_GAS_CHECK_FEATURE([support for %gotoff relocations in constant data],
- gcc_cv_as_nios2_gotoff_relocation,,
-[ .extern foo
- .data
- .long %gotoff(foo)],,
- [AC_DEFINE(HAVE_AS_NIOS2_GOTOFF_RELOCATION, 1,
- [Define if your assembler supports %gotoff relocation syntax.])])
- ;;
riscv*-*-*)
gcc_GAS_CHECK_FEATURE([.attribute support],
gcc_cv_as_riscv_attribute,,
@@ -5618,7 +5602,7 @@ esac
# version to the per-target configury.
case "$cpu_type" in
aarch64 | alpha | arc | arm | avr | bfin | cris | csky | i386 | loongarch | m32c \
- | m68k | microblaze | mips | nds32 | nios2 | pa | riscv | rs6000 | score | sparc \
+ | m68k | microblaze | mips | nds32 | pa | riscv | rs6000 | score | sparc \
| visium | xstormy16 | xtensa | ft32)
insn="nop"
;;
diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi
index 59644606261c..df34cd1da309 100644
--- a/gcc/doc/extend.texi
+++ b/gcc/doc/extend.texi
@@ -2641,7 +2641,6 @@ GCC plugins may provide their own attributes.
* MIPS Function Attributes::
* MSP430 Function Attributes::
* NDS32 Function Attributes::
-* Nios II Function Attributes::
* Nvidia PTX Function Attributes::
* PowerPC Function Attributes::
* RISC-V Function Attributes::
@@ -4312,8 +4311,7 @@ within the strings.
The options supported are specific to each target; refer to @ref{x86
Function Attributes}, @ref{PowerPC Function Attributes},
@ref{ARM Function Attributes}, @ref{AArch64 Function Attributes},
-@ref{Nios II Function Attributes}, and @ref{S/390 Function Attributes}
-for details.
+and @ref{S/390 Function Attributes} for details.
@cindex @code{target_clones} function attribute
@item target_clones (@var{options})
@@ -6193,42 +6191,6 @@ Provide a user-defined function to handle warm reset exception.
@end table
@end table
-@node Nios II Function Attributes
-@subsection Nios II Function Attributes
-
-These function attributes are supported by the Nios II back end:
-
-@table @code
-@cindex @code{target} function attribute
-@item target (@var{options})
-As discussed in @ref{Common Function Attributes}, this attribute
-allows specification of target-specific compilation options.
-
-When compiling for Nios II, the following options are allowed:
-
-@table @samp
-@cindex @code{target("custom-@var{insn}=@var{N}")} function attribute, Nios II
-@cindex @code{target("no-custom-@var{insn}")} function attribute, Nios II
-@item custom-@var{insn}=@var{N}
-@itemx no-custom-@var{insn}
-Each @samp{custom-@var{insn}=@var{N}} attribute locally enables use of a
-custom instruction with encoding @var{N} when generating code that uses
-@var{insn}. Similarly, @samp{no-custom-@var{insn}} locally inhibits use of
-the custom instruction @var{insn}.
-These target attributes correspond to the
-@option{-mcustom-@var{insn}=@var{N}} and @option{-mno-custom-@var{insn}}
-command-line options, and support the same set of @var{insn} keywords.
-@xref{Nios II Options}, for more information.
-
-@cindex @code{target("custom-fpu-cfg=@var{name}")} function attribute, Nios II
-@item custom-fpu-cfg=@var{name}
-This attribute corresponds to the @option{-mcustom-fpu-cfg=@var{name}}
-command-line option, to select a predefined set of custom instructions
-named @var{name}.
-@xref{Nios II Options}, for more information.
-@end table
-@end table
-
@node Nvidia PTX Function Attributes
@subsection Nvidia PTX Function Attributes
@@ -16292,7 +16254,6 @@ instructions, but allow the compiler to schedule those calls.
@menu
* AArch64 Built-in Functions::
* Alpha Built-in Functions::
-* Altera Nios II Built-in Functions::
* ARC Built-in Functions::
* ARC SIMD Built-in Functions::
* ARM iWMMXt Built-in Functions::
@@ -16432,119 +[...]
[diff truncated at 524288 bytes]
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