[gcc r14-9265] [14 regression] Fix insn types in risc-v port
Jeff Law
law@gcc.gnu.org
Fri Mar 1 21:55:44 GMT 2024
https://gcc.gnu.org/g:b7b387e1200fd182599195979d5d21656fa8969d
commit r14-9265-gb7b387e1200fd182599195979d5d21656fa8969d
Author: Jeff Law <jlaw@ventanamicro.com>
Date: Fri Mar 1 14:54:04 2024 -0700
[14 regression] Fix insn types in risc-v port
So one of the broad goals we've had over the last few months has been to ensure
that every insn has a scheduling type and that every insn is associated with an
insn reservation in the scheduler.
This avoids some amazingly bad behavior in the scheduler. I won't go through
the gory details.
I was recently analyzing a code quality regression with dhrystone (ugh!) and
one of the issues was poor scheduling which lengthened the lifetime of a pseudo
and ultimately resulted in needing an additional callee saved register
save/restore.
This was ultimately tracked down incorrect types on a few patterns. So I did
an audit of all the patterns that had types added/changed as part of this
effort and found a variety of problems, primarily in the various move patterns
and extension patterns. This is a regression relative to gcc-13.
Naturally the change in types affects scheduling, which in turn changes the
precise code we generate and causes some testsuite fallout.
I considered updating the regexps since the change in the resulting output is
pretty consistent. But of course the test would still be sensitive to things
like load latency. So instead I just turned off the 2nd phase scheduler in the
affected tests.
Bootstrapped and regression tested on rv64gc-linux-gnu.
gcc
* config/riscv/riscv.md (zero_extendqi<SUPERQI:mode>2_internal): Fix
type attribute.
(extendsidi2_internal, movhf_hardfloat, movhf_softfloat): Likewise.
(movdi_32bit, movdi_64bit, movsi_internal): Likewise.
(movhi_internal, movqi_internal): Likewise.
(movsf_softfloat, movsf_hardfloat): Likewise.
(movdf_hardfloat_rv32, movdf_hardfloat_rv64): Likewise.
(movdf_softfloat): Likewise.
gcc/testsuite
* gcc.target/riscv/rvv/autovec/vls/calling-convention-1.c: Turn off
second phase scheduler.
* gcc.target/riscv/rvv/autovec/vls/calling-convention-2.c: Likewise.
* gcc.target/riscv/rvv/autovec/vls/calling-convention-3.c: Likewise.
* gcc.target/riscv/rvv/autovec/vls/calling-convention-4.c: Likewise.
* gcc.target/riscv/rvv/autovec/vls/calling-convention-5.c: Likewise.
* gcc.target/riscv/rvv/autovec/vls/calling-convention-6.c: Likewise.
* gcc.target/riscv/rvv/autovec/vls/calling-convention-7.c: Likewise.
Diff:
---
gcc/config/riscv/riscv.md | 28 +++++++++++-----------
.../riscv/rvv/autovec/vls/calling-convention-1.c | 2 +-
.../riscv/rvv/autovec/vls/calling-convention-2.c | 2 +-
.../riscv/rvv/autovec/vls/calling-convention-3.c | 2 +-
.../riscv/rvv/autovec/vls/calling-convention-4.c | 2 +-
.../riscv/rvv/autovec/vls/calling-convention-5.c | 2 +-
.../riscv/rvv/autovec/vls/calling-convention-6.c | 2 +-
.../riscv/rvv/autovec/vls/calling-convention-7.c | 2 +-
8 files changed, 21 insertions(+), 21 deletions(-)
diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index 1fec13092e2..b16ed97909c 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -1836,7 +1836,7 @@
andi\t%0,%1,0xff
lbu\t%0,%1"
[(set_attr "move_type" "andi,load")
- (set_attr "type" "multi")
+ (set_attr "type" "arith,load")
(set_attr "mode" "<SUPERQI:MODE>")])
;;
@@ -1861,7 +1861,7 @@
sext.w\t%0,%1
lw\t%0,%1"
[(set_attr "move_type" "move,load")
- (set_attr "type" "multi")
+ (set_attr "type" "move,load")
(set_attr "mode" "DI")])
(define_expand "extend<SHORT:mode><SUPERQI:mode>2"
@@ -1938,7 +1938,7 @@
|| reg_or_0_operand (operands[1], HFmode))"
{ return riscv_output_move (operands[0], operands[1]); }
[(set_attr "move_type" "fmove,fmove,mtc,fpload,fpstore,store,mtc,mfc,move,load,store")
- (set_attr "type" "fmove")
+ (set_attr "type" "fmove,fmove,mtc,fpload,fpstore,store,mtc,mfc,move,load,store")
(set_attr "mode" "HF")])
(define_insn "*movhf_softfloat"
@@ -1949,7 +1949,7 @@
|| reg_or_0_operand (operands[1], HFmode))"
{ return riscv_output_move (operands[0], operands[1]); }
[(set_attr "move_type" "fmove,move,load,store,mtc,mfc")
- (set_attr "type" "fmove")
+ (set_attr "type" "fmove,move,load,store,mtc,mfc")
(set_attr "mode" "HF")])
(define_insn "*movhf_softfloat_boxing"
@@ -2182,7 +2182,7 @@
{ return riscv_output_move (operands[0], operands[1]); }
[(set_attr "move_type" "move,const,load,store,mtc,fpload,mfc,fmove,fpstore,rdvlenb")
(set_attr "mode" "DI")
- (set_attr "type" "move")
+ (set_attr "type" "move,move,load,store,move,fpload,move,fmove,fpstore,move")
(set_attr "ext" "base,base,base,base,d,d,d,d,d,vector")])
(define_insn "*movdi_64bit"
@@ -2194,7 +2194,7 @@
{ return riscv_output_move (operands[0], operands[1]); }
[(set_attr "move_type" "move,const,load,store,mtc,fpload,mfc,fmove,fpstore,rdvlenb")
(set_attr "mode" "DI")
- (set_attr "type" "move")
+ (set_attr "type" "move,move,load,store,mtc,fpload,mfc,fmove,fpstore,move")
(set_attr "ext" "base,base,base,base,d,d,d,d,d,vector")])
;; 32-bit Integer moves
@@ -2217,7 +2217,7 @@
{ return riscv_output_move (operands[0], operands[1]); }
[(set_attr "move_type" "move,const,load,store,mtc,fpload,mfc,fpstore,rdvlenb")
(set_attr "mode" "SI")
- (set_attr "type" "move")
+ (set_attr "type" "move,move,load,store,mtc,fpload,mfc,fpstore,move")
(set_attr "ext" "base,base,base,base,f,f,f,f,vector")])
;; 16-bit Integer moves
@@ -2244,7 +2244,7 @@
{ return riscv_output_move (operands[0], operands[1]); }
[(set_attr "move_type" "move,const,load,store,mtc,mfc,rdvlenb")
(set_attr "mode" "HI")
- (set_attr "type" "move")
+ (set_attr "type" "move,move,load,store,mtc,mfc,move")
(set_attr "ext" "base,base,base,base,f,f,vector")])
;; HImode constant generation; see riscv_move_integer for details.
@@ -2288,7 +2288,7 @@
{ return riscv_output_move (operands[0], operands[1]); }
[(set_attr "move_type" "move,const,load,store,mtc,mfc,rdvlenb")
(set_attr "mode" "QI")
- (set_attr "type" "move")
+ (set_attr "type" "move,move,load,store,mtc,mfc,move")
(set_attr "ext" "base,base,base,base,f,f,vector")])
;; 32-bit floating point moves
@@ -2310,7 +2310,7 @@
|| reg_or_0_operand (operands[1], SFmode))"
{ return riscv_output_move (operands[0], operands[1]); }
[(set_attr "move_type" "fmove,fmove,mtc,fpload,fpstore,store,mtc,mfc,move,load,store")
- (set_attr "type" "fmove")
+ (set_attr "type" "fmove,fmove,mtc,fpload,fpstore,store,mtc,mfc,move,load,store")
(set_attr "mode" "SF")])
(define_insn "*movsf_softfloat"
@@ -2321,7 +2321,7 @@
|| reg_or_0_operand (operands[1], SFmode))"
{ return riscv_output_move (operands[0], operands[1]); }
[(set_attr "move_type" "move,load,store")
- (set_attr "type" "fmove")
+ (set_attr "type" "move,load,store")
(set_attr "mode" "SF")])
;; 64-bit floating point moves
@@ -2346,7 +2346,7 @@
|| reg_or_0_operand (operands[1], DFmode))"
{ return riscv_output_move (operands[0], operands[1]); }
[(set_attr "move_type" "fmove,fmove,mtc,fpload,fpstore,store,mtc,mfc,move,load,store")
- (set_attr "type" "fmove")
+ (set_attr "type" "fmove,fmove,mtc,fpload,fpstore,store,mtc,mfc,move,load,store")
(set_attr "mode" "DF")])
(define_insn "*movdf_hardfloat_rv64"
@@ -2357,7 +2357,7 @@
|| reg_or_0_operand (operands[1], DFmode))"
{ return riscv_output_move (operands[0], operands[1]); }
[(set_attr "move_type" "fmove,fmove,mtc,fpload,fpstore,store,mtc,mfc,move,load,store")
- (set_attr "type" "fmove")
+ (set_attr "type" "fmove,fmove,mtc,fpload,fpstore,store,mtc,mfc,move,load,store")
(set_attr "mode" "DF")])
(define_insn "*movdf_softfloat"
@@ -2368,7 +2368,7 @@
|| reg_or_0_operand (operands[1], DFmode))"
{ return riscv_output_move (operands[0], operands[1]); }
[(set_attr "move_type" "move,load,store")
- (set_attr "type" "fmove")
+ (set_attr "type" "fmove,fpload,fpstore")
(set_attr "mode" "DF")])
(define_insn "movsidf2_low_rv32"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-1.c
index 28b8a82096a..60c838eb21d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-1.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvl4096b -mrvv-vector-bits=scalable -mabi=lp64d -O3" } */
+/* { dg-options "-march=rv64gcv_zvl4096b -mrvv-vector-bits=scalable -mabi=lp64d -O3 -fno-schedule-insns2" } */
#include "def.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-2.c
index d45fb4c1f2f..b9922a64332 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-2.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvl4096b -mrvv-vector-bits=scalable -mabi=lp64d -O3" } */
+/* { dg-options "-march=rv64gcv_zvl4096b -mrvv-vector-bits=scalable -mabi=lp64d -O3 -fno-schedule-insns2" } */
#include "def.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-3.c
index 1885004fda4..989d45de254 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-3.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvl4096b -mrvv-vector-bits=scalable -mabi=lp64d -O3" } */
+/* { dg-options "-march=rv64gcv_zvl4096b -mrvv-vector-bits=scalable -mabi=lp64d -O3 -fno-schedule-insns2" } */
#include "def.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-4.c
index 3a4ed22614c..b8bb2932de8 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-4.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvl4096b -mrvv-vector-bits=scalable -mabi=lp64d -O3" } */
+/* { dg-options "-march=rv64gcv_zvl4096b -mrvv-vector-bits=scalable -mabi=lp64d -O3 -fno-schedule-insns2" } */
#include "def.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-5.c
index e3f3b397f3f..f0357d30aec 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-5.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mrvv-vector-bits=scalable -mabi=lp64d -O3" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mrvv-vector-bits=scalable -mabi=lp64d -O3 -fno-schedule-insns2" } */
#include "def.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-6.c
index 4c876ac3b86..edf6539b0f2 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-6.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvl4096b -mrvv-vector-bits=scalable -mabi=lp64d -O3" } */
+/* { dg-options "-march=rv64gcv_zvl4096b -mrvv-vector-bits=scalable -mabi=lp64d -O3 -fno-schedule-insns2" } */
#include "def.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-7.c
index 5542d4878ff..e001a73de52 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-7.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvl4096b -mrvv-vector-bits=scalable -mabi=lp64d -O3" } */
+/* { dg-options "-march=rv64gcv_zvl4096b -mrvv-vector-bits=scalable -mabi=lp64d -O3 -fno-schedule-insns2" } */
#include "def.h"
More information about the Gcc-cvs
mailing list