[gcc r14-9250] RISC-V: Introduce gcc option mrvv-vector-bits for RVV
Pan Li
panli@gcc.gnu.org
Fri Mar 1 10:32:52 GMT 2024
https://gcc.gnu.org/g:0a01d1232ff0a8b094270fbf45c9fd0ea46df19f
commit r14-9250-g0a01d1232ff0a8b094270fbf45c9fd0ea46df19f
Author: Pan Li <pan2.li@intel.com>
Date: Fri Feb 23 15:37:28 2024 +0800
RISC-V: Introduce gcc option mrvv-vector-bits for RVV
This patch would like to introduce one new gcc option for RVV. To
appoint the bits size of one RVV vector register. Valid arguments to
'-mrvv-vector-bits=' are:
* scalable
* zvl
The scalable will pick up the zvl*b in the march as the minimal vlen.
For example, the minimal vlen will be 512 when march=rv64gcv_zvl512b
and mrvv-vector-bits=scalable.
The zvl will pick up the zvl*b in the march as exactly vlen.
For example, the vlen will be 1024 exactly when march=rv64gcv_zvl1024b
and mrvv-vector-bits=zvl.
The internal option --param=riscv-autovec-preference will be replaced
by option -mrvv-vector-bits. Aka:
* -mrvv-vector-bits=scalable indicates --param=riscv-autovec-preference=scalable
* -mrvv-vector-bits=zvl indicates --param=riscv-autovec-preference=fixed-vlmax
You can also take -fno-tree-vectorize for --param=riscv-autovec-preference=none.
The internal option --param=riscv-autovec-preference is unavailable after this
patch.
Given below sample for more details:
void test_rvv_vector_bits ()
{
vint32m1_t x;
asm volatile ("def %0": "=vr"(x));
asm volatile (""::: "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7",
"v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15",
"v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23",
"v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31");
asm volatile ("use %0": : "vr"(x));
}
With -march=rv64gcv_zvl128b -mrvv-vector-bits=scalable we have (for min_vlen >= 128)
csrr t0,vlenb
sub sp,sp,t0
def v1
vs1r.v v1,0(sp)
vl1re32.v v1,0(sp)
use v1
csrr t0,vlenb
add sp,sp,t0
jr ra
With -march=rv64gcv_zvl128b -mrvv-vector-bits=zvl we have (for vlen = 128)
addi sp,sp,-16
def v1
vs1r.v v1,0(sp)
vl1re32.v v1,0(sp)
use v1
addi sp,sp,16
jr ra
The below test are passed for this patch.
* The riscv fully regression test.
PR target/112817
gcc/ChangeLog:
* config/riscv/riscv-avlprop.cc (pass_avlprop::execute): Replace
RVV_FIXED_VLMAX to RVV_VECTOR_BITS_ZVL.
* config/riscv/riscv-opts.h (enum riscv_autovec_preference_enum): Remove.
(enum rvv_vector_bits_enum): New enum for different RVV vector bits.
* config/riscv/riscv-selftests.cc (riscv_run_selftests): Update
comments for option replacement.
* config/riscv/riscv-v.cc (autovec_use_vlmax_p): Replace enum of
riscv_autovec_preference to rvv_vector_bits.
(vls_mode_valid_p): Ditto.
(estimated_poly_value): Ditto.
* config/riscv/riscv.cc (riscv_convert_vector_chunks): Rename to
vector chunks and honor new option mrvv-vector-bits.
(riscv_override_options_internal): Update comments and rename the
vector chunks.
* config/riscv/riscv.opt: Add option mrvv-vector-bits and remove
internal option param=riscv-autovec-preference.
gcc/testsuite/ChangeLog:
* g++.target/riscv/rvv/base/pr111296.C: Replace
param=riscv-autovec-preference to mrvv-vector-bits.
* gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-6.c: Ditto.
* gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-8.c: Ditto.
* gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul8-12.c: Ditto.
* gcc.dg/vect/costmodel/riscv/rvv/pr113112-1.c: Ditto.
* gcc.dg/vect/costmodel/riscv/rvv/pr113112-2.c: Ditto.
* gcc.dg/vect/costmodel/riscv/rvv/pr113112-3.c: Ditto.
* gcc.dg/vect/costmodel/riscv/rvv/pr113112-4.c: Ditto.
* gcc.dg/vect/costmodel/riscv/rvv/pr113112-5.c: Ditto.
* gcc.dg/vect/costmodel/riscv/rvv/pr113247-2.c: Ditto.
* gcc.dg/vect/costmodel/riscv/rvv/pr113247-4.c: Ditto.
* gcc.dg/vect/costmodel/riscv/rvv/pr113281-2.c: Ditto.
* gcc.dg/vect/costmodel/riscv/rvv/pr113281-4.c: Ditto.
* gcc.target/riscv/rvv/autovec/align-1.c: Ditto.
* gcc.target/riscv/rvv/autovec/align-2.c: Ditto.
* gcc.target/riscv/rvv/autovec/binop/copysign-run.c: Ditto.
* gcc.target/riscv/rvv/autovec/binop/copysign-rv32gcv.c: Ditto.
* gcc.target/riscv/rvv/autovec/binop/copysign-rv64gcv.c: Ditto.
* gcc.target/riscv/rvv/autovec/binop/copysign-zvfh-run.c: Ditto.
* gcc.target/riscv/rvv/autovec/binop/fmax-1.c: Ditto.
* gcc.target/riscv/rvv/autovec/binop/fmax_run-1.c: Ditto.
* gcc.target/riscv/rvv/autovec/binop/fmax_zvfh-1.c: Ditto.
* gcc.target/riscv/rvv/autovec/binop/fmax_zvfh_run-1.c: Ditto.
* gcc.target/riscv/rvv/autovec/binop/fmin-1.c: Ditto.
* gcc.target/riscv/rvv/autovec/binop/fmin_run-1.c: Ditto.
* gcc.target/riscv/rvv/autovec/binop/fmin_zvfh-1.c: Ditto.
* gcc.target/riscv/rvv/autovec/binop/fmin_zvfh_run-1.c: Ditto.
* gcc.target/riscv/rvv/autovec/binop/mulh-1.c: Ditto.
* gcc.target/riscv/rvv/autovec/binop/mulh-2.c: Ditto.
* gcc.target/riscv/rvv/autovec/binop/mulh_run-1.c: Ditto.
* gcc.target/riscv/rvv/autovec/binop/mulh_run-2.c: Ditto.
* gcc.target/riscv/rvv/autovec/binop/narrow-1.c: Ditto.
* gcc.target/riscv/rvv/autovec/binop/narrow-2.c: Ditto.
* gcc.target/riscv/rvv/autovec/binop/narrow-3.c: Ditto.
* gcc.target/riscv/rvv/autovec/binop/narrow_run-1.c: Ditto.
* gcc.target/riscv/rvv/autovec/binop/narrow_run-2.c: Ditto.
* gcc.target/riscv/rvv/autovec/binop/narrow_run-3.c: Ditto.
* gcc.target/riscv/rvv/autovec/binop/shift-immediate.c: Ditto.
* gcc.target/riscv/rvv/autovec/binop/shift-run.c: Ditto.
* gcc.target/riscv/rvv/autovec/binop/shift-rv32gcv.c: Ditto.
* gcc.target/riscv/rvv/autovec/binop/shift-rv64gcv.c: Ditto.
* gcc.target/riscv/rvv/autovec/binop/shift-scalar-run.c: Ditto.
* gcc.target/riscv/rvv/autovec/binop/shift-scalar-rv32gcv.c: Ditto.
* gcc.target/riscv/rvv/autovec/binop/shift-scalar-rv64gcv.c: Ditto.
* gcc.target/riscv/rvv/autovec/binop/shift-scalar-template.h: Ditto.
* gcc.target/riscv/rvv/autovec/binop/vadd-run-nofm.c: Ditto.
* gcc.target/riscv/rvv/autovec/binop/vadd-run.c: Ditto.
* gcc.target/riscv/rvv/autovec/binop/vadd-rv32gcv-nofm.c: Ditto.
* gcc.target/riscv/rvv/autovec/binop/vadd-rv32gcv.c: Ditto.
* gcc.target/riscv/rvv/autovec/binop/vadd-rv64gcv-nofm.c: Ditto.
* gcc.target/riscv/rvv/autovec/binop/vadd-rv64gcv.c: Ditto.
* gcc.target/riscv/rvv/autovec/binop/vadd-zvfh-run.c: Ditto.
* gcc.target/riscv/rvv/autovec/binop/vand-run.c: Ditto.
* gcc.target/riscv/rvv/autovec/binop/vand-rv32gcv.c: Ditto.
* gcc.target/riscv/rvv/autovec/binop/vand-rv64gcv.c: Ditto.
* gcc.target/riscv/rvv/autovec/binop/vcompress-avlprop-1.c: Ditto.
* gcc.target/riscv/rvv/autovec/binop/vdiv-run-nofm.c: Ditto.
* gcc.target/riscv/rvv/autovec/binop/vdiv-run.c: Ditto.
* gcc.target/riscv/rvv/autovec/binop/vdiv-rv32gcv-nofm.c: Ditto.
* gcc.target/riscv/rvv/autovec/binop/vdiv-rv32gcv.c: Ditto.
* gcc.target/riscv/rvv/autovec/binop/vdiv-rv64gcv-nofm.c: Ditto.
* gcc.target/riscv/rvv/autovec/binop/vdiv-rv64gcv.c: Ditto.
* gcc.target/riscv/rvv/autovec/binop/vdiv-zvfh-run.c: Ditto.
* gcc.target/riscv/rvv/autovec/binop/vmax-run.c: Ditto.
* gcc.target/riscv/rvv/autovec/binop/vmax-rv32gcv.c: Ditto.
* gcc.target/riscv/rvv/autovec/binop/vmax-rv64gcv.c: Ditto.
* gcc.target/riscv/rvv/autovec/binop/vmax-zvfh-run.c: Ditto.
* gcc.target/riscv/rvv/autovec/binop/vmin-run.c: Ditto.
* gcc.target/riscv/rvv/autovec/binop/vmin-rv32gcv.c: Ditto.
* gcc.target/riscv/rvv/autovec/binop/vmin-rv64gcv.c: Ditto.
* gcc.target/riscv/rvv/autovec/binop/vmin-zvfh-run.c: Ditto.
* gcc.target/riscv/rvv/autovec/binop/vmul-run-nofm.c: Ditto.
* gcc.target/riscv/rvv/autovec/binop/vmul-run.c: Ditto.
* gcc.target/riscv/rvv/autovec/binop/vmul-rv32gcv-nofm.c: Ditto.
* gcc.target/riscv/rvv/autovec/binop/vmul-rv32gcv.c: Ditto.
* gcc.target/riscv/rvv/autovec/binop/vmul-rv64gcv-nofm.c: Ditto.
* gcc.target/riscv/rvv/autovec/binop/vmul-rv64gcv.c: Ditto.
* gcc.target/riscv/rvv/autovec/binop/vmul-zvfh-run.c: Ditto.
* gcc.target/riscv/rvv/autovec/binop/vor-run.c: Ditto.
* gcc.target/riscv/rvv/autovec/binop/vor-rv32gcv.c: Ditto.
* gcc.target/riscv/rvv/autovec/binop/vor-rv64gcv.c: Ditto.
* gcc.target/riscv/rvv/autovec/binop/vrem-run.c: Ditto.
* gcc.target/riscv/rvv/autovec/binop/vrem-rv32gcv.c: Ditto.
* gcc.target/riscv/rvv/autovec/binop/vrem-rv64gcv.c: Ditto.
* gcc.target/riscv/rvv/autovec/binop/vsub-run-nofm.c: Ditto.
* gcc.target/riscv/rvv/autovec/binop/vsub-run.c: Ditto.
* gcc.target/riscv/rvv/autovec/binop/vsub-rv32gcv-nofm.c: Ditto.
* gcc.target/riscv/rvv/autovec/binop/vsub-rv32gcv.c: Ditto.
* gcc.target/riscv/rvv/autovec/binop/vsub-rv64gcv-nofm.c: Ditto.
* gcc.target/riscv/rvv/autovec/binop/vsub-rv64gcv.c: Ditto.
* gcc.target/riscv/rvv/autovec/binop/vsub-zvfh-run.c: Ditto.
* gcc.target/riscv/rvv/autovec/binop/vxor-run.c: Ditto.
* gcc.target/riscv/rvv/autovec/binop/vxor-rv32gcv.c: Ditto.
* gcc.target/riscv/rvv/autovec/binop/vxor-rv64gcv.c: Ditto.
* gcc.target/riscv/rvv/autovec/bug-1.c: Ditto.
* gcc.target/riscv/rvv/autovec/bug-2.c: Ditto.
* gcc.target/riscv/rvv/autovec/bug-3.c: Ditto.
* gcc.target/riscv/rvv/autovec/bug-4.c: Ditto.
* gcc.target/riscv/rvv/autovec/bug-5.c: Ditto.
* gcc.target/riscv/rvv/autovec/bug-6.c: Ditto.
* gcc.target/riscv/rvv/autovec/bug-8.c: Ditto.
* gcc.target/riscv/rvv/autovec/cmp/vcond-1.c: Ditto.
* gcc.target/riscv/rvv/autovec/cmp/vcond-2.c: Ditto.
* gcc.target/riscv/rvv/autovec/cmp/vcond-3.c: Ditto.
* gcc.target/riscv/rvv/autovec/cmp/vcond-4.c: Ditto.
* gcc.target/riscv/rvv/autovec/cmp/vcond_run-1.c: Ditto.
* gcc.target/riscv/rvv/autovec/cmp/vcond_run-2.c: Ditto.
* gcc.target/riscv/rvv/autovec/cmp/vcond_run-3.c: Ditto.
* gcc.target/riscv/rvv/autovec/cmp/vcond_run-4.c: Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_arith-1.c: Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_arith-10.c: Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_arith-11.c: Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_arith-2.c: Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_arith-3.c: Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_arith-4.c: Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_arith-5.c: Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_arith-6.c: Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_arith-7.c: Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_arith-8.c: Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_arith-9.c: Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_arith_run-1.c: Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_arith_run-10.c: Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_arith_run-11.c: Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_arith_run-2.c: Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_arith_run-3.c: Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_arith_run-4.c: Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_arith_run-5.c: Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_arith_run-6.c: Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_arith_run-7.c: Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_arith_run-8.c: Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_arith_run-9.c: Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv32-1.c: Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv32-2.c: Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv64-1.c: Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv64-2.c: Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float_run-1.c: Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float_run-2.c: Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv32-1.c: Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv32-2.c: Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv64-1.c: Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv64-2.c: Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_run-1.c: Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_run-2.c: Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh-rv32-1.c: Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh-rv32-2.c: Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh-rv64-1.c: Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh-rv64-2.c: Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh_run-1.c: Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh_run-2.c: Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv32-1.c: Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv32-2.c: Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv64-1.c: Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv64-2.c: Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float_run-1.c: Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float_run-2.c: Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv32-1.c: Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv32-2.c: Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv64-1.c: Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv64-2.c: Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int_run-1.c: Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int_run-2.c: Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_copysign-run.c: Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_copysign-rv32gcv.c: Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_copysign-rv64gcv.c: Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_copysign-zvfh-run.c: Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_fadd-1.c: Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_fadd-2.c: Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_fadd-3.c: Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_fadd-4.c: Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_fadd_run-1.c: Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_fadd_run-2.c: Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_fadd_run-3.c: Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_fadd_run-4.c: Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-1.c: Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-2.c: Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-3.c: Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-4.c: Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-5.c: Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-6.c: Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-7.c: Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-8.c:
* gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-1.c: Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-2.c: Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-3.c: Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-4.c: Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-5.c: Diito.
* gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-6.c: Diito.
* gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-7.c: Diito.
* gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-8.c: Diito.
* gcc.target/riscv/rvv/autovec/cond/cond_fmax-1.c: Diito.
* gcc.target/riscv/rvv/autovec/cond/cond_fmax-2.c: Diito.
* gcc.target/riscv/rvv/autovec/cond/cond_fmax-3.c: Diito.
* gcc.target/riscv/rvv/autovec/cond/cond_fmax-4.c: Diito.
* gcc.target/riscv/rvv/autovec/cond/cond_fmax_run-1.c: Diito.
* gcc.target/riscv/rvv/autovec/cond/cond_fmax_run-2.c: Diito.
* gcc.target/riscv/rvv/autovec/cond/cond_fmax_run-3.c: Diito.
* gcc.target/riscv/rvv/autovec/cond/cond_fmax_run-4.c: Diito.
* gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh-1.c: Diito.
* gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh-2.c: Diito.
* gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh-3.c: Diito.
* gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh-4.c: Diito.
* gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh_run-1.c: Diito.
* gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh_run-2.c: Diito.
* gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh_run-3.c: Diito.
* gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh_run-4.c: Diito.
* gcc.target/riscv/rvv/autovec/cond/cond_fmin-1.c: Diito.
* gcc.target/riscv/rvv/autovec/cond/cond_fmin-2.c: Diito.
* gcc.target/riscv/rvv/autovec/cond/cond_fmin-3.c: Diito.
* gcc.target/riscv/rvv/autovec/cond/cond_fmin-4.c: Diito.
* gcc.target/riscv/rvv/autovec/cond/cond_fmin_run-1.c: Diito.
* gcc.target/riscv/rvv/autovec/cond/cond_fmin_run-2.c: Diito.
* gcc.target/riscv/rvv/autovec/cond/cond_fmin_run-3.c: Diito.
* gcc.target/riscv/rvv/autovec/cond/cond_fmin_run-4.c: Diito.
* gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh-1.c: Diito.
* gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh-2.c: Diito.
* gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh-3.c: Diito.
* gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh-4.c: Diito.
* gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh_run-1.c: Diito.
* gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh_run-2.c: Diito.
* gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh_run-3.c: Diito.
* gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh_run-4.c: Diito.
* gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-1.c: Diito.
* gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-2.c: Diito.
* gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-3.c: Diito.
* gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-4.c: Diito.
* gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-5.c: Diito.
* gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-6.c: Diito.
* gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms_run-1.c: Diito.
* gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms_run-2.c: Diito.
* gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms_run-3.c: Diito.
* gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms_run-4.c: Diito.
* gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms_run-5.c: Diito.
* gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms_run-6.c: Diito.
* gcc.target/riscv/rvv/autovec/cond/cond_fmul-1.c: Diito.
* gcc.target/riscv/rvv/autovec/cond/cond_fmul-2.c: Diito.
* gcc.target/riscv/rvv/autovec/cond/cond_fmul-3.c: Diito.
* gcc.target/riscv/rvv/autovec/cond/cond_fmul-4.c: Diito.
* gcc.target/riscv/rvv/autovec/cond/cond_fmul-5.c: Diito.
* gcc.target/riscv/rvv/autovec/cond/cond_fmul_run-1.c: Diito.
* gcc.target/riscv/rvv/autovec/cond/cond_fmul_run-2.c: Diito.
* gcc.target/riscv/rvv/autovec/cond/cond_fmul_run-3.c: Diito.
* gcc.target/riscv/rvv/autovec/cond/cond_fmul_run-4.c: Diito.
* gcc.target/riscv/rvv/autovec/cond/cond_fmul_run-5.c: Diito.
* gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max-1.c: Diito.
* gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max-2.c: Diito.
* gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max-3.c: Diito.
* gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max-4.c: Diito.
* gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max-5.c: Diito.
* gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max_run-1.c: Diito.
* gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max_run-2.c: Diito.
* gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max_run-3.c: Diito.
* gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max_run-4.c: Diito.
* gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max_run-5.c: Diito.
* gcc.target/riscv/rvv/autovec/cond/cond_mulh-1.c: Diito.
* gcc.target/riscv/rvv/autovec/cond/cond_mulh-2.c: Diito.
* gcc.target/riscv/rvv/autovec/cond/cond_mulh_run-1.c: Diito.
* gcc.target/riscv/rvv/autovec/cond/cond_mulh_run-2.c: Diito.
* gcc.target/riscv/rvv/autovec/cond/cond_narrow_shift-1.c: Diito.
* gcc.target/riscv/rvv/autovec/cond/cond_narrow_shift-2.c: Diito.
* gcc.target/riscv/rvv/autovec/cond/cond_narrow_shift-3.c: Diito.
* gcc.target/riscv/rvv/autovec/cond/cond_narrow_shift_run-1.c: Diito.
* gcc.target/riscv/rvv/autovec/cond/cond_narrow_shift_run-2.c: Diito.
* gcc.target/riscv/rvv/autovec/cond/cond_narrow_shift_run-3.c: Diito.
* gcc.target/riscv/rvv/autovec/cond/cond_shift-1.c: Diito.
* gcc.target/riscv/rvv/autovec/cond/cond_shift-2.c: Diito.
* gcc.target/riscv/rvv/autovec/cond/cond_shift-3.c: Diito.
* gcc.target/riscv/rvv/autovec/cond/cond_shift-4.c: Diito.
* gcc.target/riscv/rvv/autovec/cond/cond_shift-5.c: Diito.
* gcc.target/riscv/rvv/autovec/cond/cond_shift-6.c: Diito.
* gcc.target/riscv/rvv/autovec/cond/cond_shift-7.c: Diito.
* gcc.target/riscv/rvv/autovec/cond/cond_shift-8.c: Diito.
* gcc.target/riscv/rvv/autovec/cond/cond_shift-9.c: Diito.
* gcc.target/riscv/rvv/autovec/cond/cond_shift_run-1.c: Diito.
* gcc.target/riscv/rvv/autovec/cond/cond_shift_run-2.c: Diito.
* gcc.target/riscv/rvv/autovec/cond/cond_shift_run-3.c: Diito.
* gcc.target/riscv/rvv/autovec/cond/cond_shift_run-4.c: Diito.
* gcc.target/riscv/rvv/autovec/cond/cond_shift_run-5.c: Diito.
* gcc.target/riscv/rvv/autovec/cond/cond_shift_run-6.c: Diito.
* gcc.target/riscv/rvv/autovec/cond/cond_shift_run-7.c: Diito.
* gcc.target/riscv/rvv/autovec/cond/cond_shift_run-8.c: Diito.
* gcc.target/riscv/rvv/autovec/cond/cond_shift_run-9.c: Diito.
* gcc.target/riscv/rvv/autovec/cond/cond_sqrt-1.c: Diito.
* gcc.target/riscv/rvv/autovec/cond/cond_sqrt-2.c: Diito.
* gcc.target/riscv/rvv/autovec/cond/cond_sqrt-zvfh-1.c: Diito.
* gcc.target/riscv/rvv/autovec/cond/cond_sqrt-zvfh-2.c: Diito.
* gcc.target/riscv/rvv/autovec/cond/cond_sqrt_run-1.c: Diito.
* gcc.target/riscv/rvv/autovec/cond/cond_sqrt_run-2.c: Diito.
* gcc.target/riscv/rvv/autovec/cond/cond_sqrt_run-zvfh-1.c: Diito.
* gcc.target/riscv/rvv/autovec/cond/cond_sqrt_run-zvfh-2.c: Diito.
* gcc.target/riscv/rvv/autovec/cond/cond_unary-1.c: Diito.
* gcc.target/riscv/rvv/autovec/cond/cond_unary-2.c: Diito.
* gcc.target/riscv/rvv/autovec/cond/cond_unary-3.c: Diito.
* gcc.target/riscv/rvv/autovec/cond/cond_unary-4.c: Diito.
* gcc.target/riscv/rvv/autovec/cond/cond_unary-5.c: Diito.
* gcc.target/riscv/rvv/autovec/cond/cond_unary-6.c: Diito.
* gcc.target/riscv/rvv/autovec/cond/cond_unary-7.c: Diito.
* gcc.target/riscv/rvv/autovec/cond/cond_unary-8.c: Diito.
* gcc.target/riscv/rvv/autovec/cond/cond_unary_run-1.c: Diito.
* gcc.target/riscv/rvv/autovec/cond/cond_unary_run-2.c: Diito.
* gcc.target/riscv/rvv/autovec/cond/cond_unary_run-3.c: Diito.
* gcc.target/riscv/rvv/autovec/cond/cond_unary_run-4.c: Diito.
* gcc.target/riscv/rvv/autovec/cond/cond_unary_run-5.c: Diito.
* gcc.target/riscv/rvv/autovec/cond/cond_unary_run-6.c: Diito.
* gcc.target/riscv/rvv/autovec/cond/cond_unary_run-7.c: Diito.
* gcc.target/riscv/rvv/autovec/cond/cond_unary_run-8.c: Diito.
* gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-1.c: Diito.
* gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-2.c: Diito.
* gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-3.c: Diito.
* gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-4.c: Diito.
* gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-5.c: Diito.
* gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-6.c: Diito.
* gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-7.c: Diito.
* gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-8.c: Diito.
* gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-9.c: Diito.
* gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc-1.c: Diito.
* gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc-2.c: Diito.
* gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc_run-1.c: Diito.
* gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc_run-2.c: Diito.
* gcc.target/riscv/rvv/autovec/cond/pr111401.c: Diito.
* gcc.target/riscv/rvv/autovec/conversions/vec-narrow-int64-float16.c: Diito.
* gcc.target/riscv/rvv/autovec/conversions/vec-widen-float16-int64.c: Diito.
* gcc.target/riscv/rvv/autovec/conversions/vfcvt-itof-run.c: Diito.
* gcc.target/riscv/rvv/autovec/conversions/vfcvt-itof-rv32gcv.c: Diito.
* gcc.target/riscv/rvv/autovec/conversions/vfcvt-itof-rv64gcv.c: Diito.
* gcc.target/riscv/rvv/autovec/conversions/vfcvt-itof-zvfh-run.c: Diito.
* gcc.target/riscv/rvv/autovec/conversions/vfcvt_rtz-run.c: Diito.
* gcc.target/riscv/rvv/autovec/conversions/vfcvt_rtz-rv32gcv.c: Diito.
* gcc.target/riscv/rvv/autovec/conversions/vfcvt_rtz-rv64gcv.c: Diito.
* gcc.target/riscv/rvv/autovec/conversions/vfcvt_rtz-zvfh-run.c: Diito.
* gcc.target/riscv/rvv/autovec/conversions/vfncvt-ftoi-run.c: Diito.
* gcc.target/riscv/rvv/autovec/conversions/vfncvt-ftoi-rv32gcv.c: Diito.
* gcc.target/riscv/rvv/autovec/conversions/vfncvt-ftoi-rv64gcv.c: Diito.
* gcc.target/riscv/rvv/autovec/conversions/vfncvt-ftoi-zvfh-run.c: Diito.
* gcc.target/riscv/rvv/autovec/conversions/vfncvt-itof-run.c: Diito.
* gcc.target/riscv/rvv/autovec/conversions/vfncvt-itof-rv32gcv.c: Diito.
* gcc.target/riscv/rvv/autovec/conversions/vfncvt-itof-rv64gcv.c: Diito.
* gcc.target/riscv/rvv/autovec/conversions/vfncvt-itof-zvfh-run.c: Diito.
* gcc.target/riscv/rvv/autovec/conversions/vfncvt-run.c: Diito.
* gcc.target/riscv/rvv/autovec/conversions/vfncvt-rv32gcv.c: Diito.
* gcc.target/riscv/rvv/autovec/conversions/vfncvt-rv64gcv.c: Diito.
* gcc.target/riscv/rvv/autovec/conversions/vfncvt-zvfh-run.c: Diito.
* gcc.target/riscv/rvv/autovec/conversions/vfwcvt-ftoi-run.c: Diito.
* gcc.target/riscv/rvv/autovec/conversions/vfwcvt-ftoi-rv32gcv.c: Diito.
* gcc.target/riscv/rvv/autovec/conversions/vfwcvt-ftoi-rv64gcv.c: Diito.
* gcc.target/riscv/rvv/autovec/conversions/vfwcvt-ftoi-zvfh-run.c: Diito.
* gcc.target/riscv/rvv/autovec/conversions/vfwcvt-itof-run.c: Diito.
* gcc.target/riscv/rvv/autovec/conversions/vfwcvt-itof-rv32gcv.c: Diito.
* gcc.target/riscv/rvv/autovec/conversions/vfwcvt-itof-rv64gcv.c: Diito.
* gcc.target/riscv/rvv/autovec/conversions/vfwcvt-itof-zvfh-run.c: Diito.
* gcc.target/riscv/rvv/autovec/conversions/vfwcvt-run.c: Diito.
* gcc.target/riscv/rvv/autovec/conversions/vfwcvt-rv32gcv.c: Diito.
* gcc.target/riscv/rvv/autovec/conversions/vfwcvt-rv64gcv.c: Diito.
* gcc.target/riscv/rvv/autovec/conversions/vfwcvt-zvfh-run.c: Diito.
* gcc.target/riscv/rvv/autovec/conversions/vncvt-run.c: Diito.
* gcc.target/riscv/rvv/autovec/conversions/vncvt-rv32gcv.c: Diito.
* gcc.target/riscv/rvv/autovec/conversions/vncvt-rv64gcv.c: Diito.
* gcc.target/riscv/rvv/autovec/conversions/vsext-run.c: Diito.
* gcc.target/riscv/rvv/autovec/conversions/vsext-rv32gcv.c: Diito.
* gcc.target/riscv/rvv/autovec/conversions/vsext-rv64gcv.c: Diito.
* gcc.target/riscv/rvv/autovec/conversions/vzext-run.c: Diito.
* gcc.target/riscv/rvv/autovec/conversions/vzext-rv32gcv.c: Diito.
* gcc.target/riscv/rvv/autovec/conversions/vzext-rv64gcv.c: Diito.
* gcc.target/riscv/rvv/autovec/fixed-vlmax-1.c: Diito.
* gcc.target/riscv/rvv/autovec/fold-min-poly.c: Diito.
* gcc.target/riscv/rvv/autovec/gather-scatter/strided_load-1.c: Diito.
* gcc.target/riscv/rvv/autovec/gather-scatter/strided_load-2.c: Diito.
* gcc.target/riscv/rvv/autovec/gather-scatter/strided_store-1.c: Diito.
* gcc.target/riscv/rvv/autovec/gather-scatter/strided_store-2.c: Diito.
* gcc.target/riscv/rvv/autovec/madd-split2-1.c: Diito.
* gcc.target/riscv/rvv/autovec/partial/gimple_fold-1.c: Diito.
* gcc.target/riscv/rvv/autovec/partial/live-1.c: Diito.
* gcc.target/riscv/rvv/autovec/partial/live-2.c: Diito.
* gcc.target/riscv/rvv/autovec/partial/live_run-1.c: Diito.
* gcc.target/riscv/rvv/autovec/partial/live_run-2.c: Diito.
* gcc.target/riscv/rvv/autovec/partial/multiple_rgroup-1.c: Diito.
* gcc.target/riscv/rvv/autovec/partial/multiple_rgroup-2.c: Diito.
* gcc.target/riscv/rvv/autovec/partial/multiple_rgroup-3.c: Diito.
* gcc.target/riscv/rvv/autovec/partial/multiple_rgroup-4.c: Diito.
* gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-1.c: Diito.
* gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-2.c: Diito.
* gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-3.c: Diito.
* gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-4.c: Diito.
* gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_zbb.c: Diito.
* gcc.target/riscv/rvv/autovec/partial/select_vl-1.c: Diito.
* gcc.target/riscv/rvv/autovec/partial/select_vl-2.c: Diito.
* gcc.target/riscv/rvv/autovec/partial/single_rgroup-1.c: Diito.
* gcc.target/riscv/rvv/autovec/partial/single_rgroup-2.c: Diito.
* gcc.target/riscv/rvv/autovec/partial/single_rgroup-3.c: Diito.
* gcc.target/riscv/rvv/autovec/partial/single_rgroup_run-1.c: Diito.
* gcc.target/riscv/rvv/autovec/partial/single_rgroup_run-2.c: Diito.
* gcc.target/riscv/rvv/autovec/partial/single_rgroup_run-3.c: Diito.
* gcc.target/riscv/rvv/autovec/partial/slp-1.c: Diito.
* gcc.target/riscv/rvv/autovec/partial/slp-10.c: Diito.
* gcc.target/riscv/rvv/autovec/partial/slp-11.c: Diito.
* gcc.target/riscv/rvv/autovec/partial/slp-12.c: Diito.
* gcc.target/riscv/rvv/autovec/partial/slp-13.c: Diito.
* gcc.target/riscv/rvv/autovec/partial/slp-14.c: Diito.
* gcc.target/riscv/rvv/autovec/partial/slp-15.c: Diito.
* gcc.target/riscv/rvv/autovec/partial/slp-16.c: Diito.
* gcc.target/riscv/rvv/autovec/partial/slp-17.c: Diito.
* gcc.target/riscv/rvv/autovec/partial/slp-18.c: Diito.
* gcc.target/riscv/rvv/autovec/partial/slp-19.c: Diito.
* gcc.target/riscv/rvv/autovec/partial/slp-2.c: Diito.
* gcc.target/riscv/rvv/autovec/partial/slp-3.c: Diito.
* gcc.target/riscv/rvv/autovec/partial/slp-4.c: Diito.
* gcc.target/riscv/rvv/autovec/partial/slp-5.c: Diito.
* gcc.target/riscv/rvv/autovec/partial/slp-6.c: Diito.
* gcc.target/riscv/rvv/autovec/partial/slp-7.c: Diito.
* gcc.target/riscv/rvv/autovec/partial/slp-8.c: Diito.
* gcc.target/riscv/rvv/autovec/partial/slp-9.c: Diito.
* gcc.target/riscv/rvv/autovec/partial/slp_run-1.c: Diito.
* gcc.target/riscv/rvv/autovec/partial/slp_run-10.c: Diito.
* gcc.target/riscv/rvv/autovec/partial/slp_run-11.c: Diito.
* gcc.target/riscv/rvv/autovec/partial/slp_run-12.c: Diito.
* gcc.target/riscv/rvv/autovec/partial/slp_run-13.c: Diito.
* gcc.target/riscv/rvv/autovec/partial/slp_run-14.c: Diito.
* gcc.target/riscv/rvv/autovec/partial/slp_run-15.c: Diito.
* gcc.target/riscv/rvv/autovec/partial/slp_run-16.c: Diito.
* gcc.target/riscv/rvv/autovec/partial/slp_run-17.c: Diito.
* gcc.target/riscv/rvv/autovec/partial/slp_run-18.c: Diito.
* gcc.target/riscv/rvv/autovec/partial/slp_run-19.c: Diito.
* gcc.target/riscv/rvv/autovec/partial/slp_run-2.c: Diito.
* gcc.target/riscv/rvv/autovec/partial/slp_run-3.c: Diito.
* gcc.target/riscv/rvv/autovec/partial/slp_run-4.c: Diito.
* gcc.target/riscv/rvv/autovec/partial/slp_run-5.c: Diito.
* gcc.target/riscv/rvv/autovec/partial/slp_run-6.c: Diito.
* gcc.target/riscv/rvv/autovec/partial/slp_run-7.c: Diito.
* gcc.target/riscv/rvv/autovec/partial/slp_run-8.c: Diito.
* gcc.target/riscv/rvv/autovec/partial/slp_run-9.c: Diito.
* gcc.target/riscv/rvv/autovec/post-ra-avl.c: Diito.
* gcc.target/riscv/rvv/autovec/pr110950.c: Diito.
* gcc.target/riscv/rvv/autovec/pr110964.c: Diito.
* gcc.target/riscv/rvv/autovec/pr110989.c: Diito.
* gcc.target/riscv/rvv/autovec/pr111232.c: Diito.
* gcc.target/riscv/rvv/autovec/pr111295.c: Diito.
* gcc.target/riscv/rvv/autovec/pr111313.c: Diito.
* gcc.target/riscv/rvv/autovec/pr112326.c: Diito.
* gcc.target/riscv/rvv/autovec/pr112552.c: Diito.
* gcc.target/riscv/rvv/autovec/pr112554.c: Diito.
* gcc.target/riscv/rvv/autovec/pr112561.c: Diito.
* gcc.target/riscv/rvv/autovec/pr112597-1.c: Diito.
* gcc.target/riscv/rvv/autovec/pr112599-1.c: Diito.
* gcc.target/riscv/rvv/autovec/pr112599-3.c: Diito.
* gcc.target/riscv/rvv/autovec/pr112694-1.c: Diito.
* gcc.target/riscv/rvv/autovec/pr112854.c: Diito.
* gcc.target/riscv/rvv/autovec/pr112872.c: Diito.
* gcc.target/riscv/rvv/autovec/pr112999.c: Diito.
* gcc.target/riscv/rvv/autovec/pr113393-1.c: Diito.
* gcc.target/riscv/rvv/autovec/pr113393-2.c: Diito.
* gcc.target/riscv/rvv/autovec/pr113393-3.c: Diito.
* gcc.target/riscv/rvv/autovec/reduc/extract_last-1.c: Diito.
* gcc.target/riscv/rvv/autovec/reduc/extract_last-10.c: Diito.
* gcc.target/riscv/rvv/autovec/reduc/extract_last-11.c: Diito.
* gcc.target/riscv/rvv/autovec/reduc/extract_last-12.c: Diito.
* gcc.target/riscv/rvv/autovec/reduc/extract_last-13.c: Diito.
* gcc.target/riscv/rvv/autovec/reduc/extract_last-14.c: Diito.
* gcc.target/riscv/rvv/autovec/reduc/extract_last-2.c: Diito.
* gcc.target/riscv/rvv/autovec/reduc/extract_last-3.c: Diito.
* gcc.target/riscv/rvv/autovec/reduc/extract_last-4.c: Diito.
* gcc.target/riscv/rvv/autovec/reduc/extract_last-5.c: Diito.
* gcc.target/riscv/rvv/autovec/reduc/extract_last-6.c: Diito.
* gcc.target/riscv/rvv/autovec/reduc/extract_last-7.c: Diito.
* gcc.target/riscv/rvv/autovec/reduc/extract_last-8.c: Diito.
* gcc.target/riscv/rvv/autovec/reduc/extract_last-9.c: Diito.
* gcc.target/riscv/rvv/autovec/reduc/extract_last_run-1.c: Diito.
* gcc.target/riscv/rvv/autovec/reduc/extract_last_run-10.c: Diito.
* gcc.target/riscv/rvv/autovec/reduc/extract_last_run-11.c: Diito.
* gcc.target/riscv/rvv/autovec/reduc/extract_last_run-12.c: Diito.
* gcc.target/riscv/rvv/autovec/reduc/extract_last_run-13.c: Diito.
* gcc.target/riscv/rvv/autovec/reduc/extract_last_run-14.c: Diito.
* gcc.target/riscv/rvv/autovec/reduc/extract_last_run-2.c: Diito.
* gcc.target/riscv/rvv/autovec/reduc/extract_last_run-3.c: Diito.
* gcc.target/riscv/rvv/autovec/reduc/extract_last_run-4.c: Diito.
* gcc.target/riscv/rvv/autovec/reduc/extract_last_run-5.c: Diito.
* gcc.target/riscv/rvv/autovec/reduc/extract_last_run-6.c: Diito.
* gcc.target/riscv/rvv/autovec/reduc/extract_last_run-7.c: Diito.
* gcc.target/riscv/rvv/autovec/reduc/extract_last_run-8.c: Diito.
* gcc.target/riscv/rvv/autovec/reduc/extract_last_run-9.c: Diito.
* gcc.target/riscv/rvv/autovec/reduc/reduc-1.c: Diito.
* gcc.target/riscv/rvv/autovec/reduc/reduc-10.c: Diito.
* gcc.target/riscv/rvv/autovec/reduc/reduc-2.c: Diito.
* gcc.target/riscv/rvv/autovec/reduc/reduc-3.c: Diito.
* gcc.target/riscv/rvv/autovec/reduc/reduc-4.c: Diito.
* gcc.target/riscv/rvv/autovec/reduc/reduc-5.c: Diito.
* gcc.target/riscv/rvv/autovec/reduc/reduc-6.c: Diito.
* gcc.target/riscv/rvv/autovec/reduc/reduc-7.c: Diito.
* gcc.target/riscv/rvv/autovec/reduc/reduc-8.c: Diito.
* gcc.target/riscv/rvv/autovec/reduc/reduc-9.c: Diito.
* gcc.target/riscv/rvv/autovec/reduc/reduc_call-1.c: Diito.
* gcc.target/riscv/rvv/autovec/reduc/reduc_call-2.c: Diito.
* gcc.target/riscv/rvv/autovec/reduc/reduc_call-3.c: Diito.
* gcc.target/riscv/rvv/autovec/reduc/reduc_call-4.c: Diito.
* gcc.target/riscv/rvv/autovec/reduc/reduc_call-5.c: Diito.
* gcc.target/riscv/rvv/autovec/reduc/reduc_run-1.c: Diito.
* gcc.target/riscv/rvv/autovec/reduc/reduc_run-10.c: Diito.
* gcc.target/riscv/rvv/autovec/reduc/reduc_run-2.c: Diito.
* gcc.target/riscv/rvv/autovec/reduc/reduc_run-3.c: Diito.
* gcc.target/riscv/rvv/autovec/reduc/reduc_run-4.c: Diito.
* gcc.target/riscv/rvv/autovec/reduc/reduc_run-5.c: Diito.
* gcc.target/riscv/rvv/autovec/reduc/reduc_run-6.c: Diito.
* gcc.target/riscv/rvv/autovec/reduc/reduc_run-7.c: Diito.
* gcc.target/riscv/rvv/autovec/reduc/reduc_run-8.c: Diito.
* gcc.target/riscv/rvv/autovec/reduc/reduc_strict-1.c: Diito.
* gcc.target/riscv/rvv/autovec/reduc/reduc_strict-2.c: Diito.
* gcc.target/riscv/rvv/autovec/reduc/reduc_strict-3.c: Diito.
* gcc.target/riscv/rvv/autovec/reduc/reduc_strict-4.c: Diito.
* gcc.target/riscv/rvv/autovec/reduc/reduc_strict-5.c: Diito.
* gcc.target/riscv/rvv/autovec/reduc/reduc_strict-6.c: Diito.
* gcc.target/riscv/rvv/autovec/reduc/reduc_strict-7.c: Diito.
* gcc.target/riscv/rvv/autovec/reduc/reduc_strict_run-1.c: Diito.
* gcc.target/riscv/rvv/autovec/reduc/reduc_strict_run-2.c: Diito.
* gcc.target/riscv/rvv/autovec/reduc/reduc_zvfh-10.c: Diito.
* gcc.target/riscv/rvv/autovec/reduc/reduc_zvfh_run-10.c: Diito.
* gcc.target/riscv/rvv/autovec/scalable-1.c: Diito.
* gcc.target/riscv/rvv/autovec/series-1.c: Diito.
* gcc.target/riscv/rvv/autovec/series_run-1.c: Diito.
* gcc.target/riscv/rvv/autovec/slp-mask-1.c: Diito.
* gcc.target/riscv/rvv/autovec/slp-mask-run-1.c: Diito.
* gcc.target/riscv/rvv/autovec/struct/mask_struct_load-1.c: Diito.
* gcc.target/riscv/rvv/autovec/struct/mask_struct_load-2.c: Diito.
* gcc.target/riscv/rvv/autovec/struct/mask_struct_load-3.c: Diito.
* gcc.target/riscv/rvv/autovec/struct/mask_struct_load-4.c: Diito.
* gcc.target/riscv/rvv/autovec/struct/mask_struct_load-5.c: Diito.
* gcc.target/riscv/rvv/autovec/struct/mask_struct_load-6.c: Diito.
* gcc.target/riscv/rvv/autovec/struct/mask_struct_load-7.c: Diito.
* gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-1.c: Diito.
* gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-2.c: Diito.
* gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-3.c: Diito.
* gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-4.c: Diito.
* gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-5.c: Diito.
* gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-6.c: Diito.
* gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-7.c: Diito.
* gcc.target/riscv/rvv/autovec/struct/mask_struct_store-1.c: Diito.
* gcc.target/riscv/rvv/autovec/struct/mask_struct_store-2.c: Diito.
* gcc.target/riscv/rvv/autovec/struct/mask_struct_store-3.c: Diito.
* gcc.target/riscv/rvv/autovec/struct/mask_struct_store-4.c: Diito.
* gcc.target/riscv/rvv/autovec/struct/mask_struct_store-5.c: Diito.
* gcc.target/riscv/rvv/autovec/struct/mask_struct_store-6.c: Diito.
* gcc.target/riscv/rvv/autovec/struct/mask_struct_store-7.c: Diito.
* gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-1.c: Diito.
* gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-2.c: Diito.
* gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-3.c: Diito.
* gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-4.c: Diito.
* gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-5.c: Diito.
* gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-6.c: Diito.
* gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-7.c: Diito.
* gcc.target/riscv/rvv/autovec/struct/struct_vect-1.c: Diito.
* gcc.target/riscv/rvv/autovec/struct/struct_vect-10.c: Diito.
* gcc.target/riscv/rvv/autovec/struct/struct_vect-11.c: Diito.
* gcc.target/riscv/rvv/autovec/struct/struct_vect-12.c: Diito.
* gcc.target/riscv/rvv/autovec/struct/struct_vect-13.c: Diito.
* gcc.target/riscv/rvv/autovec/struct/struct_vect-14.c: Diito.
* gcc.target/riscv/rvv/autovec/struct/struct_vect-15.c: Diito.
* gcc.target/riscv/rvv/autovec/struct/struct_vect-16.c: Diito.
* gcc.target/riscv/rvv/autovec/struct/struct_vect-17.c: Diito.
* gcc.target/riscv/rvv/autovec/struct/struct_vect-18.c: Diito.
* gcc.target/riscv/rvv/autovec/struct/struct_vect-2.c: Diito.
* gcc.target/riscv/rvv/autovec/struct/struct_vect-3.c: Diito.
* gcc.target/riscv/rvv/autovec/struct/struct_vect-4.c: Diito.
* gcc.target/riscv/rvv/autovec/struct/struct_vect-5.c: Diito.
* gcc.target/riscv/rvv/autovec/struct/struct_vect-6.c: Diito.
* gcc.target/riscv/rvv/autovec/struct/struct_vect-7.c: Diito.
* gcc.target/riscv/rvv/autovec/struct/struct_vect-8.c: Diito.
* gcc.target/riscv/rvv/autovec/struct/struct_vect-9.c: Diito.
* gcc.target/riscv/rvv/autovec/struct/struct_vect_run-1.c: Diito.
* gcc.target/riscv/rvv/autovec/struct/struct_vect_run-10.c: Diito.
* gcc.target/riscv/rvv/autovec/struct/struct_vect_run-11.c: Diito.
* gcc.target/riscv/rvv/autovec/struct/struct_vect_run-12.c: Diito.
* gcc.target/riscv/rvv/autovec/struct/struct_vect_run-13.c: Diito.
* gcc.target/riscv/rvv/autovec/struct/struct_vect_run-14.c: Diito.
* gcc.target/riscv/rvv/autovec/struct/struct_vect_run-15.c: Diito.
* gcc.target/riscv/rvv/autovec/struct/struct_vect_run-16.c: Diito.
* gcc.target/riscv/rvv/autovec/struct/struct_vect_run-17.c: Diito.
* gcc.target/riscv/rvv/autovec/struct/struct_vect_run-18.c: Diito.
* gcc.target/riscv/rvv/autovec/struct/struct_vect_run-2.c: Diito.
* gcc.target/riscv/rvv/autovec/struct/struct_vect_run-3.c: Diito.
* gcc.target/riscv/rvv/autovec/struct/struct_vect_run-4.c: Diito.
* gcc.target/riscv/rvv/autovec/struct/struct_vect_run-5.c: Diito.
* gcc.target/riscv/rvv/autovec/struct/struct_vect_run-6.c: Diito.
* gcc.target/riscv/rvv/autovec/struct/struct_vect_run-7.c: Diito.
* gcc.target/riscv/rvv/autovec/struct/struct_vect_run-8.c: Diito.
* gcc.target/riscv/rvv/autovec/struct/struct_vect_run-9.c: Diito.
* gcc.target/riscv/rvv/autovec/ternop/ternop-1.c: Diito.
* gcc.target/riscv/rvv/autovec/ternop/ternop-10.c: Diito.
* gcc.target/riscv/rvv/autovec/ternop/ternop-11.c: Diito.
* gcc.target/riscv/rvv/autovec/ternop/ternop-12.c: Diito.
* gcc.target/riscv/rvv/autovec/ternop/ternop-2.c: Diito.
* gcc.target/riscv/rvv/autovec/ternop/ternop-3.c: Diito.
* gcc.target/riscv/rvv/autovec/ternop/ternop-4.c: Diito.
* gcc.target/riscv/rvv/autovec/ternop/ternop-5.c: Diito.
* gcc.target/riscv/rvv/autovec/ternop/ternop-6.c: Diito.
* gcc.target/riscv/rvv/autovec/ternop/ternop-7.c: Diito.
* gcc.target/riscv/rvv/autovec/ternop/ternop-8.c: Diito.
* gcc.target/riscv/rvv/autovec/ternop/ternop-9.c: Diito.
* gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-1.c: Diito.
* gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-10.c: Diito.
* gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-11.c: Diito.
* gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-12.c: Diito.
* gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-2.c: Diito.
* gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-3.c: Diito.
* gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-4.c: Diito.
* gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-5.c: Diito.
* gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-6.c: Diito.
* gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-7.c: Diito.
* gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-8.c: Diito.
* gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-9.c: Diito.
* gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-1.c: Diito.
* gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-10.c: Diito.
* gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-11.c: Diito.
* gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-12.c: Diito.
* gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-2.c: Diito.
* gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-3.c: Diito.
* gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-4.c: Diito.
* gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-5.c: Diito.
* gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-6.c: Diito.
* gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-7.c: Diito.
* gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-8.c: Diito.
* gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-9.c: Diito.
* gcc.target/riscv/rvv/autovec/ternop/ternop_run-1.c: Diito.
* gcc.target/riscv/rvv/autovec/ternop/ternop_run-10.c: Diito.
* gcc.target/riscv/rvv/autovec/ternop/ternop_run-11.c: Diito.
* gcc.target/riscv/rvv/autovec/ternop/ternop_run-12.c: Diito.
* gcc.target/riscv/rvv/autovec/ternop/ternop_run-2.c: Diito.
* gcc.target/riscv/rvv/autovec/ternop/ternop_run-3.c: Diito.
* gcc.target/riscv/rvv/autovec/ternop/ternop_run-4.c: Diito.
* gcc.target/riscv/rvv/autovec/ternop/ternop_run-5.c: Diito.
* gcc.target/riscv/rvv/autovec/ternop/ternop_run-6.c: Diito.
* gcc.target/riscv/rvv/autovec/ternop/ternop_run-7.c: Diito.
* gcc.target/riscv/rvv/autovec/ternop/ternop_run-8.c: Diito.
* gcc.target/riscv/rvv/autovec/ternop/ternop_run-9.c: Diito.
* gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-1.c: Diito.
* gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-10.c: Diito.
* gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-11.c: Diito.
* gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-12.c: Diito.
* gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-2.c: Diito.
* gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-3.c: Diito.
* gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-4.c: Diito.
* gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-5.c: Diito.
* gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-6.c: Diito.
* gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-7.c: Diito.
* gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-8.c: Diito.
* gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-9.c: Diito.
* gcc.target/riscv/rvv/autovec/unop/abs-run.c: Diito.
* gcc.target/riscv/rvv/autovec/unop/abs-rv32gcv.c: Diito.
* gcc.target/riscv/rvv/autovec/unop/abs-rv64gcv.c: Diito.
* gcc.target/riscv/rvv/autovec/unop/abs-zvfh-run.c: Diito.
* gcc.target/riscv/rvv/autovec/unop/popcount-1.c: Diito.
* gcc.target/riscv/rvv/autovec/unop/popcount-2.c: Diito.
* gcc.target/riscv/rvv/autovec/unop/vfsqrt-run.c: Diito.
* gcc.target/riscv/rvv/autovec/unop/vfsqrt-rv32gcv.c: Diito.
* gcc.target/riscv/rvv/autovec/unop/vfsqrt-rv64gcv.c: Diito.
* gcc.target/riscv/rvv/autovec/unop/vfsqrt-zvfh-run.c: Diito.
* gcc.target/riscv/rvv/autovec/unop/vneg-run.c: Diito.
* gcc.target/riscv/rvv/autovec/unop/vneg-rv32gcv.c: Diito.
* gcc.target/riscv/rvv/autovec/unop/vneg-rv64gcv.c: Diito.
* gcc.target/riscv/rvv/autovec/unop/vneg-zvfh-run.c: Diito.
* gcc.target/riscv/rvv/autovec/unop/vnot-run.c: Diito.
* gcc.target/riscv/rvv/autovec/unop/vnot-rv32gcv.c: Diito.
* gcc.target/riscv/rvv/autovec/unop/vnot-rv64gcv.c: Diito.
* gcc.target/riscv/rvv/autovec/v-1.c: Diito.
* gcc.target/riscv/rvv/autovec/v-2.c: Diito.
* gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-1.c: Diito.
* gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-10.c: Diito.
* gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-11.c: Diito.
* gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-12.c: Diito.
* gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-13.c: Diito.
* gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-14.c: Diito.
* gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-2.c: Diito.
* gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-3.c: Diito.
* gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-4.c: Diito.
* gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-5.c: Diito.
* gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-6.c: Diito.
* gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-7.c: Diito.
* gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-8.c: Diito.
* gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-9.c: Diito.
* gcc.target/riscv/rvv/autovec/vls-vlmax/combine-1.c: Diito.
* gcc.target/riscv/rvv/autovec/vls-vlmax/combine-merge_run-1.c: Diito.
* gcc.target/riscv/rvv/autovec/vls-vlmax/combine-merge_run-2.c: Diito.
* gcc.target/riscv/rvv/autovec/vls-vlmax/compress-1.c: Diito.
* gcc.target/riscv/rvv/autovec/vls-vlmax/compress-2.c: Diito.
* gcc.target/riscv/rvv/autovec/vls-vlmax/compress-3.c: Diito.
* gcc.target/riscv/rvv/autovec/vls-vlmax/compress-4.c: Diito.
* gcc.target/riscv/rvv/autovec/vls-vlmax/compress-5.c: Diito.
* gcc.target/riscv/rvv/autovec/vls-vlmax/compress-6.c: Diito.
* gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-1.c: Diito.
* gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-2.c: Diito.
* gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-3.c: Diito.
* gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-4.c: Diito.
* gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-5.c: Diito.
* gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-6.c: Diito.
* gcc.target/riscv/rvv/autovec/vls-vlmax/consecutive-1.c: Diito.
* gcc.target/riscv/rvv/autovec/vls-vlmax/consecutive-2.c: Diito.
* gcc.target/riscv/rvv/autovec/vls-vlmax/consecutive_run-1.c: Diito.
* gcc.target/riscv/rvv/autovec/vls-vlmax/consecutive_run-2.c: Diito.
* gcc.target/riscv/rvv/autovec/vls-vlmax/full-vec-move1.c: Diito.
* gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-run-1.c: Diito.
* gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-run-2.c: Diito.
* gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-run-3.c: Diito.
* gcc.target/riscv/rvv/autovec/vls-vlmax/insert_run-1.c: Diito.
* gcc.target/riscv/rvv/autovec/vls-vlmax/insert_run-2.c: Diito.
* gcc.target/riscv/rvv/autovec/vls-vlmax/merge-1.c: Diito.
* gcc.target/riscv/rvv/autovec/vls-vlmax/merge-2.c: Diito.
* gcc.target/riscv/rvv/autovec/vls-vlmax/merge-3.c: Diito.
* gcc.target/riscv/rvv/autovec/vls-vlmax/merge-4.c: Diito.
* gcc.target/riscv/rvv/autovec/vls-vlmax/merge-5.c: Diito.
* gcc.target/riscv/rvv/autovec/vls-vlmax/merge-6.c: Diito.
* gcc.target/riscv/rvv/autovec/vls-vlmax/merge-7.c: Diito.
* gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-1.c: Diito.
* gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-2.c: Diito.
* gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-3.c: Diito.
* gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-4.c: Diito.
* gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-5.c: Diito.
* gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-6.c: Diito.
* gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-7.c: Diito.
* gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-1.c: Diito.
* gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-2.c: Diito.
* gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-3.c: Diito.
* gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-4.c: Diito.
* gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-5.c: Diito.
* gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-6.c: Diito.
* gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-7.c: Diito.
* gcc.target/riscv/rvv/autovec/vls-vlmax/pr110985.c: Diito.
* gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-1.c: Diito.
* gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-2.c: Diito.
* gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-3.c: Diito.
* gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-4.c: Diito.
* gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-5.c: Diito.
* gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-6.c: Diito.
* gcc.target/riscv/rvv/autovec/vls-vlmax/trailing-1.c: Diito.
* gcc.target/riscv/rvv/autovec/vls-vlmax/trailing-2.c: Diito.
* gcc.target/riscv/rvv/autovec/vls-vlmax/trailing_run-1.c: Diito.
* gcc.target/riscv/rvv/autovec/vls-vlmax/trailing_run-2.c: Diito.
* gcc.target/riscv/rvv/autovec/vls/calling-convention-1.c: Diito.
* gcc.target/riscv/rvv/autovec/vls/calling-convention-10.c: Diito.
* gcc.target/riscv/rvv/autovec/vls/calling-convention-2.c: Diito.
* gcc.target/riscv/rvv/autovec/vls/calling-convention-3.c: Diito.
* gcc.target/riscv/rvv/autovec/vls/calling-convention-4.c: Diito.
* gcc.target/riscv/rvv/autovec/vls/calling-convention-5.c: Diito.
* gcc.target/riscv/rvv/autovec/vls/calling-convention-6.c: Diito.
* gcc.target/riscv/rvv/autovec/vls/calling-convention-7.c: Diito.
* gcc.target/riscv/rvv/autovec/vls/calling-convention-8.c: Diito.
* gcc.target/riscv/rvv/autovec/vls/calling-convention-9.c: Diito.
* gcc.target/riscv/rvv/autovec/vls/calling-convention-run-1.c: Diito.
* gcc.target/riscv/rvv/autovec/vls/calling-convention-run-2.c: Diito.
* gcc.target/riscv/rvv/autovec/vls/calling-convention-run-3.c: Diito.
* gcc.target/riscv/rvv/autovec/vls/calling-convention-run-4.c: Diito.
* gcc.target/riscv/rvv/autovec/vls/calling-convention-run-5.c: Diito.
* gcc.target/riscv/rvv/autovec/vls/calling-convention-run-6.c: Diito.
* gcc.target/riscv/rvv/autovec/vls/pr110994.c: Diito.
* gcc.target/riscv/rvv/autovec/vmv-imm-fixed-rv32.c: Diito.
* gcc.target/riscv/rvv/autovec/vmv-imm-fixed-rv64.c: Diito.
* gcc.target/riscv/rvv/autovec/vmv-imm-run.c: Diito.
* gcc.target/riscv/rvv/autovec/vmv-imm-rv32.c: Diito.
* gcc.target/riscv/rvv/autovec/vmv-imm-rv64.c: Diito.
* gcc.target/riscv/rvv/autovec/vreinterpet-fixed.c: Diito.
* gcc.target/riscv/rvv/autovec/widen/vec-avg-run.c: Diito.
* gcc.target/riscv/rvv/autovec/widen/vec-avg-rv32gcv.c: Diito.
* gcc.target/riscv/rvv/autovec/widen/vec-avg-rv64gcv.c: Diito.
* gcc.target/riscv/rvv/autovec/widen/widen-1.c: Diito.
* gcc.target/riscv/rvv/autovec/widen/widen-10.c: Diito.
* gcc.target/riscv/rvv/autovec/widen/widen-11.c: Diito.
* gcc.target/riscv/rvv/autovec/widen/widen-12.c: Diito.
* gcc.target/riscv/rvv/autovec/widen/widen-2.c: Diito.
* gcc.target/riscv/rvv/autovec/widen/widen-3.c: Diito.
* gcc.target/riscv/rvv/autovec/widen/widen-4.c: Diito.
* gcc.target/riscv/rvv/autovec/widen/widen-5.c: Diito.
* gcc.target/riscv/rvv/autovec/widen/widen-6.c: Diito.
* gcc.target/riscv/rvv/autovec/widen/widen-7.c: Diito.
* gcc.target/riscv/rvv/autovec/widen/widen-8.c: Diito.
* gcc.target/riscv/rvv/autovec/widen/widen-9.c: Diito.
* gcc.target/riscv/rvv/autovec/widen/widen-complicate-1.c: Diito.
* gcc.target/riscv/rvv/autovec/widen/widen-complicate-2.c: Diito.
* gcc.target/riscv/rvv/autovec/widen/widen-complicate-3.c: Diito.
* gcc.target/riscv/rvv/autovec/widen/widen-complicate-4.c: Diito.
* gcc.target/riscv/rvv/autovec/widen/widen-complicate-5.c: Diito.
* gcc.target/riscv/rvv/autovec/widen/widen-complicate-6.c: Diito.
* gcc.target/riscv/rvv/autovec/widen/widen-complicate-7.c: Diito.
* gcc.target/riscv/rvv/autovec/widen/widen-complicate-8.c: Diito.
* gcc.target/riscv/rvv/autovec/widen/widen-complicate-9.c: Diito.
* gcc.target/riscv/rvv/autovec/widen/widen_reduc-1.c: Diito.
* gcc.target/riscv/rvv/autovec/widen/widen_reduc_order-1.c: Diito.
* gcc.target/riscv/rvv/autovec/widen/widen_reduc_order-2.c: Diito.
* gcc.target/riscv/rvv/autovec/widen/widen_reduc_order_run-1.c: Diito.
* gcc.target/riscv/rvv/autovec/widen/widen_reduc_order_run-2.c: Diito.
* gcc.target/riscv/rvv/autovec/widen/widen_reduc_run-1.c: Diito.
* gcc.target/riscv/rvv/autovec/widen/widen_run-1.c: Diito.
* gcc.target/riscv/rvv/autovec/widen/widen_run-10.c: Diito.
* gcc.target/riscv/rvv/autovec/widen/widen_run-11.c: Diito.
* gcc.target/riscv/rvv/autovec/widen/widen_run-12.c: Diito.
* gcc.target/riscv/rvv/autovec/widen/widen_run-2.c: Diito.
* gcc.target/riscv/rvv/autovec/widen/widen_run-3.c: Diito.
* gcc.target/riscv/rvv/autovec/widen/widen_run-4.c: Diito.
* gcc.target/riscv/rvv/autovec/widen/widen_run-5.c: Diito.
* gcc.target/riscv/rvv/autovec/widen/widen_run-6.c: Diito.
* gcc.target/riscv/rvv/autovec/widen/widen_run-7.c: Diito.
* gcc.target/riscv/rvv/autovec/widen/widen_run-8.c: Diito.
* gcc.target/riscv/rvv/autovec/widen/widen_run-9.c: Diito.
* gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-1.c: Diito.
* gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-10.c: Diito.
* gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-11.c: Diito.
* gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-12.c: Diito.
* gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-2.c: Diito.
* gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-3.c: Diito.
* gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-5.c: Diito.
* gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-6.c: Diito.
* gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-7.c: Diito.
* gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-8.c: Diito.
* gcc.target/riscv/rvv/autovec/zve32f-1.c: Diito.
* gcc.target/riscv/rvv/autovec/zve32f-2.c: Diito.
* gcc.target/riscv/rvv/autovec/zve32f-3.c: Diito.
* gcc.target/riscv/rvv/autovec/zve32f_zvl1024b-1.c: Diito.
* gcc.target/riscv/rvv/autovec/zve32f_zvl128b-1.c: Diito.
* gcc.target/riscv/rvv/autovec/zve32f_zvl128b-2.c: Diito.
* gcc.target/riscv/rvv/autovec/zve32f_zvl2048b-1.c: Diito.
* gcc.target/riscv/rvv/autovec/zve32f_zvl256b-1.c: Diito.
* gcc.target/riscv/rvv/autovec/zve32f_zvl4096b-1.c: Diito.
* gcc.target/riscv/rvv/autovec/zve32f_zvl512b-1.c: Diito.
* gcc.target/riscv/rvv/autovec/zve32x-1.c: Diito.
* gcc.target/riscv/rvv/autovec/zve32x-2.c: Diito.
* gcc.target/riscv/rvv/autovec/zve32x-3.c: Diito.
* gcc.target/riscv/rvv/autovec/zve32x_zvl1024b-1.c: Diito.
* gcc.target/riscv/rvv/autovec/zve32x_zvl128b-1.c: Diito.
* gcc.target/riscv/rvv/autovec/zve32x_zvl128b-2.c: Diito.
* gcc.target/riscv/rvv/autovec/zve32x_zvl2048b-1.c: Diito.
* gcc.target/riscv/rvv/autovec/zve32x_zvl256b-1.c: Diito.
* gcc.target/riscv/rvv/autovec/zve32x_zvl4096b-1.c: Diito.
* gcc.target/riscv/rvv/autovec/zve32x_zvl512b-1.c: Diito.
* gcc.target/riscv/rvv/autovec/zve64d-1.c: Diito.
* gcc.target/riscv/rvv/autovec/zve64d-2.c: Diito.
* gcc.target/riscv/rvv/autovec/zve64d-3.c: Diito.
* gcc.target/riscv/rvv/autovec/zve64d_zvl1024b-1.c: Diito.
* gcc.target/riscv/rvv/autovec/zve64d_zvl128b-1.c: Diito.
* gcc.target/riscv/rvv/autovec/zve64d_zvl128b-2.c: Diito.
* gcc.target/riscv/rvv/autovec/zve64d_zvl2048b-1.c: Diito.
* gcc.target/riscv/rvv/autovec/zve64d_zvl256b-1.c: Diito.
* gcc.target/riscv/rvv/autovec/zve64d_zvl4096b-1.c: Diito.
* gcc.target/riscv/rvv/autovec/zve64d_zvl512b-1.c: Diito.
* gcc.target/riscv/rvv/autovec/zve64f-1.c: Diito.
* gcc.target/riscv/rvv/autovec/zve64f-2.c: Diito.
* gcc.target/riscv/rvv/autovec/zve64f-3.c: Diito.
* gcc.target/riscv/rvv/autovec/zve64f_zvl1024b-1.c: Diito.
* gcc.target/riscv/rvv/autovec/zve64f_zvl128b-1.c: Diito.
* gcc.target/riscv/rvv/autovec/zve64f_zvl128b-2.c: Diito.
* gcc.target/riscv/rvv/autovec/zve64f_zvl2048b-1.c: Diito.
* gcc.target/riscv/rvv/autovec/zve64f_zvl256b-1.c: Diito.
* gcc.target/riscv/rvv/autovec/zve64f_zvl4096b-1.c: Diito.
* gcc.target/riscv/rvv/autovec/zve64f_zvl512b-1.c: Diito.
* gcc.target/riscv/rvv/autovec/zve64x-1.c: Diito.
* gcc.target/riscv/rvv/autovec/zve64x-2.c: Diito.
* gcc.target/riscv/rvv/autovec/zve64x-3.c: Diito.
* gcc.target/riscv/rvv/autovec/zve64x_zvl1024b-1.c: Diito.
* gcc.target/riscv/rvv/autovec/zve64x_zvl128b-1.c: Diito.
* gcc.target/riscv/rvv/autovec/zve64x_zvl128b-2.c: Diito.
* gcc.target/riscv/rvv/autovec/zve64x_zvl2048b-1.c: Diito.
* gcc.target/riscv/rvv/autovec/zve64x_zvl256b-1.c: Diito.
* gcc.target/riscv/rvv/autovec/zve64x_zvl4096b-1.c: Diito.
* gcc.target/riscv/rvv/autovec/zve64x_zvl512b-1.c: Diito.
* gcc.target/riscv/rvv/autovec/zvfhmin-1.c: Diito.
* gcc.target/riscv/rvv/base/abi-callee-saved-1-fixed-1.c: Diito.
* gcc.target/riscv/rvv/base/abi-callee-saved-1-fixed-2.c: Diito.
* gcc.target/riscv/rvv/base/cpymem-1.c: Diito.
* gcc.target/riscv/rvv/base/cpymem-2.c: Diito.
* gcc.target/riscv/rvv/base/cpymem-strategy-3.c: Diito.
* gcc.target/riscv/rvv/base/cpymem-strategy-4.c: Diito.
* gcc.target/riscv/rvv/base/float-point-dynamic-frm-77.c: Diito.
* gcc.target/riscv/rvv/base/float-point-frm-autovec-1.c: Diito.
* gcc.target/riscv/rvv/base/float-point-frm-autovec-2.c: Diito.
* gcc.target/riscv/rvv/base/float-point-frm-autovec-3.c: Diito.
* gcc.target/riscv/rvv/base/float-point-frm-autovec-4.c: Diito.
* gcc.target/riscv/rvv/base/poly-selftest-1.c: Diito.
* gcc.target/riscv/rvv/base/pr110119-1.c: Diito.
* gcc.target/riscv/rvv/base/pr110119-2.c: Diito.
* gcc.target/riscv/rvv/base/pr111720-0.c: Diito.
* gcc.target/riscv/rvv/base/pr111720-1.c: Diito.
* gcc.target/riscv/rvv/base/pr111720-10.c: Diito.
* gcc.target/riscv/rvv/base/pr111720-2.c: Diito.
* gcc.target/riscv/rvv/base/pr111720-3.c: Diito.
* gcc.target/riscv/rvv/base/pr111720-4.c: Diito.
* gcc.target/riscv/rvv/base/pr111720-5.c: Diito.
* gcc.target/riscv/rvv/base/pr111720-6.c: Diito.
* gcc.target/riscv/rvv/base/pr111720-7.c: Diito.
* gcc.target/riscv/rvv/base/pr111720-8.c: Diito.
* gcc.target/riscv/rvv/base/pr111720-9.c: Diito.
* gcc.target/riscv/rvv/base/vf_avl-1.c: Diito.
* gcc.target/riscv/rvv/base/vf_avl-2.c: Diito.
* gcc.target/riscv/rvv/base/vf_avl-3.c: Diito.
* gcc.target/riscv/rvv/base/vf_avl-4.c: Diito.
* gcc.target/riscv/rvv/base/zvl-unimplemented-1.c: Diito.
* gcc.target/riscv/rvv/base/zvl-unimplemented-2.c: Diito.
* gcc.target/riscv/rvv/rvv.exp: Diito.
* gcc.target/riscv/rvv/vsetvl/avl_multiple-1.c: Diito.
* gcc.target/riscv/rvv/vsetvl/avl_multiple-10.c: Diito.
* gcc.target/riscv/rvv/vsetvl/avl_multiple-11.c: Diito.
* gcc.target/riscv/rvv/vsetvl/avl_multiple-12.c: Diito.
* gcc.target/riscv/rvv/vsetvl/avl_multiple-13.c: Diito.
* gcc.target/riscv/rvv/vsetvl/avl_multiple-14.c: Diito.
* gcc.target/riscv/rvv/vsetvl/avl_multiple-15.c: Diito.
* gcc.target/riscv/rvv/vsetvl/avl_multiple-16.c: Diito.
* gcc.target/riscv/rvv/vsetvl/avl_multiple-2.c: Diito.
* gcc.target/riscv/rvv/vsetvl/avl_multiple-3.c: Diito.
* gcc.target/riscv/rvv/vsetvl/avl_multiple-4.c: Diito.
* gcc.target/riscv/rvv/vsetvl/avl_multiple-5.c: Diito.
* gcc.target/riscv/rvv/vsetvl/avl_multiple-6.c: Diito.
* gcc.target/riscv/rvv/vsetvl/avl_multiple-7.c: Diito.
* gcc.target/riscv/rvv/vsetvl/avl_multiple-8.c: Diito.
* gcc.target/riscv/rvv/vsetvl/avl_multiple-9.c: Diito.
* gcc.target/riscv/rvv/vsetvl/avl_prop-1.c: Diito.
* gcc.target/riscv/rvv/vsetvl/avl_prop-2.c: Diito.
* gcc.target/riscv/rvv/vsetvl/avl_single-1.c: Diito.
* gcc.target/riscv/rvv/vsetvl/avl_single-10.c: Diito.
* gcc.target/riscv/rvv/vsetvl/avl_single-100.c: Diito.
* gcc.target/riscv/rvv/vsetvl/avl_single-101.c: Diito.
* gcc.target/riscv/rvv/vsetvl/avl_single-102.c: Diito.
* gcc.target/riscv/rvv/vsetvl/avl_single-103.c: Diito.
* gcc.target/riscv/rvv/vsetvl/avl_single-104.c: Diito.
* gcc.target/riscv/rvv/vsetvl/avl_single-105.c: Diito.
* gcc.target/riscv/rvv/vsetvl/avl_single-106.c: Diito.
* gcc.target/riscv/rvv/vsetvl/avl_single-107.c: Diito.
* gcc.target/riscv/rvv/vsetvl/avl_single-108.c: Diito.
* gcc.target/riscv/rvv/vsetvl/avl_single-109.c: Diito.
* gcc.target/riscv/rvv/vsetvl/avl_single-11.c: Diito.
* gcc.target/riscv/rvv/vsetvl/avl_single-12.c: Diito.
* gcc.target/riscv/rvv/vsetvl/avl_single-13.c: Diito.
* gcc.target/riscv/rvv/vsetvl/avl_single-14.c: Diito.
* gcc.target/riscv/rvv/vsetvl/avl_single-15.c: Diito.
* gcc.target/riscv/rvv/vsetvl/avl_single-16.c: Diito.
* gcc.target/riscv/rvv/vsetvl/avl_single-17.c: Diito.
* gcc.target/riscv/rvv/vsetvl/avl_single-18.c: Diito.
* gcc.target/riscv/rvv/vsetvl/avl_single-19.c: Diito.
* gcc.target/riscv/rvv/vsetvl/avl_single-2.c: Diito.
* gcc.target/riscv/rvv/vsetvl/avl_single-20.c: Diito.
* gcc.target/riscv/rvv/vsetvl/avl_single-21.c: Diito.
* gcc.target/riscv/rvv/vsetvl/avl_single-22.c: Diito.
* gcc.target/riscv/rvv/vsetvl/avl_single-23.c: Diito.
* gcc.target/riscv/rvv/vsetvl/avl_single-24.c: Diito.
* gcc.target/riscv/rvv/vsetvl/avl_single-25.c: Diito.
* gcc.target/riscv/rvv/vsetvl/avl_single-26.c: Diito.
* gcc.target/riscv/rvv/vsetvl/avl_single-27.c: Diito.
* gcc.target/riscv/rvv/vsetvl/avl_single-28.c: Diito.
* gcc.target/riscv/rvv/vsetvl/avl_single-29.c: Diito.
* gcc.target/riscv/rvv/vsetvl/avl_single-3.c: Diito.
* gcc.target/riscv/rvv/vsetvl/avl_single-30.c: Diito.
* gcc.target/riscv/rvv/vsetvl/avl_single-31.c: Diito.
* gcc.target/riscv/rvv/vsetvl/avl_single-32.c: Diito.
* gcc.target/riscv/rvv/vsetvl/avl_single-33.c: Diito.
* gcc.target/riscv/rvv/vsetvl/avl_single-34.c: Diito.
* gcc.target/riscv/rvv/vsetvl/avl_single-35.c: Diito.
* gcc.target/riscv/rvv/vsetvl/avl_single-36.c: Diito.
* gcc.target/riscv/rvv/vsetvl/avl_single-37.c: Diito.
* gcc.target/riscv/rvv/vsetvl/avl_single-38.c: Diito.
* gcc.target/riscv/rvv/vsetvl/avl_single-39.c: Diito.
* gcc.target/riscv/rvv/vsetvl/avl_single-4.c: Diito.
* gcc.target/riscv/rvv/vsetvl/avl_single-40.c: Diito.
* gcc.target/riscv/rvv/vsetvl/avl_single-41.c: Diito.
* gcc.target/riscv/rvv/vsetvl/avl_single-42.c: Diito.
* gcc.target/riscv/rvv/vsetvl/avl_single-43.c: Diito.
* gcc.target/riscv/rvv/vsetvl/avl_single-44.c: Diito.
* gcc.target/riscv/rvv/vsetvl/avl_single-45.c: Diito.
* gcc.target/riscv/rvv/vsetvl/avl_single-46.c: Diito.
* gcc.target/riscv/rvv/vsetvl/avl_single-47.c: Diito.
* gcc.target/riscv/rvv/vsetvl/avl_single-48.c: Diito.
* gcc.target/riscv/rvv/vsetvl/avl_single-49.c: Diito.
* gcc.target/riscv/rvv/vsetvl/avl_single-5.c: Diito.
* gcc.target/riscv/rvv/vsetvl/avl_single-50.c: Diito.
* gcc.target/riscv/rvv/vsetvl/avl_single-51.c: Diito.
* gcc.target/riscv/rvv/vsetvl/avl_single-52.c: Diito.
* gcc.target/riscv/rvv/vsetvl/avl_single-53.c: Diito.
* gcc.target/riscv/rvv/vsetvl/avl_single-54.c: Diito.
* gcc.target/riscv/rvv/vsetvl/avl_single-55.c: Diito.
* gcc.target/riscv/rvv/vsetvl/avl_single-56.c: Diito.
* gcc.target/riscv/rvv/vsetvl/avl_single-57.c: Diito.
* gcc.target/riscv/rvv/vsetvl/avl_single-58.c: Diito.
* gcc.target/riscv/rvv/vsetvl/avl_single-59.c: Diito.
* gcc.target/riscv/rvv/vsetvl/avl_single-6.c: Diito.
* gcc.target/riscv/rvv/vsetvl/avl_single-60.c: Diito.
* gcc.target/riscv/rvv/vsetvl/avl_single-61.c: Diito.
* gcc.target/riscv/rvv/vsetvl/avl_single-62.c: Diito.
* gcc.target/riscv/rvv/vsetvl/avl_single-63.c: Diito.
* gcc.target/riscv/rvv/vsetvl/avl_single-64.c: Diito.
* gcc.target/riscv/rvv/vsetvl/avl_single-65.c: Diito.
* gcc.target/riscv/rvv/vsetvl/avl_single-66.c: Diito.
* gcc.target/riscv/rvv/vsetvl/avl_single-67.c: Diito.
* gcc.target/riscv/rvv/vsetvl/avl_single-68.c: Diito.
* gcc.target/riscv/rvv/vsetvl/avl_single-69.c: Diito.
* gcc.target/riscv/rvv/vsetvl/avl_single-7.c: Diito.
* gcc.target/riscv/rvv/vsetvl/avl_single-70.c: Diito.
* gcc.target/riscv/rvv/vsetvl/avl_single-71.c: Diito.
* gcc.target/riscv/rvv/vsetvl/avl_single-72.c: Diito.
* gcc.target/riscv/rvv/vsetvl/avl_single-73.c: Diito.
* gcc.target/riscv/rvv/vsetvl/avl_single-74.c: Diito.
* gcc.target/riscv/rvv/vsetvl/avl_single-75.c: Diito.
* gcc.target/riscv/rvv/vsetvl/avl_single-76.c: Diito.
* gcc.target/riscv/rvv/vsetvl/avl_single-77.c: Diito.
* gcc.target/riscv/rvv/vsetvl/avl_single-78.c: Diito.
* gcc.target/riscv/rvv/vsetvl/avl_single-79.c: Diito.
* gcc.target/riscv/rvv/vsetvl/avl_single-8.c: Diito.
* gcc.target/riscv/rvv/vsetvl/avl_single-80.c: Diito.
* gcc.target/riscv/rvv/vsetvl/avl_single-81.c: Diito.
* gcc.target/riscv/rvv/vsetvl/avl_single-82.c: Diito.
* gcc.target/riscv/rvv/vsetvl/avl_single-83.c: Diito.
* gcc.target/riscv/rvv/vsetvl/avl_single-84.c: Diito.
* gcc.target/riscv/rvv/vsetvl/avl_single-85.c: Diito.
* gcc.target/riscv/rvv/vsetvl/avl_single-86.c: Diito.
* gcc.target/riscv/rvv/vsetvl/avl_single-87.c: Diito.
* gcc.target/riscv/rvv/vsetvl/avl_single-88.c: Diito.
* gcc.target/riscv/rvv/vsetvl/avl_single-89.c: Diito.
* gcc.target/riscv/rvv/vsetvl/avl_single-9.c: Diito.
* gcc.target/riscv/rvv/vsetvl/avl_single-90.c: Diito.
* gcc.target/riscv/rvv/vsetvl/avl_single-91.c: Diito.
* gcc.target/riscv/rvv/vsetvl/avl_single-92.c: Diito.
* gcc.target/riscv/rvv/vsetvl/avl_single-93.c: Diito.
* gcc.target/riscv/rvv/vsetvl/avl_single-94.c: Diito.
* gcc.target/riscv/rvv/vsetvl/avl_single-95.c: Diito.
* gcc.target/riscv/rvv/vsetvl/avl_single-96.c: Diito.
* gcc.target/riscv/rvv/vsetvl/avl_single-97.c: Diito.
* gcc.target/riscv/rvv/vsetvl/avl_single-98.c: Diito.
* gcc.target/riscv/rvv/vsetvl/avl_single-99.c: Diito.
* gcc.target/riscv/rvv/vsetvl/dump-1.c: Diito.
* gcc.target/riscv/rvv/vsetvl/ffload-1.c: Diito.
* gcc.target/riscv/rvv/vsetvl/ffload-2.c: Diito.
* gcc.target/riscv/rvv/vsetvl/ffload-3.c: Diito.
* gcc.target/riscv/rvv/vsetvl/ffload-5.c: Diito.
* gcc.target/riscv/rvv/vsetvl/ffload-6.c: Diito.
* gcc.target/riscv/rvv/vsetvl/ffload-7.c: Diito.
* gcc.target/riscv/rvv/vsetvl/imm_bb_prop-1.c: Diito.
* gcc.target/riscv/rvv/vsetvl/imm_bb_prop-10.c: Diito.
* gcc.target/riscv/rvv/vsetvl/imm_bb_prop-11.c: Diito.
* gcc.target/riscv/rvv/vsetvl/imm_bb_prop-12.c: Diito.
* gcc.target/riscv/rvv/vsetvl/imm_bb_prop-13.c: Diito.
* gcc.target/riscv/rvv/vsetvl/imm_bb_prop-2.c: Diito.
* gcc.target/riscv/rvv/vsetvl/imm_bb_prop-3.c: Diito.
* gcc.target/riscv/rvv/vsetvl/imm_bb_prop-4.c: Diito.
* gcc.target/riscv/rvv/vsetvl/imm_bb_prop-5.c: Diito.
* gcc.target/riscv/rvv/vsetvl/imm_bb_prop-6.c: Diito.
* gcc.target/riscv/rvv/vsetvl/imm_bb_prop-7.c: Diito.
* gcc.target/riscv/rvv/vsetvl/imm_bb_prop-8.c: Diito.
* gcc.target/riscv/rvv/vsetvl/imm_bb_prop-9.c: Diito.
* gcc.target/riscv/rvv/vsetvl/imm_conflict-1.c: Diito.
* gcc.target/riscv/rvv/vsetvl/imm_conflict-2.c: Diito.
* gcc.target/riscv/rvv/vsetvl/imm_conflict-3.c: Diito.
* gcc.target/riscv/rvv/vsetvl/imm_conflict-4.c: Diito.
* gcc.target/riscv/rvv/vsetvl/imm_conflict-5.c: Diito.
* gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-1.c: Diito.
* gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-10.c: Diito.
* gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-11.c: Diito.
* gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-12.c: Diito.
* gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-13.c: Diito.
* gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-14.c: Diito.
* gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-15.c: Diito.
* gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-16.c: Diito.
* gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-17.c: Diito.
* gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-2.c: Diito.
* gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-3.c: Diito.
* gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-4.c: Diito.
* gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-5.c: Diito.
* gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-6.c: Diito.
* gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-7.c: Diito.
* gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-8.c: Diito.
* gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-9.c: Diito.
* gcc.target/riscv/rvv/vsetvl/imm_switch-1.c: Diito.
* gcc.target/riscv/rvv/vsetvl/imm_switch-2.c: Diito.
* gcc.target/riscv/rvv/vsetvl/imm_switch-3.c: Diito.
* gcc.target/riscv/rvv/vsetvl/imm_switch-4.c: Diito.
* gcc.target/riscv/rvv/vsetvl/imm_switch-5.c: Diito.
* gcc.target/riscv/rvv/vsetvl/imm_switch-6.c: Diito.
* gcc.target/riscv/rvv/vsetvl/imm_switch-7.c: Diito.
* gcc.target/riscv/rvv/vsetvl/imm_switch-8.c: Diito.
* gcc.target/riscv/rvv/vsetvl/imm_switch-9.c: Diito.
* gcc.target/riscv/rvv/vsetvl/pr108270.c: Diito.
* gcc.target/riscv/rvv/vsetvl/pr109399.c: Diito.
* gcc.target/riscv/rvv/vsetvl/pr109547.c: Diito.
* gcc.target/riscv/rvv/vsetvl/pr109615.c: Diito.
* gcc.target/riscv/rvv/vsetvl/pr109743-1.c: Diito.
* gcc.target/riscv/rvv/vsetvl/pr109743-2.c: Diito.
* gcc.target/riscv/rvv/vsetvl/pr109743-3.c: Diito.
* gcc.target/riscv/rvv/vsetvl/pr109743-4.c: Diito.
* gcc.target/riscv/rvv/vsetvl/pr109748.c: Diito.
* gcc.target/riscv/rvv/vsetvl/pr109773-1.c: Diito.
* gcc.target/riscv/rvv/vsetvl/pr109773-2.c: Diito.
* gcc.target/riscv/rvv/vsetvl/pr109974.c: Diito.
* gcc.target/riscv/rvv/vsetvl/pr111037-1.c: Diito.
* gcc.target/riscv/rvv/vsetvl/pr111037-2.c: Diito.
* gcc.target/riscv/rvv/vsetvl/pr111037-3.c: Diito.
* gcc.target/riscv/rvv/vsetvl/pr111037-4.c: Diito.
* gcc.target/riscv/rvv/vsetvl/pr111234.c: Diito.
* gcc.target/riscv/rvv/vsetvl/pr111255.c: Diito.
* gcc.target/riscv/rvv/vsetvl/pr111927.c: Diito.
* gcc.target/riscv/rvv/vsetvl/pr111947.c: Diito.
* gcc.target/riscv/rvv/vsetvl/pr112092-1.c: Diito.
* gcc.target/riscv/rvv/vsetvl/pr112092-2.c: Diito.
* gcc.target/riscv/rvv/vsetvl/pr112713-1.c: Diito.
* gcc.target/riscv/rvv/vsetvl/pr112713-2.c: Diito.
* gcc.target/riscv/rvv/vsetvl/pr112776.c: Diito.
* gcc.target/riscv/rvv/vsetvl/pr112813-1.c: Diito.
* gcc.target/riscv/rvv/vsetvl/pr112929-1.c: Diito.
* gcc.target/riscv/rvv/vsetvl/pr112988-1.c: Diito.
* gcc.target/riscv/rvv/vsetvl/pr113248.c: Diito.
* gcc.target/riscv/rvv/vsetvl/pr113696.c: Diito.
* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-1.c: Diito.
* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-10.c: Diito.
* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-11.c: Diito.
* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-12.c: Diito.
* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-13.c: Diito.
* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-14.c: Diito.
* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-15.c: Diito.
* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-16.c: Diito.
* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-17.c: Diito.
* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-18.c: Diito.
* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-19.c: Diito.
* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-2.c: Diito.
* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-20.c: Diito.
* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-21.c: Diito.
* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-22.c: Diito.
* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-23.c: Diito.
* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-24.c: Diito.
* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-25.c: Diito.
* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-26.c: Diito.
* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-27.c: Diito.
* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-28.c: Diito.
* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-29.c: Diito.
* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-3.c: Diito.
* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-30.c: Diito.
* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-31.c: Diito.
* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-32.c: Diito.
* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-33.c: Diito.
* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-34.c: Diito.
* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-35.c: Diito.
* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-36.c: Diito.
* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-37.c: Diito.
* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-38.c: Diito.
* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-39.c: Diito.
* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-4.c: Diito.
* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-40.c: Diito.
* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-41.c: Diito.
* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-42.c: Diito.
* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-43.c: Diito.
* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-44.c: Diito.
* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-45.c: Diito.
* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-46.c: Diito.
* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-5.c: Diito.
* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-6.c: Diito.
* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-7.c: Diito.
* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-8.c: Diito.
* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-9.c: Diito.
* gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-1.c: Diito.
* gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-10.c: Diito.
* gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-11.c: Diito.
* gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-12.c: Diito.
* gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-13.c: Diito.
* gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-14.c: Diito.
* gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-15.c: Diito.
* gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-16.c: Diito.
* gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-17.c: Diito.
* gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-18.c: Diito.
* gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-19.c: Diito.
* gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-2.c: Diito.
* gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-20.c: Diito.
* gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-21.c: Diito.
* gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-22.c: Diito.
* gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-23.c: Diito.
* gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-24.c: Diito.
* gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-25.c: Diito.
* gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-26.c: Diito.
* gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-27.c: Diito.
* gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-28.c: Diito.
* gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-3.c: Diito.
* gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-4.c: Diito.
* gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-5.c: Diito.
* gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-6.c: Diito.
* gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-7.c: Diito.
* gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-8.c: Diito.
* gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-9.c: Diito.
* gcc.target/riscv/rvv/vsetvl/vlmax_call-1.c: Diito.
* gcc.target/riscv/rvv/vsetvl/vlmax_call-2.c: Diito.
* gcc.target/riscv/rvv/vsetvl/vlmax_call-3.c: Diito.
* gcc.target/riscv/rvv/vsetvl/vlmax_call-4.c: Diito.
* gcc.target/riscv/rvv/vsetvl/vlmax_complex_loop-1.c: Diito.
* gcc.target/riscv/rvv/vsetvl/vlmax_complex_loop-2.c: Diito.
* gcc.target/riscv/rvv/vsetvl/vlmax_conflict-1.c: Diito.
* gcc.target/riscv/rvv/vsetvl/vlmax_conflict-10.c: Diito.
* gcc.target/riscv/rvv/vsetvl/vlmax_conflict-11.c: Diito.
* gcc.target/riscv/rvv/vsetvl/vlmax_conflict-12.c: Diito.
* gcc.target/riscv/rvv/vsetvl/vlmax_conflict-13.c: Diito.
* gcc.target/riscv/rvv/vsetvl/vlmax_conflict-2.c: Diito.
* gcc.target/riscv/rvv/vsetvl/vlmax_conflict-3.c: Diito.
* gcc.target/riscv/rvv/vsetvl/vlmax_conflict-4.c: Diito.
* gcc.target/riscv/rvv/vsetvl/vlmax_conflict-5.c: Diito.
* gcc.target/riscv/rvv/vsetvl/vlmax_conflict-6.c: Diito.
* gcc.target/riscv/rvv/vsetvl/vlmax_conflict-7.c: Diito.
* gcc.target/riscv/rvv/vsetvl/vlmax_conflict-8.c: Diito.
* gcc.target/riscv/rvv/vsetvl/vlmax_conflict-9.c: Diito.
* gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-1.c: Diito.
* gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-10.c: Diito.
* gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-11.c: Diito.
* gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-12.c: Diito.
* gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-13.c: Diito.
* gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-14.c: Diito.
* gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-15.c: Diito.
* gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-16.c: Diito.
* gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-17.c: Diito.
* gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-18.c: Diito.
* gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-19.c: Diito.
* gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-2.c: Diito.
* gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-20.c: Diito.
* gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-21.c: Diito.
* gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-22.c: Diito.
* gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-23.c: Diito.
* gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-24.c: Diito.
* gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-25.c: Diito.
* gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-26.c: Diito.
* gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-27.c: Diito.
* gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-28.c: Diito.
* gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-3.c: Diito.
* gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-4.c: Diito.
* gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-5.c: Diito.
* gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-6.c: Diito.
* gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-7.c: Diito.
* gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-8.c: Diito.
* gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-9.c: Diito.
* gcc.target/riscv/rvv/vsetvl/vlmax_phi-1.c: Diito.
* gcc.target/riscv/rvv/vsetvl/vlmax_phi-10.c: Diito.
* gcc.target/riscv/rvv/vsetvl/vlmax_phi-11.c: Diito.
* gcc.target/riscv/rvv/vsetvl/vlmax_phi-12.c: Diito.
* gcc.target/riscv/rvv/vsetvl/vlmax_phi-13.c: Diito.
* gcc.target/riscv/rvv/vsetvl/vlmax_phi-14.c: Diito.
* gcc.target/riscv/rvv/vsetvl/vlmax_phi-15.c: Diito.
* gcc.target/riscv/rvv/vsetvl/vlmax_phi-16.c: Diito.
* gcc.target/riscv/rvv/vsetvl/vlmax_phi-17.c: Diito.
* gcc.target/riscv/rvv/vsetvl/vlmax_phi-18.c: Diito.
* gcc.target/riscv/rvv/vsetvl/vlmax_phi-19.c: Diito.
* gcc.target/riscv/rvv/vsetvl/vlmax_phi-2.c: Diito.
* gcc.target/riscv/rvv/vsetvl/vlmax_phi-20.c: Diito.
* gcc.target/riscv/rvv/vsetvl/vlmax_phi-21.c: Diito.
* gcc.target/riscv/rvv/vsetvl/vlmax_phi-22.c: Diito.
* gcc.target/riscv/rvv/vsetvl/vlmax_phi-23.c: Diito.
* gcc.target/riscv/rvv/vsetvl/vlmax_phi-24.c: Diito.
* gcc.target/riscv/rvv/vsetvl/vlmax_phi-25.c: Diito.
* gcc.target/riscv/rvv/vsetvl/vlmax_phi-26.c: Diito.
* gcc.target/riscv/rvv/vsetvl/vlmax_phi-27.c: Diito.
* gcc.target/riscv/rvv/vsetvl/vlmax_phi-28.c: Diito.
* gcc.target/riscv/rvv/vsetvl/vlmax_phi-3.c: Diito.
* gcc.target/riscv/rvv/vsetvl/vlmax_phi-4.c: Diito.
* gcc.target/riscv/rvv/vsetvl/vlmax_phi-5.c: Diito.
* gcc.target/riscv/rvv/vsetvl/vlmax_phi-6.c: Diito.
* gcc.target/riscv/rvv/vsetvl/vlmax_phi-7.c: Diito.
* gcc.target/riscv/rvv/vsetvl/vlmax_phi-8.c: Diito.
* gcc.target/riscv/rvv/vsetvl/vlmax_phi-9.c: Diito.
* gcc.target/riscv/rvv/vsetvl/vlmax_single_block-1.c: Diito.
* gcc.target/riscv/rvv/vsetvl/vlmax_single_block-10.c: Diito.
* gcc.target/riscv/rvv/vsetvl/vlmax_single_block-11.c: Diito.
* gcc.target/riscv/rvv/vsetvl/vlmax_single_block-12.c: Diito.
* gcc.target/riscv/rvv/vsetvl/vlmax_single_block-13.c: Diito.
* gcc.target/riscv/rvv/vsetvl/vlmax_single_block-14.c: Diito.
* gcc.target/riscv/rvv/vsetvl/vlmax_single_block-15.c: Diito.
* gcc.target/riscv/rvv/vsetvl/vlmax_single_block-16.c: Diito.
* gcc.target/riscv/rvv/vsetvl/vlmax_single_block-17.c: Diito.
* gcc.target/riscv/rvv/vsetvl/vlmax_single_block-18.c: Diito.
* gcc.target/riscv/rvv/vsetvl/vlmax_single_block-19.c: Diito.
* gcc.target/riscv/rvv/vsetvl/vlmax_single_block-2.c: Diito.
* gcc.target/riscv/rvv/vsetvl/vlmax_single_block-3.c: Diito.
* gcc.target/riscv/rvv/vsetvl/vlmax_single_block-4.c: Diito.
* gcc.target/riscv/rvv/vsetvl/vlmax_single_block-5.c: Diito.
* gcc.target/riscv/rvv/vsetvl/vlmax_single_block-6.c: Diito.
* gcc.target/riscv/rvv/vsetvl/vlmax_single_block-7.c: Diito.
* gcc.target/riscv/rvv/vsetvl/vlmax_single_block-8.c: Diito.
* gcc.target/riscv/rvv/vsetvl/vlmax_single_block-9.c: Diito.
* gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-1.c: Diito.
* gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-2.c: Diito.
* gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-3.c: Diito.
* gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-4.c: Diito.
* gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-5.c: Diito.
* gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-6.c: Diito.
* gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-7.c: Diito.
* gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-8.c: Diito.
* gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-1.c: Diito.
* gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-10.c: Diito.
* gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-11.c: Diito.
* gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-12.c: Diito.
* gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-13.c: Diito.
* gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-14.c: Diito.
* gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-15.c: Diito.
* gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-16.c: Diito.
* gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-2.c: Diito.
* gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-3.c: Diito.
* gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-4.c: Diito.
* gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-5.c: Diito.
* gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-6.c: Diito.
* gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-7.c: Diito.
* gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-8.c: Diito.
* gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-9.c: Diito.
* gcc.target/riscv/rvv/vsetvl/vsetvl-1.c: Diito.
* gcc.target/riscv/rvv/vsetvl/vsetvl-10.c: Diito.
* gcc.target/riscv/rvv/vsetvl/vsetvl-11.c: Diito.
* gcc.target/riscv/rvv/vsetvl/vsetvl-12.c: Diito.
* gcc.target/riscv/rvv/vsetvl/vsetvl-13.c: Diito.
* gcc.target/riscv/rvv/vsetvl/vsetvl-14.c: Diito.
* gcc.target/riscv/rvv/vsetvl/vsetvl-15.c: Diito.
* gcc.target/riscv/rvv/vsetvl/vsetvl-16.c: Diito.
* gcc.target/riscv/rvv/vsetvl/vsetvl-17.c: Diito.
* gcc.target/riscv/rvv/vsetvl/vsetvl-18.c: Diito.
* gcc.target/riscv/rvv/vsetvl/vsetvl-19.c: Diito.
* gcc.target/riscv/rvv/vsetvl/vsetvl-2.c: Diito.
* gcc.target/riscv/rvv/vsetvl/vsetvl-20.c: Diito.
* gcc.target/riscv/rvv/vsetvl/vsetvl-21.c: Diito.
* gcc.target/riscv/rvv/vsetvl/vsetvl-22.c: Diito.
* gcc.target/riscv/rvv/vsetvl/vsetvl-23.c: Diito.
* gcc.target/riscv/rvv/vsetvl/vsetvl-24.c: Diito.
* gcc.target/riscv/rvv/vsetvl/vsetvl-3.c: Diito.
* gcc.target/riscv/rvv/vsetvl/vsetvl-4.c: Diito.
* gcc.target/riscv/rvv/vsetvl/vsetvl-5.c: Diito.
* gcc.target/riscv/rvv/vsetvl/vsetvl-6.c: Diito.
* gcc.target/riscv/rvv/vsetvl/vsetvl-7.c: Diito.
* gcc.target/riscv/rvv/vsetvl/vsetvl-8.c: Diito.
* gcc.target/riscv/rvv/vsetvl/vsetvl-9.c: Diito.
* gcc.target/riscv/rvv/vsetvl/vsetvl_bug-1.c: Diito.
* gcc.target/riscv/rvv/vsetvl/vsetvl_bug-2.c: Diito.
* gcc.target/riscv/rvv/vsetvl/vsetvl_int.c: Diito.
* gcc.target/riscv/rvv/vsetvl/vsetvl_pre-1.c: Diito.
* gcc.target/riscv/rvv/vsetvl/vsetvlmax-1.c: Diito.
* gcc.target/riscv/rvv/vsetvl/vsetvlmax-10.c: Diito.
* gcc.target/riscv/rvv/vsetvl/vsetvlmax-11.c: Diito.
* gcc.target/riscv/rvv/vsetvl/vsetvlmax-12.c: Diito.
* gcc.target/riscv/rvv/vsetvl/vsetvlmax-13.c: Diito.
* gcc.target/riscv/rvv/vsetvl/vsetvlmax-14.c: Diito.
* gcc.target/riscv/rvv/vsetvl/vsetvlmax-15.c: Diito.
* gcc.target/riscv/rvv/vsetvl/vsetvlmax-16.c: Diito.
* gcc.target/riscv/rvv/vsetvl/vsetvlmax-17.c: Diito.
* gcc.target/riscv/rvv/vsetvl/vsetvlmax-18.c: Diito.
* gcc.target/riscv/rvv/vsetvl/vsetvlmax-19.c: Diito.
* gcc.target/riscv/rvv/vsetvl/vsetvlmax-2.c: Diito.
* gcc.target/riscv/rvv/vsetvl/vsetvlmax-20.c: Diito.
* gcc.target/riscv/rvv/vsetvl/vsetvlmax-3.c: Diito.
* gcc.target/riscv/rvv/vsetvl/vsetvlmax-4.c: Diito.
* gcc.target/riscv/rvv/vsetvl/vsetvlmax-5.c: Diito.
* gcc.target/riscv/rvv/vsetvl/vsetvlmax-6.c: Diito.
* gcc.target/riscv/rvv/vsetvl/vsetvlmax-7.c: Diito.
* gcc.target/riscv/rvv/vsetvl/vsetvlmax-8.c: Diito.
* gcc.target/riscv/rvv/vsetvl/vsetvlmax-9.c: Diito.
* gcc.target/riscv/rvv/vsetvl/wredsum_vlmax.c: Diito.
* gcc.target/riscv/rvv/base/rvv-vector-bits-1.c: New test.
* gcc.target/riscv/rvv/base/rvv-vector-bits-2.c: New test.
* gcc.target/riscv/rvv/base/rvv-vector-bits-3.c: New test.
* gcc.target/riscv/rvv/base/rvv-vector-bits-4.c: New test.
* gcc.target/riscv/rvv/base/rvv-vector-bits-5.c: New test.
* gcc.target/riscv/rvv/base/rvv-vector-bits-6.c: New test.
Signed-off-by: Pan Li <pan2.li@intel.com>
Diff:
---
gcc/config/riscv/riscv-avlprop.cc | 2 +-
gcc/config/riscv/riscv-opts.h | 15 ++++----
gcc/config/riscv/riscv-selftests.cc | 2 +-
gcc/config/riscv/riscv-v.cc | 16 ++++----
gcc/config/riscv/riscv.cc | 21 +++++++----
gcc/config/riscv/riscv.opt | 31 +++++++--------
gcc/testsuite/g++.target/riscv/rvv/base/pr111296.C | 2 +-
.../vect/costmodel/riscv/rvv/dynamic-lmul4-6.c | 2 +-
.../vect/costmodel/riscv/rvv/dynamic-lmul4-8.c | 2 +-
.../vect/costmodel/riscv/rvv/dynamic-lmul8-12.c | 2 +-
.../gcc.dg/vect/costmodel/riscv/rvv/pr113112-1.c | 2 +-
.../gcc.dg/vect/costmodel/riscv/rvv/pr113112-2.c | 2 +-
.../gcc.dg/vect/costmodel/riscv/rvv/pr113112-3.c | 2 +-
.../gcc.dg/vect/costmodel/riscv/rvv/pr113112-4.c | 2 +-
.../gcc.dg/vect/costmodel/riscv/rvv/pr113112-5.c | 2 +-
.../gcc.dg/vect/costmodel/riscv/rvv/pr113247-2.c | 2 +-
.../gcc.dg/vect/costmodel/riscv/rvv/pr113247-4.c | 2 +-
.../gcc.dg/vect/costmodel/riscv/rvv/pr113281-2.c | 2 +-
.../gcc.dg/vect/costmodel/riscv/rvv/pr113281-4.c | 2 +-
.../gcc.target/riscv/rvv/autovec/align-1.c | 2 +-
.../gcc.target/riscv/rvv/autovec/align-2.c | 2 +-
.../riscv/rvv/autovec/binop/copysign-run.c | 2 +-
.../riscv/rvv/autovec/binop/copysign-rv32gcv.c | 2 +-
.../riscv/rvv/autovec/binop/copysign-rv64gcv.c | 2 +-
.../riscv/rvv/autovec/binop/copysign-zvfh-run.c | 2 +-
.../gcc.target/riscv/rvv/autovec/binop/fmax-1.c | 2 +-
.../riscv/rvv/autovec/binop/fmax_run-1.c | 2 +-
.../riscv/rvv/autovec/binop/fmax_zvfh-1.c | 2 +-
.../riscv/rvv/autovec/binop/fmax_zvfh_run-1.c | 2 +-
.../gcc.target/riscv/rvv/autovec/binop/fmin-1.c | 2 +-
.../riscv/rvv/autovec/binop/fmin_run-1.c | 2 +-
.../riscv/rvv/autovec/binop/fmin_zvfh-1.c | 2 +-
.../riscv/rvv/autovec/binop/fmin_zvfh_run-1.c | 2 +-
.../gcc.target/riscv/rvv/autovec/binop/mulh-1.c | 2 +-
.../gcc.target/riscv/rvv/autovec/binop/mulh-2.c | 2 +-
.../riscv/rvv/autovec/binop/mulh_run-1.c | 2 +-
.../riscv/rvv/autovec/binop/mulh_run-2.c | 2 +-
.../gcc.target/riscv/rvv/autovec/binop/narrow-1.c | 2 +-
.../gcc.target/riscv/rvv/autovec/binop/narrow-2.c | 2 +-
.../gcc.target/riscv/rvv/autovec/binop/narrow-3.c | 2 +-
.../riscv/rvv/autovec/binop/narrow_run-1.c | 2 +-
.../riscv/rvv/autovec/binop/narrow_run-2.c | 2 +-
.../riscv/rvv/autovec/binop/narrow_run-3.c | 2 +-
.../riscv/rvv/autovec/binop/shift-immediate.c | 2 +-
.../gcc.target/riscv/rvv/autovec/binop/shift-run.c | 2 +-
.../riscv/rvv/autovec/binop/shift-rv32gcv.c | 2 +-
.../riscv/rvv/autovec/binop/shift-rv64gcv.c | 2 +-
.../riscv/rvv/autovec/binop/shift-scalar-run.c | 2 +-
.../riscv/rvv/autovec/binop/shift-scalar-rv32gcv.c | 2 +-
.../riscv/rvv/autovec/binop/shift-scalar-rv64gcv.c | 2 +-
.../rvv/autovec/binop/shift-scalar-template.h | 2 +-
.../riscv/rvv/autovec/binop/vadd-run-nofm.c | 2 +-
.../gcc.target/riscv/rvv/autovec/binop/vadd-run.c | 2 +-
.../riscv/rvv/autovec/binop/vadd-rv32gcv-nofm.c | 2 +-
.../riscv/rvv/autovec/binop/vadd-rv32gcv.c | 2 +-
.../riscv/rvv/autovec/binop/vadd-rv64gcv-nofm.c | 2 +-
.../riscv/rvv/autovec/binop/vadd-rv64gcv.c | 2 +-
.../riscv/rvv/autovec/binop/vadd-zvfh-run.c | 2 +-
.../gcc.target/riscv/rvv/autovec/binop/vand-run.c | 2 +-
.../riscv/rvv/autovec/binop/vand-rv32gcv.c | 2 +-
.../riscv/rvv/autovec/binop/vand-rv64gcv.c | 2 +-
.../riscv/rvv/autovec/binop/vcompress-avlprop-1.c | 2 +-
.../riscv/rvv/autovec/binop/vdiv-run-nofm.c | 2 +-
.../gcc.target/riscv/rvv/autovec/binop/vdiv-run.c | 2 +-
.../riscv/rvv/autovec/binop/vdiv-rv32gcv-nofm.c | 2 +-
.../riscv/rvv/autovec/binop/vdiv-rv32gcv.c | 2 +-
.../riscv/rvv/autovec/binop/vdiv-rv64gcv-nofm.c | 2 +-
.../riscv/rvv/autovec/binop/vdiv-rv64gcv.c | 2 +-
.../riscv/rvv/autovec/binop/vdiv-zvfh-run.c | 2 +-
.../gcc.target/riscv/rvv/autovec/binop/vmax-run.c | 2 +-
.../riscv/rvv/autovec/binop/vmax-rv32gcv.c | 2 +-
.../riscv/rvv/autovec/binop/vmax-rv64gcv.c | 2 +-
.../riscv/rvv/autovec/binop/vmax-zvfh-run.c | 2 +-
.../gcc.target/riscv/rvv/autovec/binop/vmin-run.c | 2 +-
.../riscv/rvv/autovec/binop/vmin-rv32gcv.c | 2 +-
.../riscv/rvv/autovec/binop/vmin-rv64gcv.c | 2 +-
.../riscv/rvv/autovec/binop/vmin-zvfh-run.c | 2 +-
.../riscv/rvv/autovec/binop/vmul-run-nofm.c | 2 +-
.../gcc.target/riscv/rvv/autovec/binop/vmul-run.c | 2 +-
.../riscv/rvv/autovec/binop/vmul-rv32gcv-nofm.c | 2 +-
.../riscv/rvv/autovec/binop/vmul-rv32gcv.c | 2 +-
.../riscv/rvv/autovec/binop/vmul-rv64gcv-nofm.c | 2 +-
.../riscv/rvv/autovec/binop/vmul-rv64gcv.c | 2 +-
.../riscv/rvv/autovec/binop/vmul-zvfh-run.c | 2 +-
.../gcc.target/riscv/rvv/autovec/binop/vor-run.c | 2 +-
.../riscv/rvv/autovec/binop/vor-rv32gcv.c | 2 +-
.../riscv/rvv/autovec/binop/vor-rv64gcv.c | 2 +-
.../gcc.target/riscv/rvv/autovec/binop/vrem-run.c | 2 +-
.../riscv/rvv/autovec/binop/vrem-rv32gcv.c | 2 +-
.../riscv/rvv/autovec/binop/vrem-rv64gcv.c | 2 +-
.../riscv/rvv/autovec/binop/vsub-run-nofm.c | 2 +-
.../gcc.target/riscv/rvv/autovec/binop/vsub-run.c | 2 +-
.../riscv/rvv/autovec/binop/vsub-rv32gcv-nofm.c | 2 +-
.../riscv/rvv/autovec/binop/vsub-rv32gcv.c | 2 +-
.../riscv/rvv/autovec/binop/vsub-rv64gcv-nofm.c | 2 +-
.../riscv/rvv/autovec/binop/vsub-rv64gcv.c | 2 +-
.../riscv/rvv/autovec/binop/vsub-zvfh-run.c | 2 +-
.../gcc.target/riscv/rvv/autovec/binop/vxor-run.c | 2 +-
.../riscv/rvv/autovec/binop/vxor-rv32gcv.c | 2 +-
.../riscv/rvv/autovec/binop/vxor-rv64gcv.c | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-1.c | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-2.c | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-3.c | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-4.c | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-5.c | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-6.c | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-8.c | 2 +-
.../gcc.target/riscv/rvv/autovec/cmp/vcond-1.c | 2 +-
.../gcc.target/riscv/rvv/autovec/cmp/vcond-2.c | 2 +-
.../gcc.target/riscv/rvv/autovec/cmp/vcond-3.c | 2 +-
.../gcc.target/riscv/rvv/autovec/cmp/vcond-4.c | 2 +-
.../gcc.target/riscv/rvv/autovec/cmp/vcond_run-1.c | 2 +-
.../gcc.target/riscv/rvv/autovec/cmp/vcond_run-2.c | 2 +-
.../gcc.target/riscv/rvv/autovec/cmp/vcond_run-3.c | 2 +-
.../gcc.target/riscv/rvv/autovec/cmp/vcond_run-4.c | 2 +-
.../riscv/rvv/autovec/cond/cond_arith-1.c | 2 +-
.../riscv/rvv/autovec/cond/cond_arith-10.c | 2 +-
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.../riscv/rvv/autovec/unop/vfsqrt-rv32gcv.c | 2 +-
.../riscv/rvv/autovec/unop/vfsqrt-rv64gcv.c | 2 +-
.../riscv/rvv/autovec/unop/vfsqrt-zvfh-run.c | 2 +-
.../gcc.target/riscv/rvv/autovec/unop/vneg-run.c | 2 +-
.../riscv/rvv/autovec/unop/vneg-rv32gcv.c | 2 +-
.../riscv/rvv/autovec/unop/vneg-rv64gcv.c | 2 +-
.../riscv/rvv/autovec/unop/vneg-zvfh-run.c | 2 +-
.../gcc.target/riscv/rvv/autovec/unop/vnot-run.c | 2 +-
.../riscv/rvv/autovec/unop/vnot-rv32gcv.c | 2 +-
.../riscv/rvv/autovec/unop/vnot-rv64gcv.c | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/autovec/v-1.c | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/autovec/v-2.c | 2 +-
.../riscv/rvv/autovec/vls-vlmax/bitmask-1.c | 2 +-
.../riscv/rvv/autovec/vls-vlmax/bitmask-10.c | 2 +-
.../riscv/rvv/autovec/vls-vlmax/bitmask-11.c | 2 +-
.../riscv/rvv/autovec/vls-vlmax/bitmask-12.c | 2 +-
.../riscv/rvv/autovec/vls-vlmax/bitmask-13.c | 2 +-
.../riscv/rvv/autovec/vls-vlmax/bitmask-14.c | 2 +-
.../riscv/rvv/autovec/vls-vlmax/bitmask-2.c | 2 +-
.../riscv/rvv/autovec/vls-vlmax/bitmask-3.c | 2 +-
.../riscv/rvv/autovec/vls-vlmax/bitmask-4.c | 2 +-
.../riscv/rvv/autovec/vls-vlmax/bitmask-5.c | 2 +-
.../riscv/rvv/autovec/vls-vlmax/bitmask-6.c | 2 +-
.../riscv/rvv/autovec/vls-vlmax/bitmask-7.c | 2 +-
.../riscv/rvv/autovec/vls-vlmax/bitmask-8.c | 2 +-
.../riscv/rvv/autovec/vls-vlmax/bitmask-9.c | 2 +-
.../riscv/rvv/autovec/vls-vlmax/combine-1.c | 2 +-
.../rvv/autovec/vls-vlmax/combine-merge_run-1.c | 2 +-
.../rvv/autovec/vls-vlmax/combine-merge_run-2.c | 2 +-
.../riscv/rvv/autovec/vls-vlmax/compress-1.c | 2 +-
.../riscv/rvv/autovec/vls-vlmax/compress-2.c | 2 +-
.../riscv/rvv/autovec/vls-vlmax/compress-3.c | 2 +-
.../riscv/rvv/autovec/vls-vlmax/compress-4.c | 2 +-
.../riscv/rvv/autovec/vls-vlmax/compress-5.c | 2 +-
.../riscv/rvv/autovec/vls-vlmax/compress-6.c | 2 +-
.../riscv/rvv/autovec/vls-vlmax/compress_run-1.c | 2 +-
.../riscv/rvv/autovec/vls-vlmax/compress_run-2.c | 2 +-
.../riscv/rvv/autovec/vls-vlmax/compress_run-3.c | 2 +-
.../riscv/rvv/autovec/vls-vlmax/compress_run-4.c | 2 +-
.../riscv/rvv/autovec/vls-vlmax/compress_run-5.c | 2 +-
.../riscv/rvv/autovec/vls-vlmax/compress_run-6.c | 2 +-
.../riscv/rvv/autovec/vls-vlmax/consecutive-1.c | 2 +-
.../riscv/rvv/autovec/vls-vlmax/consecutive-2.c | 2 +-
.../rvv/autovec/vls-vlmax/consecutive_run-1.c | 2 +-
.../rvv/autovec/vls-vlmax/consecutive_run-2.c | 2 +-
.../riscv/rvv/autovec/vls-vlmax/full-vec-move1.c | 2 +-
.../autovec/vls-vlmax/init-repeat-sequence-run-1.c | 2 +-
.../autovec/vls-vlmax/init-repeat-sequence-run-2.c | 2 +-
.../autovec/vls-vlmax/init-repeat-sequence-run-3.c | 2 +-
.../riscv/rvv/autovec/vls-vlmax/insert_run-1.c | 2 +-
.../riscv/rvv/autovec/vls-vlmax/insert_run-2.c | 2 +-
.../riscv/rvv/autovec/vls-vlmax/merge-1.c | 2 +-
.../riscv/rvv/autovec/vls-vlmax/merge-2.c | 2 +-
.../riscv/rvv/autovec/vls-vlmax/merge-3.c | 2 +-
.../riscv/rvv/autovec/vls-vlmax/merge-4.c | 2 +-
.../riscv/rvv/autovec/vls-vlmax/merge-5.c | 2 +-
.../riscv/rvv/autovec/vls-vlmax/merge-6.c | 2 +-
.../riscv/rvv/autovec/vls-vlmax/merge-7.c | 2 +-
.../riscv/rvv/autovec/vls-vlmax/merge_run-1.c | 2 +-
.../riscv/rvv/autovec/vls-vlmax/merge_run-2.c | 2 +-
.../riscv/rvv/autovec/vls-vlmax/merge_run-3.c | 2 +-
.../riscv/rvv/autovec/vls-vlmax/merge_run-4.c | 2 +-
.../riscv/rvv/autovec/vls-vlmax/merge_run-5.c | 2 +-
.../riscv/rvv/autovec/vls-vlmax/merge_run-6.c | 2 +-
.../riscv/rvv/autovec/vls-vlmax/merge_run-7.c | 2 +-
.../riscv/rvv/autovec/vls-vlmax/perm_run-1.c | 2 +-
.../riscv/rvv/autovec/vls-vlmax/perm_run-2.c | 2 +-
.../riscv/rvv/autovec/vls-vlmax/perm_run-3.c | 2 +-
.../riscv/rvv/autovec/vls-vlmax/perm_run-4.c | 2 +-
.../riscv/rvv/autovec/vls-vlmax/perm_run-5.c | 2 +-
.../riscv/rvv/autovec/vls-vlmax/perm_run-6.c | 2 +-
.../riscv/rvv/autovec/vls-vlmax/perm_run-7.c | 2 +-
.../riscv/rvv/autovec/vls-vlmax/pr110985.c | 2 +-
.../riscv/rvv/autovec/vls-vlmax/repeat_run-1.c | 2 +-
.../riscv/rvv/autovec/vls-vlmax/repeat_run-2.c | 2 +-
.../riscv/rvv/autovec/vls-vlmax/repeat_run-3.c | 2 +-
.../riscv/rvv/autovec/vls-vlmax/repeat_run-4.c | 2 +-
.../riscv/rvv/autovec/vls-vlmax/repeat_run-5.c | 2 +-
.../riscv/rvv/autovec/vls-vlmax/repeat_run-6.c | 2 +-
.../riscv/rvv/autovec/vls-vlmax/trailing-1.c | 2 +-
.../riscv/rvv/autovec/vls-vlmax/trailing-2.c | 2 +-
.../riscv/rvv/autovec/vls-vlmax/trailing_run-1.c | 2 +-
.../riscv/rvv/autovec/vls-vlmax/trailing_run-2.c | 2 +-
.../riscv/rvv/autovec/vls/calling-convention-1.c | 2 +-
.../riscv/rvv/autovec/vls/calling-convention-10.c | 2 +-
.../riscv/rvv/autovec/vls/calling-convention-2.c | 2 +-
.../riscv/rvv/autovec/vls/calling-convention-3.c | 2 +-
.../riscv/rvv/autovec/vls/calling-convention-4.c | 2 +-
.../riscv/rvv/autovec/vls/calling-convention-5.c | 2 +-
.../riscv/rvv/autovec/vls/calling-convention-6.c | 2 +-
.../riscv/rvv/autovec/vls/calling-convention-7.c | 2 +-
.../riscv/rvv/autovec/vls/calling-convention-8.c | 2 +-
.../riscv/rvv/autovec/vls/calling-convention-9.c | 2 +-
.../rvv/autovec/vls/calling-convention-run-1.c | 2 +-
.../rvv/autovec/vls/calling-convention-run-2.c | 2 +-
.../rvv/autovec/vls/calling-convention-run-3.c | 2 +-
.../rvv/autovec/vls/calling-convention-run-4.c | 2 +-
.../rvv/autovec/vls/calling-convention-run-5.c | 2 +-
.../rvv/autovec/vls/calling-convention-run-6.c | 2 +-
.../gcc.target/riscv/rvv/autovec/vls/pr110994.c | 2 +-
.../riscv/rvv/autovec/vmv-imm-fixed-rv32.c | 2 +-
.../riscv/rvv/autovec/vmv-imm-fixed-rv64.c | 2 +-
.../gcc.target/riscv/rvv/autovec/vmv-imm-run.c | 2 +-
.../gcc.target/riscv/rvv/autovec/vmv-imm-rv32.c | 2 +-
.../gcc.target/riscv/rvv/autovec/vmv-imm-rv64.c | 2 +-
.../riscv/rvv/autovec/vreinterpet-fixed.c | 2 +-
.../riscv/rvv/autovec/widen/vec-avg-run.c | 2 +-
.../riscv/rvv/autovec/widen/vec-avg-rv32gcv.c | 2 +-
.../riscv/rvv/autovec/widen/vec-avg-rv64gcv.c | 2 +-
.../gcc.target/riscv/rvv/autovec/widen/widen-1.c | 2 +-
.../gcc.target/riscv/rvv/autovec/widen/widen-10.c | 2 +-
.../gcc.target/riscv/rvv/autovec/widen/widen-11.c | 2 +-
.../gcc.target/riscv/rvv/autovec/widen/widen-12.c | 2 +-
.../gcc.target/riscv/rvv/autovec/widen/widen-2.c | 2 +-
.../gcc.target/riscv/rvv/autovec/widen/widen-3.c | 2 +-
.../gcc.target/riscv/rvv/autovec/widen/widen-4.c | 2 +-
.../gcc.target/riscv/rvv/autovec/widen/widen-5.c | 2 +-
.../gcc.target/riscv/rvv/autovec/widen/widen-6.c | 2 +-
.../gcc.target/riscv/rvv/autovec/widen/widen-7.c | 2 +-
.../gcc.target/riscv/rvv/autovec/widen/widen-8.c | 2 +-
.../gcc.target/riscv/rvv/autovec/widen/widen-9.c | 2 +-
.../riscv/rvv/autovec/widen/widen-complicate-1.c | 2 +-
.../riscv/rvv/autovec/widen/widen-complicate-2.c | 2 +-
.../riscv/rvv/autovec/widen/widen-complicate-3.c | 2 +-
.../riscv/rvv/autovec/widen/widen-complicate-4.c | 2 +-
.../riscv/rvv/autovec/widen/widen-complicate-5.c | 2 +-
.../riscv/rvv/autovec/widen/widen-complicate-6.c | 2 +-
.../riscv/rvv/autovec/widen/widen-complicate-7.c | 2 +-
.../riscv/rvv/autovec/widen/widen-complicate-8.c | 2 +-
.../riscv/rvv/autovec/widen/widen-complicate-9.c | 2 +-
.../riscv/rvv/autovec/widen/widen_reduc-1.c | 2 +-
.../riscv/rvv/autovec/widen/widen_reduc_order-1.c | 2 +-
.../riscv/rvv/autovec/widen/widen_reduc_order-2.c | 2 +-
.../rvv/autovec/widen/widen_reduc_order_run-1.c | 2 +-
.../rvv/autovec/widen/widen_reduc_order_run-2.c | 2 +-
.../riscv/rvv/autovec/widen/widen_reduc_run-1.c | 2 +-
.../riscv/rvv/autovec/widen/widen_run-1.c | 2 +-
.../riscv/rvv/autovec/widen/widen_run-10.c | 2 +-
.../riscv/rvv/autovec/widen/widen_run-11.c | 2 +-
.../riscv/rvv/autovec/widen/widen_run-12.c | 2 +-
.../riscv/rvv/autovec/widen/widen_run-2.c | 2 +-
.../riscv/rvv/autovec/widen/widen_run-3.c | 2 +-
.../riscv/rvv/autovec/widen/widen_run-4.c | 2 +-
.../riscv/rvv/autovec/widen/widen_run-5.c | 2 +-
.../riscv/rvv/autovec/widen/widen_run-6.c | 2 +-
.../riscv/rvv/autovec/widen/widen_run-7.c | 2 +-
.../riscv/rvv/autovec/widen/widen_run-8.c | 2 +-
.../riscv/rvv/autovec/widen/widen_run-9.c | 2 +-
.../riscv/rvv/autovec/widen/widen_run_zvfh-1.c | 2 +-
.../riscv/rvv/autovec/widen/widen_run_zvfh-10.c | 2 +-
.../riscv/rvv/autovec/widen/widen_run_zvfh-11.c | 2 +-
.../riscv/rvv/autovec/widen/widen_run_zvfh-12.c | 2 +-
.../riscv/rvv/autovec/widen/widen_run_zvfh-2.c | 2 +-
.../riscv/rvv/autovec/widen/widen_run_zvfh-3.c | 2 +-
.../riscv/rvv/autovec/widen/widen_run_zvfh-5.c | 2 +-
.../riscv/rvv/autovec/widen/widen_run_zvfh-6.c | 2 +-
.../riscv/rvv/autovec/widen/widen_run_zvfh-7.c | 2 +-
.../riscv/rvv/autovec/widen/widen_run_zvfh-8.c | 2 +-
.../gcc.target/riscv/rvv/autovec/zve32f-1.c | 2 +-
.../gcc.target/riscv/rvv/autovec/zve32f-2.c | 2 +-
.../gcc.target/riscv/rvv/autovec/zve32f-3.c | 2 +-
.../riscv/rvv/autovec/zve32f_zvl1024b-1.c | 2 +-
.../riscv/rvv/autovec/zve32f_zvl128b-1.c | 2 +-
.../riscv/rvv/autovec/zve32f_zvl128b-2.c | 2 +-
.../riscv/rvv/autovec/zve32f_zvl2048b-1.c | 2 +-
.../riscv/rvv/autovec/zve32f_zvl256b-1.c | 2 +-
.../riscv/rvv/autovec/zve32f_zvl4096b-1.c | 2 +-
.../riscv/rvv/autovec/zve32f_zvl512b-1.c | 2 +-
.../gcc.target/riscv/rvv/autovec/zve32x-1.c | 2 +-
.../gcc.target/riscv/rvv/autovec/zve32x-2.c | 2 +-
.../gcc.target/riscv/rvv/autovec/zve32x-3.c | 2 +-
.../riscv/rvv/autovec/zve32x_zvl1024b-1.c | 2 +-
.../riscv/rvv/autovec/zve32x_zvl128b-1.c | 2 +-
.../riscv/rvv/autovec/zve32x_zvl128b-2.c | 2 +-
.../riscv/rvv/autovec/zve32x_zvl2048b-1.c | 2 +-
.../riscv/rvv/autovec/zve32x_zvl256b-1.c | 2 +-
.../riscv/rvv/autovec/zve32x_zvl4096b-1.c | 2 +-
.../riscv/rvv/autovec/zve32x_zvl512b-1.c | 2 +-
.../gcc.target/riscv/rvv/autovec/zve64d-1.c | 2 +-
.../gcc.target/riscv/rvv/autovec/zve64d-2.c | 2 +-
.../gcc.target/riscv/rvv/autovec/zve64d-3.c | 2 +-
.../riscv/rvv/autovec/zve64d_zvl1024b-1.c | 2 +-
.../riscv/rvv/autovec/zve64d_zvl128b-1.c | 2 +-
.../riscv/rvv/autovec/zve64d_zvl128b-2.c | 2 +-
.../riscv/rvv/autovec/zve64d_zvl2048b-1.c | 2 +-
.../riscv/rvv/autovec/zve64d_zvl256b-1.c | 2 +-
.../riscv/rvv/autovec/zve64d_zvl4096b-1.c | 2 +-
.../riscv/rvv/autovec/zve64d_zvl512b-1.c | 2 +-
.../gcc.target/riscv/rvv/autovec/zve64f-1.c | 2 +-
.../gcc.target/riscv/rvv/autovec/zve64f-2.c | 2 +-
.../gcc.target/riscv/rvv/autovec/zve64f-3.c | 2 +-
.../riscv/rvv/autovec/zve64f_zvl1024b-1.c | 2 +-
.../riscv/rvv/autovec/zve64f_zvl128b-1.c | 2 +-
.../riscv/rvv/autovec/zve64f_zvl128b-2.c | 2 +-
.../riscv/rvv/autovec/zve64f_zvl2048b-1.c | 2 +-
.../riscv/rvv/autovec/zve64f_zvl256b-1.c | 2 +-
.../riscv/rvv/autovec/zve64f_zvl4096b-1.c | 2 +-
.../riscv/rvv/autovec/zve64f_zvl512b-1.c | 2 +-
.../gcc.target/riscv/rvv/autovec/zve64x-1.c | 2 +-
.../gcc.target/riscv/rvv/autovec/zve64x-2.c | 2 +-
.../gcc.target/riscv/rvv/autovec/zve64x-3.c | 2 +-
.../riscv/rvv/autovec/zve64x_zvl1024b-1.c | 2 +-
.../riscv/rvv/autovec/zve64x_zvl128b-1.c | 2 +-
.../riscv/rvv/autovec/zve64x_zvl128b-2.c | 2 +-
.../riscv/rvv/autovec/zve64x_zvl2048b-1.c | 2 +-
.../riscv/rvv/autovec/zve64x_zvl256b-1.c | 2 +-
.../riscv/rvv/autovec/zve64x_zvl4096b-1.c | 2 +-
.../riscv/rvv/autovec/zve64x_zvl512b-1.c | 2 +-
.../gcc.target/riscv/rvv/autovec/zvfhmin-1.c | 2 +-
.../riscv/rvv/base/abi-callee-saved-1-fixed-1.c | 2 +-
.../riscv/rvv/base/abi-callee-saved-1-fixed-2.c | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-1.c | 10 ++---
gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-2.c | 12 +++---
.../gcc.target/riscv/rvv/base/cpymem-strategy-3.c | 4 +-
.../gcc.target/riscv/rvv/base/cpymem-strategy-4.c | 4 +-
.../riscv/rvv/base/float-point-dynamic-frm-77.c | 2 +-
.../riscv/rvv/base/float-point-frm-autovec-1.c | 2 +-
.../riscv/rvv/base/float-point-frm-autovec-2.c | 2 +-
.../riscv/rvv/base/float-point-frm-autovec-3.c | 2 +-
.../riscv/rvv/base/float-point-frm-autovec-4.c | 2 +-
.../gcc.target/riscv/rvv/base/poly-selftest-1.c | 2 +-
.../gcc.target/riscv/rvv/base/pr110119-1.c | 2 +-
.../gcc.target/riscv/rvv/base/pr110119-2.c | 2 +-
.../gcc.target/riscv/rvv/base/pr111720-0.c | 2 +-
.../gcc.target/riscv/rvv/base/pr111720-1.c | 2 +-
.../gcc.target/riscv/rvv/base/pr111720-10.c | 2 +-
.../gcc.target/riscv/rvv/base/pr111720-2.c | 2 +-
.../gcc.target/riscv/rvv/base/pr111720-3.c | 2 +-
.../gcc.target/riscv/rvv/base/pr111720-4.c | 2 +-
.../gcc.target/riscv/rvv/base/pr111720-5.c | 2 +-
.../gcc.target/riscv/rvv/base/pr111720-6.c | 2 +-
.../gcc.target/riscv/rvv/base/pr111720-7.c | 2 +-
.../gcc.target/riscv/rvv/base/pr111720-8.c | 2 +-
.../gcc.target/riscv/rvv/base/pr111720-9.c | 2 +-
.../gcc.target/riscv/rvv/base/rvv-vector-bits-1.c | 7 ++++
.../gcc.target/riscv/rvv/base/rvv-vector-bits-2.c | 7 ++++
.../gcc.target/riscv/rvv/base/rvv-vector-bits-3.c | 9 +++++
.../gcc.target/riscv/rvv/base/rvv-vector-bits-4.c | 9 +++++
.../gcc.target/riscv/rvv/base/rvv-vector-bits-5.c | 17 +++++++++
.../gcc.target/riscv/rvv/base/rvv-vector-bits-6.c | 17 +++++++++
gcc/testsuite/gcc.target/riscv/rvv/base/vf_avl-1.c | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/base/vf_avl-2.c | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/base/vf_avl-3.c | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/base/vf_avl-4.c | 2 +-
.../riscv/rvv/base/zvl-unimplemented-1.c | 2 +-
.../riscv/rvv/base/zvl-unimplemented-2.c | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/rvv.exp | 44 +++++++++++-----------
.../gcc.target/riscv/rvv/vsetvl/avl_multiple-1.c | 2 +-
.../gcc.target/riscv/rvv/vsetvl/avl_multiple-10.c | 2 +-
.../gcc.target/riscv/rvv/vsetvl/avl_multiple-11.c | 2 +-
.../gcc.target/riscv/rvv/vsetvl/avl_multiple-12.c | 2 +-
.../gcc.target/riscv/rvv/vsetvl/avl_multiple-13.c | 2 +-
.../gcc.target/riscv/rvv/vsetvl/avl_multiple-14.c | 2 +-
.../gcc.target/riscv/rvv/vsetvl/avl_multiple-15.c | 2 +-
.../gcc.target/riscv/rvv/vsetvl/avl_multiple-16.c | 2 +-
.../gcc.target/riscv/rvv/vsetvl/avl_multiple-2.c | 2 +-
.../gcc.target/riscv/rvv/vsetvl/avl_multiple-3.c | 2 +-
.../gcc.target/riscv/rvv/vsetvl/avl_multiple-4.c | 2 +-
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.../gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-5.c | 2 +-
.../gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-6.c | 2 +-
.../gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-7.c | 2 +-
.../gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-8.c | 2 +-
.../gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-9.c | 2 +-
.../gcc.target/riscv/rvv/vsetvl/vlmax_call-1.c | 2 +-
.../gcc.target/riscv/rvv/vsetvl/vlmax_call-2.c | 2 +-
.../gcc.target/riscv/rvv/vsetvl/vlmax_call-3.c | 2 +-
.../gcc.target/riscv/rvv/vsetvl/vlmax_call-4.c | 2 +-
.../riscv/rvv/vsetvl/vlmax_complex_loop-1.c | 2 +-
.../riscv/rvv/vsetvl/vlmax_complex_loop-2.c | 2 +-
.../gcc.target/riscv/rvv/vsetvl/vlmax_conflict-1.c | 2 +-
.../riscv/rvv/vsetvl/vlmax_conflict-10.c | 2 +-
.../riscv/rvv/vsetvl/vlmax_conflict-11.c | 2 +-
.../riscv/rvv/vsetvl/vlmax_conflict-12.c | 2 +-
.../riscv/rvv/vsetvl/vlmax_conflict-13.c | 2 +-
.../gcc.target/riscv/rvv/vsetvl/vlmax_conflict-2.c | 2 +-
.../gcc.target/riscv/rvv/vsetvl/vlmax_conflict-3.c | 2 +-
.../gcc.target/riscv/rvv/vsetvl/vlmax_conflict-4.c | 2 +-
.../gcc.target/riscv/rvv/vsetvl/vlmax_conflict-5.c | 2 +-
.../gcc.target/riscv/rvv/vsetvl/vlmax_conflict-6.c | 2 +-
.../gcc.target/riscv/rvv/vsetvl/vlmax_conflict-7.c | 2 +-
.../gcc.target/riscv/rvv/vsetvl/vlmax_conflict-8.c | 2 +-
.../gcc.target/riscv/rvv/vsetvl/vlmax_conflict-9.c | 2 +-
.../riscv/rvv/vsetvl/vlmax_miss_default-1.c | 2 +-
.../riscv/rvv/vsetvl/vlmax_miss_default-10.c | 2 +-
.../riscv/rvv/vsetvl/vlmax_miss_default-11.c | 2 +-
.../riscv/rvv/vsetvl/vlmax_miss_default-12.c | 2 +-
.../riscv/rvv/vsetvl/vlmax_miss_default-13.c | 2 +-
.../riscv/rvv/vsetvl/vlmax_miss_default-14.c | 2 +-
.../riscv/rvv/vsetvl/vlmax_miss_default-15.c | 2 +-
.../riscv/rvv/vsetvl/vlmax_miss_default-16.c | 2 +-
.../riscv/rvv/vsetvl/vlmax_miss_default-17.c | 2 +-
.../riscv/rvv/vsetvl/vlmax_miss_default-18.c | 2 +-
.../riscv/rvv/vsetvl/vlmax_miss_default-19.c | 2 +-
.../riscv/rvv/vsetvl/vlmax_miss_default-2.c | 2 +-
.../riscv/rvv/vsetvl/vlmax_miss_default-20.c | 2 +-
.../riscv/rvv/vsetvl/vlmax_miss_default-21.c | 2 +-
.../riscv/rvv/vsetvl/vlmax_miss_default-22.c | 2 +-
.../riscv/rvv/vsetvl/vlmax_miss_default-23.c | 2 +-
.../riscv/rvv/vsetvl/vlmax_miss_default-24.c | 2 +-
.../riscv/rvv/vsetvl/vlmax_miss_default-25.c | 2 +-
.../riscv/rvv/vsetvl/vlmax_miss_default-26.c | 2 +-
.../riscv/rvv/vsetvl/vlmax_miss_default-27.c | 2 +-
.../riscv/rvv/vsetvl/vlmax_miss_default-28.c | 2 +-
.../riscv/rvv/vsetvl/vlmax_miss_default-3.c | 2 +-
.../riscv/rvv/vsetvl/vlmax_miss_default-4.c | 2 +-
.../riscv/rvv/vsetvl/vlmax_miss_default-5.c | 2 +-
.../riscv/rvv/vsetvl/vlmax_miss_default-6.c | 2 +-
.../riscv/rvv/vsetvl/vlmax_miss_default-7.c | 2 +-
.../riscv/rvv/vsetvl/vlmax_miss_default-8.c | 2 +-
.../riscv/rvv/vsetvl/vlmax_miss_default-9.c | 2 +-
.../gcc.target/riscv/rvv/vsetvl/vlmax_phi-1.c | 2 +-
.../gcc.target/riscv/rvv/vsetvl/vlmax_phi-10.c | 2 +-
.../gcc.target/riscv/rvv/vsetvl/vlmax_phi-11.c | 2 +-
.../gcc.target/riscv/rvv/vsetvl/vlmax_phi-12.c | 2 +-
.../gcc.target/riscv/rvv/vsetvl/vlmax_phi-13.c | 2 +-
.../gcc.target/riscv/rvv/vsetvl/vlmax_phi-14.c | 2 +-
.../gcc.target/riscv/rvv/vsetvl/vlmax_phi-15.c | 2 +-
.../gcc.target/riscv/rvv/vsetvl/vlmax_phi-16.c | 2 +-
.../gcc.target/riscv/rvv/vsetvl/vlmax_phi-17.c | 2 +-
.../gcc.target/riscv/rvv/vsetvl/vlmax_phi-18.c | 2 +-
.../gcc.target/riscv/rvv/vsetvl/vlmax_phi-19.c | 2 +-
.../gcc.target/riscv/rvv/vsetvl/vlmax_phi-2.c | 2 +-
.../gcc.target/riscv/rvv/vsetvl/vlmax_phi-20.c | 2 +-
.../gcc.target/riscv/rvv/vsetvl/vlmax_phi-21.c | 2 +-
.../gcc.target/riscv/rvv/vsetvl/vlmax_phi-22.c | 2 +-
.../gcc.target/riscv/rvv/vsetvl/vlmax_phi-23.c | 2 +-
.../gcc.target/riscv/rvv/vsetvl/vlmax_phi-24.c | 2 +-
.../gcc.target/riscv/rvv/vsetvl/vlmax_phi-25.c | 2 +-
.../gcc.target/riscv/rvv/vsetvl/vlmax_phi-26.c | 2 +-
.../gcc.target/riscv/rvv/vsetvl/vlmax_phi-27.c | 2 +-
.../gcc.target/riscv/rvv/vsetvl/vlmax_phi-28.c | 2 +-
.../gcc.target/riscv/rvv/vsetvl/vlmax_phi-3.c | 2 +-
.../gcc.target/riscv/rvv/vsetvl/vlmax_phi-4.c | 2 +-
.../gcc.target/riscv/rvv/vsetvl/vlmax_phi-5.c | 2 +-
.../gcc.target/riscv/rvv/vsetvl/vlmax_phi-6.c | 2 +-
.../gcc.target/riscv/rvv/vsetvl/vlmax_phi-7.c | 2 +-
.../gcc.target/riscv/rvv/vsetvl/vlmax_phi-8.c | 2 +-
.../gcc.target/riscv/rvv/vsetvl/vlmax_phi-9.c | 2 +-
.../riscv/rvv/vsetvl/vlmax_single_block-1.c | 2 +-
.../riscv/rvv/vsetvl/vlmax_single_block-10.c | 2 +-
.../riscv/rvv/vsetvl/vlmax_single_block-11.c | 2 +-
.../riscv/rvv/vsetvl/vlmax_single_block-12.c | 2 +-
.../riscv/rvv/vsetvl/vlmax_single_block-13.c | 2 +-
.../riscv/rvv/vsetvl/vlmax_single_block-14.c | 2 +-
.../riscv/rvv/vsetvl/vlmax_single_block-15.c | 2 +-
.../riscv/rvv/vsetvl/vlmax_single_block-16.c | 2 +-
.../riscv/rvv/vsetvl/vlmax_single_block-17.c | 2 +-
.../riscv/rvv/vsetvl/vlmax_single_block-18.c | 2 +-
.../riscv/rvv/vsetvl/vlmax_single_block-19.c | 2 +-
.../riscv/rvv/vsetvl/vlmax_single_block-2.c | 2 +-
.../riscv/rvv/vsetvl/vlmax_single_block-3.c | 2 +-
.../riscv/rvv/vsetvl/vlmax_single_block-4.c | 2 +-
.../riscv/rvv/vsetvl/vlmax_single_block-5.c | 2 +-
.../riscv/rvv/vsetvl/vlmax_single_block-6.c | 2 +-
.../riscv/rvv/vsetvl/vlmax_single_block-7.c | 2 +-
.../riscv/rvv/vsetvl/vlmax_single_block-8.c | 2 +-
.../riscv/rvv/vsetvl/vlmax_single_block-9.c | 2 +-
.../riscv/rvv/vsetvl/vlmax_single_vtype-1.c | 2 +-
.../riscv/rvv/vsetvl/vlmax_single_vtype-2.c | 2 +-
.../riscv/rvv/vsetvl/vlmax_single_vtype-3.c | 2 +-
.../riscv/rvv/vsetvl/vlmax_single_vtype-4.c | 2 +-
.../riscv/rvv/vsetvl/vlmax_single_vtype-5.c | 2 +-
.../riscv/rvv/vsetvl/vlmax_single_vtype-6.c | 2 +-
.../riscv/rvv/vsetvl/vlmax_single_vtype-7.c | 2 +-
.../riscv/rvv/vsetvl/vlmax_single_vtype-8.c | 2 +-
.../riscv/rvv/vsetvl/vlmax_switch_vtype-1.c | 2 +-
.../riscv/rvv/vsetvl/vlmax_switch_vtype-10.c | 2 +-
.../riscv/rvv/vsetvl/vlmax_switch_vtype-11.c | 2 +-
.../riscv/rvv/vsetvl/vlmax_switch_vtype-12.c | 2 +-
.../riscv/rvv/vsetvl/vlmax_switch_vtype-13.c | 2 +-
.../riscv/rvv/vsetvl/vlmax_switch_vtype-14.c | 2 +-
.../riscv/rvv/vsetvl/vlmax_switch_vtype-15.c | 2 +-
.../riscv/rvv/vsetvl/vlmax_switch_vtype-16.c | 2 +-
.../riscv/rvv/vsetvl/vlmax_switch_vtype-2.c | 2 +-
.../riscv/rvv/vsetvl/vlmax_switch_vtype-3.c | 2 +-
.../riscv/rvv/vsetvl/vlmax_switch_vtype-4.c | 2 +-
.../riscv/rvv/vsetvl/vlmax_switch_vtype-5.c | 2 +-
.../riscv/rvv/vsetvl/vlmax_switch_vtype-6.c | 2 +-
.../riscv/rvv/vsetvl/vlmax_switch_vtype-7.c | 2 +-
.../riscv/rvv/vsetvl/vlmax_switch_vtype-8.c | 2 +-
.../riscv/rvv/vsetvl/vlmax_switch_vtype-9.c | 2 +-
.../gcc.target/riscv/rvv/vsetvl/vsetvl-1.c | 2 +-
.../gcc.target/riscv/rvv/vsetvl/vsetvl-10.c | 2 +-
.../gcc.target/riscv/rvv/vsetvl/vsetvl-11.c | 2 +-
.../gcc.target/riscv/rvv/vsetvl/vsetvl-12.c | 2 +-
.../gcc.target/riscv/rvv/vsetvl/vsetvl-13.c | 2 +-
.../gcc.target/riscv/rvv/vsetvl/vsetvl-14.c | 2 +-
.../gcc.target/riscv/rvv/vsetvl/vsetvl-15.c | 2 +-
.../gcc.target/riscv/rvv/vsetvl/vsetvl-16.c | 2 +-
.../gcc.target/riscv/rvv/vsetvl/vsetvl-17.c | 2 +-
.../gcc.target/riscv/rvv/vsetvl/vsetvl-18.c | 2 +-
.../gcc.target/riscv/rvv/vsetvl/vsetvl-19.c | 2 +-
.../gcc.target/riscv/rvv/vsetvl/vsetvl-2.c | 2 +-
.../gcc.target/riscv/rvv/vsetvl/vsetvl-20.c | 2 +-
.../gcc.target/riscv/rvv/vsetvl/vsetvl-21.c | 2 +-
.../gcc.target/riscv/rvv/vsetvl/vsetvl-22.c | 2 +-
.../gcc.target/riscv/rvv/vsetvl/vsetvl-23.c | 2 +-
.../gcc.target/riscv/rvv/vsetvl/vsetvl-24.c | 2 +-
.../gcc.target/riscv/rvv/vsetvl/vsetvl-3.c | 2 +-
.../gcc.target/riscv/rvv/vsetvl/vsetvl-4.c | 2 +-
.../gcc.target/riscv/rvv/vsetvl/vsetvl-5.c | 2 +-
.../gcc.target/riscv/rvv/vsetvl/vsetvl-6.c | 2 +-
.../gcc.target/riscv/rvv/vsetvl/vsetvl-7.c | 2 +-
.../gcc.target/riscv/rvv/vsetvl/vsetvl-8.c | 2 +-
.../gcc.target/riscv/rvv/vsetvl/vsetvl-9.c | 2 +-
.../gcc.target/riscv/rvv/vsetvl/vsetvl_bug-1.c | 2 +-
.../gcc.target/riscv/rvv/vsetvl/vsetvl_bug-2.c | 2 +-
.../gcc.target/riscv/rvv/vsetvl/vsetvl_int.c | 2 +-
.../gcc.target/riscv/rvv/vsetvl/vsetvl_pre-1.c | 2 +-
.../gcc.target/riscv/rvv/vsetvl/vsetvlmax-1.c | 2 +-
.../gcc.target/riscv/rvv/vsetvl/vsetvlmax-10.c | 2 +-
.../gcc.target/riscv/rvv/vsetvl/vsetvlmax-11.c | 2 +-
.../gcc.target/riscv/rvv/vsetvl/vsetvlmax-12.c | 2 +-
.../gcc.target/riscv/rvv/vsetvl/vsetvlmax-13.c | 2 +-
.../gcc.target/riscv/rvv/vsetvl/vsetvlmax-14.c | 2 +-
.../gcc.target/riscv/rvv/vsetvl/vsetvlmax-15.c | 2 +-
.../gcc.target/riscv/rvv/vsetvl/vsetvlmax-16.c | 2 +-
.../gcc.target/riscv/rvv/vsetvl/vsetvlmax-17.c | 2 +-
.../gcc.target/riscv/rvv/vsetvl/vsetvlmax-18.c | 2 +-
.../gcc.target/riscv/rvv/vsetvl/vsetvlmax-19.c | 2 +-
.../gcc.target/riscv/rvv/vsetvl/vsetvlmax-2.c | 2 +-
.../gcc.target/riscv/rvv/vsetvl/vsetvlmax-20.c | 2 +-
.../gcc.target/riscv/rvv/vsetvl/vsetvlmax-3.c | 2 +-
.../gcc.target/riscv/rvv/vsetvl/vsetvlmax-4.c | 2 +-
.../gcc.target/riscv/rvv/vsetvl/vsetvlmax-5.c | 2 +-
.../gcc.target/riscv/rvv/vsetvl/vsetvlmax-6.c | 2 +-
.../gcc.target/riscv/rvv/vsetvl/vsetvlmax-7.c | 2 +-
.../gcc.target/riscv/rvv/vsetvl/vsetvlmax-8.c | 2 +-
.../gcc.target/riscv/rvv/vsetvl/vsetvlmax-9.c | 2 +-
.../gcc.target/riscv/rvv/vsetvl/wredsum_vlmax.c | 2 +-
1351 files changed, 1482 insertions(+), 1413 deletions(-)
diff --git a/gcc/config/riscv/riscv-avlprop.cc b/gcc/config/riscv/riscv-avlprop.cc
index 893b83957fd..4ae15f25ca2 100644
--- a/gcc/config/riscv/riscv-avlprop.cc
+++ b/gcc/config/riscv/riscv-avlprop.cc
@@ -506,7 +506,7 @@ pass_avlprop::execute (function *fn)
simplify_replace_vlmax_avl (rinsn, prop.second);
}
- if (riscv_autovec_preference == RVV_FIXED_VLMAX)
+ if (rvv_vector_bits == RVV_VECTOR_BITS_ZVL)
{
/* Simplify VLMAX AVL into immediate AVL.
E.g. Simplify this following case:
diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h
index 4edddbadc37..281dd068c55 100644
--- a/gcc/config/riscv/riscv-opts.h
+++ b/gcc/config/riscv/riscv-opts.h
@@ -72,13 +72,6 @@ enum stack_protector_guard {
SSP_GLOBAL /* global canary */
};
-/* RISC-V auto-vectorization preference. */
-enum riscv_autovec_preference_enum {
- NO_AUTOVEC,
- RVV_SCALABLE,
- RVV_FIXED_VLMAX
-};
-
/* RISC-V auto-vectorization RVV LMUL. */
enum riscv_autovec_lmul_enum {
RVV_M1 = 1,
@@ -129,6 +122,14 @@ enum vsetvl_strategy_enum {
VSETVL_OPT_NO_FUSION,
};
+/* RVV vector bits for option -mrvv-vector-bits, default is scalable. */
+enum rvv_vector_bits_enum {
+ /* scalable indicates taking the value of zvl*b as the minimal vlen. */
+ RVV_VECTOR_BITS_SCALABLE,
+ /* zvl indicates taking the value of zvl*b as the exactly vlen. */
+ RVV_VECTOR_BITS_ZVL,
+};
+
#define TARGET_ZICOND_LIKE (TARGET_ZICOND || (TARGET_XVENTANACONDOPS && TARGET_64BIT))
/* Bit of riscv_zvl_flags will set contintuly, N-1 bit will set if N-bit is
diff --git a/gcc/config/riscv/riscv-selftests.cc b/gcc/config/riscv/riscv-selftests.cc
index 289916b999e..34d01ac76b7 100644
--- a/gcc/config/riscv/riscv-selftests.cc
+++ b/gcc/config/riscv/riscv-selftests.cc
@@ -378,7 +378,7 @@ riscv_run_selftests (void)
compile-time unknown POLY value.
Since we never need to compute a compile-time unknown POLY value
- when --param=riscv-autovec-preference=fixed-vlmax, disable poly
+ when -mrvv-vector-bits=zvl, disable poly
selftests in such situation. */
run_poly_int_selftests ();
run_const_vector_selftests ();
diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
index 29d58deb995..2d32db06dd1 100644
--- a/gcc/config/riscv/riscv-v.cc
+++ b/gcc/config/riscv/riscv-v.cc
@@ -912,14 +912,14 @@ calculate_ratio (unsigned int sew, enum vlmul_type vlmul)
}
/* SCALABLE means that the vector-length is agnostic (run-time invariant and
- compile-time unknown). FIXED meands that the vector-length is specific
- (compile-time known). Both RVV_SCALABLE and RVV_FIXED_VLMAX are doing
+ compile-time unknown). ZVL meands that the vector-length is specific
+ (compile-time known by march like zvl*b). Both SCALABLE and ZVL are doing
auto-vectorization using VLMAX vsetvl configuration. */
static bool
autovec_use_vlmax_p (void)
{
- return (riscv_autovec_preference == RVV_SCALABLE
- || riscv_autovec_preference == RVV_FIXED_VLMAX);
+ return rvv_vector_bits == RVV_VECTOR_BITS_SCALABLE
+ || rvv_vector_bits == RVV_VECTOR_BITS_ZVL;
}
/* This function emits VLMAX vrgather instruction. Emit vrgather.vx/vi when sel
@@ -4431,7 +4431,7 @@ vls_mode_valid_p (machine_mode vls_mode)
if (!TARGET_VECTOR || TARGET_XTHEADVECTOR)
return false;
- if (riscv_autovec_preference == RVV_SCALABLE)
+ if (rvv_vector_bits == RVV_VECTOR_BITS_SCALABLE)
{
if (GET_MODE_CLASS (vls_mode) != MODE_VECTOR_BOOL
&& !ordered_p (TARGET_MAX_LMUL * BITS_PER_RISCV_VECTOR,
@@ -4448,7 +4448,7 @@ vls_mode_valid_p (machine_mode vls_mode)
return true;
}
- if (riscv_autovec_preference == RVV_FIXED_VLMAX)
+ if (rvv_vector_bits == RVV_VECTOR_BITS_ZVL)
{
machine_mode inner_mode = GET_MODE_INNER (vls_mode);
int precision = GET_MODE_PRECISION (inner_mode).to_constant ();
@@ -5123,13 +5123,13 @@ estimated_poly_value (poly_int64 val, unsigned int kind)
unsigned int width_source
= BITS_PER_RISCV_VECTOR.is_constant ()
? (unsigned int) BITS_PER_RISCV_VECTOR.to_constant ()
- : (unsigned int) RVV_SCALABLE;
+ : (unsigned int) RVV_VECTOR_BITS_SCALABLE;
/* If there is no core-specific information then the minimum and likely
values are based on TARGET_MIN_VLEN vectors and the maximum is based on
the architectural maximum of 65536 bits. */
unsigned int min_vlen_bytes = TARGET_MIN_VLEN / 8 - 1;
- if (width_source == RVV_SCALABLE)
+ if (width_source == RVV_VECTOR_BITS_SCALABLE)
switch (kind)
{
case POLY_VALUE_MIN:
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 5e984ee2a55..9f64f67cbdd 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -8801,10 +8801,10 @@ riscv_init_machine_status (void)
return ggc_cleared_alloc<machine_function> ();
}
-/* Return the VLEN value associated with -march.
+/* Return the VLEN value associated with -march and -mwrvv-vector-bits.
TODO: So far we only support length-agnostic value. */
static poly_uint16
-riscv_convert_vector_bits (struct gcc_options *opts)
+riscv_convert_vector_chunks (struct gcc_options *opts)
{
int chunk_num;
int min_vlen = TARGET_MIN_VLEN_OPTS (opts);
@@ -8847,10 +8847,15 @@ riscv_convert_vector_bits (struct gcc_options *opts)
compile-time constant if TARGET_VECTOR is disabled. */
if (TARGET_VECTOR_OPTS_P (opts))
{
- if (opts->x_riscv_autovec_preference == RVV_FIXED_VLMAX)
- return (int) min_vlen / (riscv_bytes_per_vector_chunk * 8);
- else
- return poly_uint16 (chunk_num, chunk_num);
+ switch (opts->x_rvv_vector_bits)
+ {
+ case RVV_VECTOR_BITS_SCALABLE:
+ return poly_uint16 (chunk_num, chunk_num);
+ case RVV_VECTOR_BITS_ZVL:
+ return (int) min_vlen / (riscv_bytes_per_vector_chunk * 8);
+ default:
+ gcc_unreachable ();
+ }
}
else
return 1;
@@ -8920,8 +8925,8 @@ riscv_override_options_internal (struct gcc_options *opts)
if (TARGET_VECTOR && TARGET_BIG_ENDIAN)
sorry ("Current RISC-V GCC does not support RVV in big-endian mode");
- /* Convert -march to a chunks count. */
- riscv_vector_chunks = riscv_convert_vector_bits (opts);
+ /* Convert -march and -mrvv-vector-bits to a chunks count. */
+ riscv_vector_chunks = riscv_convert_vector_chunks (opts);
}
/* Implement TARGET_OPTION_OVERRIDE. */
diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt
index 20685c42aed..45a95177af3 100644
--- a/gcc/config/riscv/riscv.opt
+++ b/gcc/config/riscv/riscv.opt
@@ -528,23 +528,6 @@ Inline strlen calls if possible.
Target RejectNegative Joined UInteger Var(riscv_strcmp_inline_limit) Init(64)
Max number of bytes to compare as part of inlined strcmp/strncmp routines (default: 64).
-Enum
-Name(riscv_autovec_preference) Type(enum riscv_autovec_preference_enum)
-Valid arguments to -param=riscv-autovec-preference=:
-
-EnumValue
-Enum(riscv_autovec_preference) String(none) Value(NO_AUTOVEC)
-
-EnumValue
-Enum(riscv_autovec_preference) String(scalable) Value(RVV_SCALABLE)
-
-EnumValue
-Enum(riscv_autovec_preference) String(fixed-vlmax) Value(RVV_FIXED_VLMAX)
-
--param=riscv-autovec-preference=
-Target RejectNegative Joined Enum(riscv_autovec_preference) Var(riscv_autovec_preference) Init(RVV_SCALABLE)
--param=riscv-autovec-preference=<string> Set the preference of auto-vectorization in the RISC-V port.
-
Enum
Name(riscv_autovec_lmul) Type(enum riscv_autovec_lmul_enum)
The RVV possible LMUL (-param=riscv-autovec-lmul=):
@@ -607,3 +590,17 @@ Enum(stringop_strategy) String(vector) Value(STRATEGY_VECTOR)
mstringop-strategy=
Target RejectNegative Joined Enum(stringop_strategy) Var(stringop_strategy) Init(STRATEGY_AUTO)
Specify stringop expansion strategy.
+
+Enum
+Name(rvv_vector_bits) Type(enum rvv_vector_bits_enum)
+The possible RVV vector register lengths:
+
+EnumValue
+Enum(rvv_vector_bits) String(scalable) Value(RVV_VECTOR_BITS_SCALABLE)
+
+EnumValue
+Enum(rvv_vector_bits) String(zvl) Value(RVV_VECTOR_BITS_ZVL)
+
+mrvv-vector-bits=
+Target RejectNegative Joined Enum(rvv_vector_bits) Var(rvv_vector_bits) Init(RVV_VECTOR_BITS_SCALABLE)
+-mrvv-vector-bits=<string> Set the kind of bits for an RVV vector register.
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/pr111296.C b/gcc/testsuite/g++.target/riscv/rvv/base/pr111296.C
index 6eb14fd83a8..7410457d549 100644
--- a/gcc/testsuite/g++.target/riscv/rvv/base/pr111296.C
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/pr111296.C
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-std=c++03 -march=rv64gcv -mabi=lp64d -Ofast -ftree-vectorize --param=riscv-autovec-preference=scalable" } */
+/* { dg-options "-std=c++03 -march=rv64gcv -mabi=lp64d -Ofast -ftree-vectorize -mrvv-vector-bits=scalable" } */
struct a
{
diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-6.c b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-6.c
index d2766f5984c..bd7ce23f6b8 100644
--- a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-6.c
+++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-6.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -ftree-vectorize --param riscv-autovec-lmul=dynamic --param riscv-autovec-preference=scalable -fselective-scheduling -fdump-tree-vect-details" } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -ftree-vectorize --param riscv-autovec-lmul=dynamic -mrvv-vector-bits=scalable -fselective-scheduling -fdump-tree-vect-details" } */
#include <stdint-gcc.h>
diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-8.c b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-8.c
index 362c49f1411..61619a0c879 100644
--- a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-8.c
+++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-8.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -ftree-vectorize --param riscv-autovec-lmul=dynamic --param riscv-autovec-preference=scalable -fselective-scheduling -fdump-tree-vect-details" } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -ftree-vectorize --param riscv-autovec-lmul=dynamic -mrvv-vector-bits=scalable -fselective-scheduling -fdump-tree-vect-details" } */
#include <stdint-gcc.h>
diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul8-12.c b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul8-12.c
index d0f354279f5..8a2ebf56144 100644
--- a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul8-12.c
+++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul8-12.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -ftree-vectorize --param riscv-autovec-lmul=dynamic --param riscv-autovec-preference=scalable -fselective-scheduling -fdump-tree-vect-details" } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -ftree-vectorize --param riscv-autovec-lmul=dynamic -mrvv-vector-bits=scalable -fselective-scheduling -fdump-tree-vect-details" } */
void
foo (int *restrict a, int *restrict b, int n)
diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113112-1.c b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113112-1.c
index 2dc39ad8e8b..6d8a1d42492 100644
--- a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113112-1.c
+++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113112-1.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize --param riscv-autovec-lmul=dynamic --param riscv-autovec-preference=fixed-vlmax -fdump-tree-vect-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize --param riscv-autovec-lmul=dynamic -mrvv-vector-bits=zvl -fdump-tree-vect-details" } */
#define N 40
diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113112-2.c b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113112-2.c
index bc4f40d4b9e..9401e395c40 100644
--- a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113112-2.c
+++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113112-2.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize --param riscv-autovec-lmul=dynamic --param riscv-autovec-preference=fixed-vlmax -fdump-tree-vect-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize --param riscv-autovec-lmul=dynamic -mrvv-vector-bits=zvl -fdump-tree-vect-details" } */
#define TYPE double
#define N 200
diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113112-3.c b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113112-3.c
index c80936246d7..07e0cdfbc85 100644
--- a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113112-3.c
+++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113112-3.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize --param riscv-autovec-lmul=dynamic --param riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize --param riscv-autovec-lmul=dynamic -mrvv-vector-bits=zvl" } */
int f[12][100];
diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113112-4.c b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113112-4.c
index 5c55a66ed77..215f6de6572 100644
--- a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113112-4.c
+++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113112-4.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -Ofast -ftree-vectorize --param riscv-autovec-lmul=dynamic --param riscv-autovec-preference=fixed-vlmax -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -Ofast -ftree-vectorize --param riscv-autovec-lmul=dynamic -mrvv-vector-bits=zvl -fno-schedule-insns -fno-schedule-insns2" } */
typedef struct rtx_def *rtx;
struct replacement {
diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113112-5.c b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113112-5.c
index 117d54f68f9..9ab2ab94c79 100644
--- a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113112-5.c
+++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113112-5.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize --param riscv-autovec-lmul=dynamic --param riscv-autovec-preference=fixed-vlmax -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize --param riscv-autovec-lmul=dynamic -mrvv-vector-bits=zvl -fno-schedule-insns -fno-schedule-insns2" } */
typedef struct {
int iatom[3];
diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113247-2.c b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113247-2.c
index 64a53cfca88..af3712c55e4 100644
--- a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113247-2.c
+++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113247-2.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize --param=riscv-autovec-lmul=dynamic --param=riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize --param=riscv-autovec-lmul=dynamic -mrvv-vector-bits=zvl" } */
#include "pr113247-1.c"
diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113247-4.c b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113247-4.c
index c2a46d848e5..470b103c05d 100644
--- a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113247-4.c
+++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113247-4.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize --param=riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -mrvv-vector-bits=zvl" } */
#include "pr113247-1.c"
diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113281-2.c b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113281-2.c
index 31cecec036f..acc70810b4b 100644
--- a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113281-2.c
+++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113281-2.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64d -O3 -ftree-vectorize --param=riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64d -O3 -ftree-vectorize -mrvv-vector-bits=zvl" } */
unsigned char a;
diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113281-4.c b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113281-4.c
index b0305db2d48..3947a9ae671 100644
--- a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113281-4.c
+++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113281-4.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 -ftree-vectorize --param=riscv-autovec-lmul=m8 --param=riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 -ftree-vectorize --param=riscv-autovec-lmul=m8 -mrvv-vector-bits=zvl" } */
unsigned char a;
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/align-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/align-1.c
index 64007ee6799..d1cd70dd1ef 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/align-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/align-1.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 --param riscv-autovec-preference=scalable" } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -mrvv-vector-bits=scalable" } */
void __attribute__((noinline, noclone))
f (int * __restrict dst, int * __restrict op1, int * __restrict op2, int count)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/align-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/align-2.c
index a82f34e0464..c36819e26a7 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/align-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/align-2.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 --param riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -mrvv-vector-bits=zvl" } */
void __attribute__((noinline, noclone))
f (int * __restrict dst, int * __restrict op1, int * __restrict op2, int count)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/copysign-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/copysign-run.c
index d97555bb5de..bbe6e9043ed 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/copysign-run.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/copysign-run.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=zvl -ffast-math" } */
#include "copysign-template.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/copysign-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/copysign-rv32gcv.c
index db29e37598a..71c8dd7f2b9 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/copysign-rv32gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/copysign-rv32gcv.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -O3 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */
+/* { dg-additional-options "-std=c99 -O3 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=zvl -ffast-math" } */
#include "copysign-template.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/copysign-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/copysign-rv64gcv.c
index 1c2504915cc..76dbe5ba83c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/copysign-rv64gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/copysign-rv64gcv.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -O3 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */
+/* { dg-additional-options "-std=c99 -O3 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=zvl -ffast-math" } */
#include "copysign-template.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/copysign-zvfh-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/copysign-zvfh-run.c
index e71b6589fc3..47938eadb74 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/copysign-zvfh-run.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/copysign-zvfh-run.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v && riscv_zvfh } } } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=zvl -ffast-math" } */
#include "copysign-template.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/fmax-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/fmax-1.c
index d635499c017..bc04881fc59 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/fmax-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/fmax-1.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=scalable --param vect-epilogues-nomask=0 -fno-signaling-nans" } */
+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable --param vect-epilogues-nomask=0 -fno-signaling-nans" } */
#include <stdint-gcc.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/fmax_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/fmax_run-1.c
index 31661ee8900..20c67c6aa1b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/fmax_run-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/fmax_run-1.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-signaling-nans" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-signaling-nans" } */
#include <math.h>
#include "fmax-1.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/fmax_zvfh-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/fmax_zvfh-1.c
index 7e04cbff1e2..88815d99169 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/fmax_zvfh-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/fmax_zvfh-1.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable --param vect-epilogues-nomask=0 -fno-signaling-nans" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable --param vect-epilogues-nomask=0 -fno-signaling-nans" } */
#include <stdint-gcc.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/fmax_zvfh_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/fmax_zvfh_run-1.c
index f8c39e39fa5..bbfad07630b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/fmax_zvfh_run-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/fmax_zvfh_run-1.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_zvfh && riscv_zfh } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-signaling-nans" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-signaling-nans" } */
#include <math.h>
#include "fmax_zvfh-1.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/fmin-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/fmin-1.c
index 0d2b53e21dc..90f9378129e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/fmin-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/fmin-1.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=scalable --param vect-epilogues-nomask=0 -fno-signaling-nans" } */
+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable --param vect-epilogues-nomask=0 -fno-signaling-nans" } */
#include <stdint-gcc.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/fmin_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/fmin_run-1.c
index 1964137347f..7d49e6f171b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/fmin_run-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/fmin_run-1.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -fno-signaling-nans" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -fno-signaling-nans" } */
#define FN(X) __builtin_fmin##X
#include "fmax_run-1.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/fmin_zvfh-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/fmin_zvfh-1.c
index c7865be19ce..d8d362e1e2d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/fmin_zvfh-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/fmin_zvfh-1.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable --param vect-epilogues-nomask=0 -fno-signaling-nans" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable --param vect-epilogues-nomask=0 -fno-signaling-nans" } */
#include <stdint-gcc.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/fmin_zvfh_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/fmin_zvfh_run-1.c
index 14913eea1e7..388189238d0 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/fmin_zvfh_run-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/fmin_zvfh_run-1.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_zvfh && riscv_zfh } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-signaling-nans" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-signaling-nans" } */
#define FN(X) __builtin_fmin##X
#include "fmax_zvfh_run-1.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/mulh-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/mulh-1.c
index 265a332712a..fd9c1c3baf4 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/mulh-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/mulh-1.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */
#include <stdint-gcc.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/mulh-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/mulh-2.c
index 18faaadd68c..664593c8be1 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/mulh-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/mulh-2.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */
#include <stdint-gcc.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/mulh_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/mulh_run-1.c
index 6f7689d4bb3..e79d6aa04f7 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/mulh_run-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/mulh_run-1.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable" } */
#include "mulh-1.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/mulh_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/mulh_run-2.c
index a0f744ad6f6..25c7806b91d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/mulh_run-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/mulh_run-2.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable" } */
#include "mulh-2.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/narrow-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/narrow-1.c
index 48a2386fb7c..06ce0b1df23 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/narrow-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/narrow-1.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */
#include <stdint-gcc.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/narrow-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/narrow-2.c
index 86b766141b2..846ae1aeaa9 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/narrow-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/narrow-2.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */
#include <stdint-gcc.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/narrow-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/narrow-3.c
index 370498f0d7f..70772c0ba6f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/narrow-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/narrow-3.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv64gcv -mabi=lp64d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-march=rv64gcv -mabi=lp64d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */
#include <stdint-gcc.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/narrow_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/narrow_run-1.c
index 32a7200679d..d33a2a71100 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/narrow_run-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/narrow_run-1.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable" } */
#include <assert.h>
#include "narrow-1.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/narrow_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/narrow_run-2.c
index 5c414b18295..01123e15eef 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/narrow_run-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/narrow_run-2.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable" } */
#include <assert.h>
#include "narrow-2.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/narrow_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/narrow_run-3.c
index 21f8e8f3667..04a621b5bd3 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/narrow_run-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/narrow_run-3.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable" } */
#include <assert.h>
#include "narrow-3.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-immediate.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-immediate.c
index a2e1c33f4fa..1036c5d142e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-immediate.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-immediate.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -march=rv32gcv -mabi=ilp32d -O2 --param=riscv-autovec-preference=scalable" } */
+/* { dg-additional-options "-std=c99 -march=rv32gcv -mabi=ilp32d -O2 -mrvv-vector-bits=scalable" } */
#define uint8_t unsigned char
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-run.c
index d661c19a9ba..087138c42c1 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-run.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-run.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=zvl" } */
#include "shift-template.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-rv32gcv.c
index d5348855aa0..c80e4043850 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-rv32gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-rv32gcv.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=zvl" } */
#include "shift-template.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-rv64gcv.c
index a533dc79bc0..95e974ace2a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-rv64gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-rv64gcv.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv -mabi=lp64d -mrvv-vector-bits=zvl" } */
#include "shift-template.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-scalar-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-scalar-run.c
index 47906885476..08f35581b67 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-scalar-run.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-scalar-run.c
@@ -1,4 +1,4 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=zvl" } */
#include "shift-scalar-template.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-scalar-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-scalar-rv32gcv.c
index 8850d389c3a..e1383fddc46 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-scalar-rv32gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-scalar-rv32gcv.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=zvl" } */
#include "shift-scalar-template.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-scalar-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-scalar-rv64gcv.c
index 82a5fe23e7d..ecfcc5eb1ab 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-scalar-rv64gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-scalar-rv64gcv.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv -mabi=lp64d -mrvv-vector-bits=zvl" } */
#include "shift-scalar-template.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-scalar-template.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-scalar-template.h
index 2cf645af26e..604696f33ec 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-scalar-template.h
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-scalar-template.h
@@ -1,6 +1,6 @@
/* Test shifts by scalar (immediate or register) amount. */
/* { dg-do run } */
-/* { dg-additional-options "-std=c99 --param=riscv-autovec-preference=scalable -fno-vect-cost-model --save-temps" } */
+/* { dg-additional-options "-std=c99 -mrvv-vector-bits=scalable -fno-vect-cost-model --save-temps" } */
#include <stdint-gcc.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-run-nofm.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-run-nofm.c
index b6328d0ad65..1de8685575b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-run-nofm.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-run-nofm.c
@@ -1,4 +1,4 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=scalable" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=scalable" } */
#include "vadd-run.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-run.c
index ba453d18c66..f62bb394854 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-run.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-run.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=zvl -ffast-math" } */
#include "vadd-template.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-rv32gcv-nofm.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-rv32gcv-nofm.c
index 60c760d939d..06a30de5dfd 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-rv32gcv-nofm.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-rv32gcv-nofm.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fdump-tree-optimized-details" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-optimized-details" } */
#include "vadd-template.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-rv32gcv.c
index cd0da74d8a5..a3b012631be 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-rv32gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-rv32gcv.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=zvl -ffast-math" } */
#include "vadd-template.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-rv64gcv-nofm.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-rv64gcv-nofm.c
index 86d5283c4b6..64dd3441384 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-rv64gcv-nofm.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-rv64gcv-nofm.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d --param=riscv-autovec-preference=scalable -fdump-tree-optimized-details" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable -fdump-tree-optimized-details" } */
#include "vadd-template.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-rv64gcv.c
index 30c3ef7bd4f..ef52f49657b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-rv64gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-rv64gcv.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=zvl -ffast-math" } */
#include "vadd-template.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-zvfh-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-zvfh-run.c
index 6c2d096e103..c567decc37e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-zvfh-run.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-zvfh-run.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v && riscv_zvfh } } } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=zvl -ffast-math" } */
#include "vadd-template.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vand-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vand-run.c
index 848b6eb77f6..5a03db26826 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vand-run.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vand-run.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=zvl" } */
#include "vand-template.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vand-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vand-rv32gcv.c
index f7636abdec0..a306170d6ba 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vand-rv32gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vand-rv32gcv.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=zvl" } */
#include "vand-template.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vand-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vand-rv64gcv.c
index dee8a2d6124..536212c0e78 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vand-rv64gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vand-rv64gcv.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv -mabi=lp64d -mrvv-vector-bits=zvl" } */
#include "vand-template.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vcompress-avlprop-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vcompress-avlprop-1.c
index 43f79fe3b7b..32d81beb881 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vcompress-avlprop-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vcompress-avlprop-1.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvl512b -mabi=lp64d -O3 --param=riscv-autovec-preference=fixed-vlmax -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-march=rv64gcv_zvl512b -mabi=lp64d -O3 -mrvv-vector-bits=zvl -fno-schedule-insns -fno-schedule-insns2" } */
/* { dg-final { check-function-bodies "**" "" } } */
#define MAX 10
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-run-nofm.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-run-nofm.c
index 8b266178d2e..e436d27de7d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-run-nofm.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-run-nofm.c
@@ -1,4 +1,4 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=scalable" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=scalable" } */
#include "vdiv-run.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-run.c
index 4ce2ceee6cd..fee2d994f57 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-run.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-run.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=zvl -ffast-math" } */
#include "vdiv-template.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv32gcv-nofm.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv32gcv-nofm.c
index f7d77047ad1..095dcaa6681 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv32gcv-nofm.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv32gcv-nofm.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fdump-tree-optimized-details" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-optimized-details" } */
#include "vdiv-template.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv32gcv.c
index bb421fa7134..8a400804d52 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv32gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv32gcv.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -ffast-math -fdump-tree-optimized-details" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=zvl -ffast-math -fdump-tree-optimized-details" } */
#include "vdiv-template.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv64gcv-nofm.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv64gcv-nofm.c
index 0dd4df6a5c5..b1fae22a766 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv64gcv-nofm.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv64gcv-nofm.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d --param=riscv-autovec-preference=scalable -fdump-tree-optimized-details" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable -fdump-tree-optimized-details" } */
#include "vdiv-template.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv64gcv.c
index 9764cc3f1fd..4ec78b28aea 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv64gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv64gcv.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax -ffast-math -fdump-tree-optimized-details" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=zvl -ffast-math -fdump-tree-optimized-details" } */
#include "vdiv-template.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-zvfh-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-zvfh-run.c
index c9f9d83ccb8..7b9e5eb192e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-zvfh-run.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-zvfh-run.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v && riscv_zvfh } } } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=zvl -ffast-math" } */
#include "vdiv-template.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmax-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmax-run.c
index 9b03aa34955..282356d10c8 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmax-run.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmax-run.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=zvl -ffast-math" } */
#include "vmax-template.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmax-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmax-rv32gcv.c
index fbfa3ab057d..9876ce3ffc6 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmax-rv32gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmax-rv32gcv.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=zvl -ffast-math" } */
#include "vmax-template.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmax-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmax-rv64gcv.c
index cf01ebc65f8..c079932d8e1 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmax-rv64gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmax-rv64gcv.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=zvl -ffast-math" } */
#include "vmax-template.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmax-zvfh-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmax-zvfh-run.c
index 85e19c1ff43..292a23f6c3e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmax-zvfh-run.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmax-zvfh-run.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v && riscv_zvfh } } } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=zvl -ffast-math" } */
#include "vmax-template.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmin-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmin-run.c
index 6fce322950b..512a80278c4 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmin-run.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmin-run.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=zvl -ffast-math" } */
#include "vmin-template.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmin-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmin-rv32gcv.c
index 87640732b3b..079ed7cb0be 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmin-rv32gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmin-rv32gcv.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=zvl -ffast-math" } */
#include "vmin-template.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmin-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmin-rv64gcv.c
index 193dacc82c5..3ee49f8bc96 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmin-rv64gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmin-rv64gcv.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=zvl -ffast-math" } */
#include "vmin-template.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmin-zvfh-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmin-zvfh-run.c
index b24d4f3cb16..9ae8c88e3f9 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmin-zvfh-run.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmin-zvfh-run.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v && riscv_zvfh } } } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=zvl -ffast-math" } */
#include "vmin-template.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-run-nofm.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-run-nofm.c
index 4f4566ac763..dccf9a5f373 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-run-nofm.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-run-nofm.c
@@ -1,4 +1,4 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=scalable" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=scalable" } */
#include "vmul-run.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-run.c
index 37049953bcc..988876d23d6 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-run.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-run.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=zvl -ffast-math" } */
#include "vmul-template.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-rv32gcv-nofm.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-rv32gcv-nofm.c
index 3e0f06162fc..571623d5ffd 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-rv32gcv-nofm.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-rv32gcv-nofm.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fdump-tree-optimized-details" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-optimized-details" } */
#include "vmul-template.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-rv32gcv.c
index 7d3dfade0ee..19a1f1d10e9 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-rv32gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-rv32gcv.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=zvl -ffast-math" } */
#include "vmul-template.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-rv64gcv-nofm.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-rv64gcv-nofm.c
index ca245e28662..4ff7a1d07bb 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-rv64gcv-nofm.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-rv64gcv-nofm.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d --param=riscv-autovec-preference=scalable -fdump-tree-optimized-details" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable -fdump-tree-optimized-details" } */
#include "vmul-template.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-rv64gcv.c
index a549d6f7be4..e2c2f2f70d8 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-rv64gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-rv64gcv.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=zvl -ffast-math" } */
#include "vmul-template.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-zvfh-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-zvfh-run.c
index 63bcf707756..491b36504b5 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-zvfh-run.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-zvfh-run.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v && riscv_zvfh } } } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=zvl -ffast-math" } */
#include "vmul-template.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vor-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vor-run.c
index 10b3499644a..f69a82c7876 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vor-run.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vor-run.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=zvl" } */
#include "vor-template.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vor-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vor-rv32gcv.c
index 70ea8ef65cc..20015687cce 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vor-rv32gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vor-rv32gcv.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=zvl" } */
#include "vor-template.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vor-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vor-rv64gcv.c
index 44d09a2bddc..f09944e42e6 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vor-rv64gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vor-rv64gcv.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv -mabi=lp64d -mrvv-vector-bits=zvl" } */
#include "vor-template.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrem-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrem-run.c
index a08038eb231..6425ea65ca3 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrem-run.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrem-run.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=zvl" } */
#include "vrem-template.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrem-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrem-rv32gcv.c
index 7628f4a3d26..405649559d8 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrem-rv32gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrem-rv32gcv.c
@@ -1,4 +1,4 @@
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -fdump-tree-optimized-details" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=zvl -fdump-tree-optimized-details" } */
#include "vrem-template.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrem-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrem-rv64gcv.c
index 8af9a8b5745..a6b82ce5b4e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrem-rv64gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrem-rv64gcv.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax -fdump-tree-optimized-details" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv -mabi=lp64d -mrvv-vector-bits=zvl -fdump-tree-optimized-details" } */
#include "vrem-template.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-run-nofm.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-run-nofm.c
index 318323e2476..b83ebceb908 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-run-nofm.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-run-nofm.c
@@ -1,4 +1,4 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=scalable" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=scalable" } */
#include "vsub-run.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-run.c
index bd44f5ab399..461521a0c8c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-run.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-run.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=zvl -ffast-math" } */
#include "vsub-template.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-rv32gcv-nofm.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-rv32gcv-nofm.c
index c4ab934cdf5..4853f0bbd5d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-rv32gcv-nofm.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-rv32gcv-nofm.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fdump-tree-optimized-details" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-optimized-details" } */
#include "vsub-template.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-rv32gcv.c
index f09d0664660..57fcb70de1a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-rv32gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-rv32gcv.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=zvl -ffast-math" } */
#include "vsub-template.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-rv64gcv-nofm.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-rv64gcv-nofm.c
index 9e71911a92a..54166c20cf1 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-rv64gcv-nofm.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-rv64gcv-nofm.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d --param=riscv-autovec-preference=scalable -fdump-tree-optimized-details" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable -fdump-tree-optimized-details" } */
#include "vsub-template.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-rv64gcv.c
index 9f44f5fb5ab..626d7c19219 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-rv64gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-rv64gcv.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=zvl -ffast-math" } */
#include "vsub-template.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-zvfh-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-zvfh-run.c
index b438beafeb9..1a5770f07e5 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-zvfh-run.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-zvfh-run.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v && riscv_zvfh } } } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=zvl -ffast-math" } */
#include "vsub-template.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vxor-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vxor-run.c
index 9c03d8f9541..62294420b2e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vxor-run.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vxor-run.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=zvl" } */
#include "vxor-template.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vxor-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vxor-rv32gcv.c
index 83b223e987f..9ea9df8416c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vxor-rv32gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vxor-rv32gcv.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=zvl" } */
#include "vxor-template.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vxor-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vxor-rv64gcv.c
index 6ba007c9d90..6cc943aeddc 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vxor-rv64gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vxor-rv64gcv.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv -mabi=lp64d -mrvv-vector-bits=zvl" } */
#include "vxor-template.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-1.c
index 88059971503..86ad19cb17b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-1.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64d --param=riscv-autovec-lmul=m8 --param=riscv-autovec-preference=fixed-vlmax -fno-vect-cost-model -O3 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64d --param=riscv-autovec-lmul=m8 -mrvv-vector-bits=zvl -fno-vect-cost-model -O3 -fdump-tree-optimized" } */
#include <assert.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-2.c
index 9ff93d3b163..07f9d91dfd3 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-2.c
@@ -1,6 +1,6 @@
/* { dg-do run } */
/* { dg-require-effective-target riscv_v } */
-/* { dg-options "--param=riscv-autovec-lmul=m8 --param=riscv-autovec-preference=scalable -ftree-vectorize -fno-tree-loop-distribute-patterns -fno-vect-cost-model -fno-common -O2" } */
+/* { dg-options "--param=riscv-autovec-lmul=m8 -mrvv-vector-bits=scalable -ftree-vectorize -fno-tree-loop-distribute-patterns -fno-vect-cost-model -fno-common -O2" } */
#define N 128
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-3.c
index 643e91b918e..9af5add3ff9 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-3.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvl512b -mabi=lp64d --param=riscv-autovec-lmul=m8 --param=riscv-autovec-preference=scalable -fno-vect-cost-model -O2 -ffast-math" } */
+/* { dg-options "-march=rv64gcv_zvl512b -mabi=lp64d --param=riscv-autovec-lmul=m8 -mrvv-vector-bits=scalable -fno-vect-cost-model -O2 -ffast-math" } */
#define N 16
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-4.c
index c860e92dc3a..1b6ad2654fc 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-4.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gc_zve32f -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 --param=riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-options "-march=rv64gc_zve32f -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -mrvv-vector-bits=zvl" } */
typedef struct {
short a;
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-5.c
index df16fb28c49..1a3fc1690e6 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-5.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gc_zve32f -mabi=lp64d -O2 --param=riscv-autovec-lmul=m4 --param=riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-options "-march=rv64gc_zve32f -mabi=lp64d -O2 --param=riscv-autovec-lmul=m4 -mrvv-vector-bits=zvl" } */
typedef unsigned char u8;
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-6.c
index 975c4816a28..8bbbf8420b0 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-6.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gc_zve32f -mabi=lp64d -O2 --param=riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-options "-march=rv64gc_zve32f -mabi=lp64d -O2 -mrvv-vector-bits=zvl" } */
extern void abort(void);
extern void exit(int);
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-8.c
index 07b7e1669fe..91fc5dd9f4d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-8.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv32gc_zve32f -mabi=ilp32d -O3 --param=riscv-autovec-lmul=m2 --param=riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-options "-march=rv32gc_zve32f -mabi=ilp32d -O3 --param=riscv-autovec-lmul=m2 -mrvv-vector-bits=zvl" } */
union U
{
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond-1.c
index 99a230d1c8a..0faedacb2c7 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond-1.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */
#include <stdint-gcc.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond-2.c
index 1a82440b0cf..40fa1089b14 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond-2.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */
#include <stdint-gcc.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond-3.c
index 07a90745c59..e52a23a8409 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond-3.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-trapping-math -fno-vect-cost-model" } */
+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable -fno-trapping-math -fno-vect-cost-model" } */
/* The difference here is that nueq can use LTGT. */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond-4.c
index a73f7d8de3b..fc762ad67f6 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond-4.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */
#include <stdint-gcc.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond_run-1.c
index 105533844b1..434921743dc 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond_run-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond_run-1.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable" } */
#include "vcond-1.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond_run-2.c
index 234535dc1c9..355012d1069 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond_run-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond_run-2.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable" } */
/* { dg-require-effective-target fenv_exceptions } */
#include "vcond-2.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond_run-3.c
index e547da67fb4..c111b55f370 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond_run-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond_run-3.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-trapping-math" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-trapping-math" } */
/* { dg-require-effective-target fenv_exceptions } */
#define TEST_EXCEPTIONS 0
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond_run-4.c
index b72a44f590b..bfe8c413de5 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond_run-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond_run-4.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable" } */
#include "vcond-4.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-1.c
index afd73c25a89..0a3b847667e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-1.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math -fdump-tree-optimized-details" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math -fdump-tree-optimized-details" } */
#include <stdint-gcc.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-10.c
index f549b9e3aea..0f62f26fd67 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-10.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-10.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math -fdump-tree-optimized-details" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math -fdump-tree-optimized-details" } */
#include <stdint-gcc.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-11.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-11.c
index 8b6ae61299c..f55a1b544b6 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-11.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-11.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -fdump-tree-optimized-details" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -fdump-tree-optimized-details" } */
#include "cond_arith-1.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-2.c
index 8b6ae61299c..f55a1b544b6 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-2.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -fdump-tree-optimized-details" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -fdump-tree-optimized-details" } */
#include "cond_arith-1.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-3.c
index 7f7d08a0806..c17f618ff43 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-3.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math -fdump-tree-optimized-details" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math -fdump-tree-optimized-details" } */
#include <stdint-gcc.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-4.c
index 8b1acea56a1..68c34c24d1f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-4.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -fdump-tree-optimized-details" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -fdump-tree-optimized-details" } */
#include "cond_arith-3.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-5.c
index d659f67f22c..790a2d626da 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-5.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math -fdump-tree-optimized-details" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math -fdump-tree-optimized-details" } */
#include <stdint-gcc.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-6.c
index ef9e365d1cb..919de838974 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-6.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -fdump-tree-optimized-details" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -fdump-tree-optimized-details" } */
#include "cond_arith-5.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-7.c
index 48c2a2b2bf3..8180d44e6b0 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-7.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -fdump-tree-optimized-details" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -fdump-tree-optimized-details" } */
#include <stdint-gcc.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-8.c
index 375a7b9098c..2aeba6837f2 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-8.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -fdump-tree-optimized-details" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -fdump-tree-optimized-details" } */
#include <stdint-gcc.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-9.c
index fc8b3512e92..4298e8c1050 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-9.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-9.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -fno-vect-cost-model -fdump-tree-optimized-details" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=zvl -fno-vect-cost-model -fdump-tree-optimized-details" } */
#include <stdint-gcc.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-1.c
index df22bd39951..d82a47883dd 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-1.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */
#include "cond_arith-1.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-10.c
index 8e0d365fd19..63c5cabdf37 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-10.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-10.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */
#include "cond_arith-10.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-11.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-11.c
index b2da299f665..85b53b8317e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-11.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-11.c
@@ -1,4 +1,4 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */
#include "cond_arith_run-10.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-2.c
index 2832cc57876..ff8af28999d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-2.c
@@ -1,4 +1,4 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */
#include "cond_arith_run-1.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-3.c
index a73d9f7ca85..98d58068903 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-3.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */
#include "cond_arith-3.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-4.c
index e57f7db648c..4462a459483 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-4.c
@@ -1,4 +1,4 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */
#include "cond_arith_run-3.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-5.c
index 03092f4871b..19d381f6043 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-5.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */
#include "cond_arith-5.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-6.c
index 47055de2de8..56e12fa117a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-6.c
@@ -1,4 +1,4 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */
#include "cond_arith_run-5.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-7.c
index 8d679cdba2e..09019ef7283 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-7.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */
#include "cond_arith-7.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-8.c
index 1e317d903f7..b51260de87d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-8.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */
#include "cond_arith-8.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-9.c
index c1a5f713cf8..b82302fcd0a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-9.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-9.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=fixed-vlmax -fno-vect-cost-model -ffast-math" } */
+/* { dg-additional-options "-mrvv-vector-bits=zvl -fno-vect-cost-model -ffast-math" } */
#include "cond_arith-9.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv32-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv32-1.c
index 07512e5f40e..1cfa93b12a5 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv32-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv32-1.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */
#include "cond_convert_float2float-1.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv32-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv32-2.c
index d2d1ea3678f..8bf0e9994d8 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv32-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv32-2.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */
#include "cond_convert_float2float-2.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv64-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv64-1.c
index f793e93ecb1..b2d162d93d4 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv64-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv64-1.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d --param riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */
+/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */
#include "cond_convert_float2float-1.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv64-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv64-2.c
index 79b835a69b4..df571f29792 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv64-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv64-2.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d --param riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */
+/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */
#include "cond_convert_float2float-2.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float_run-1.c
index 31509ec4f68..59432d6552d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float_run-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float_run-1.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */
#include "cond_convert_float2float-1.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float_run-2.c
index cb4fa188867..063101964e8 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float_run-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float_run-2.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */
#include "cond_convert_float2float-2.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv32-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv32-1.c
index b7400018fb4..54971cda3ac 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv32-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv32-1.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */
#include "cond_convert_float2int-1.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv32-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv32-2.c
index 3bc1a4e2eeb..b8da8b05fbd 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv32-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv32-2.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */
#include "cond_convert_float2int-2.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv64-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv64-1.c
index a65317c91cb..5e8ef5068e6 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv64-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv64-1.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d --param riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */
+/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */
#include "cond_convert_float2int-1.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv64-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv64-2.c
index b764b72a6b8..7af99c7d5c1 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv64-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv64-2.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d --param riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */
+/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */
#include "cond_convert_float2int-2.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_run-1.c
index 3f145475a0f..497e8cde5c6 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_run-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_run-1.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */
#include "cond_convert_float2int-1.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_run-2.c
index a47602ad198..0fc40c87b8e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_run-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_run-2.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */
#include "cond_convert_float2int-2.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh-rv32-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh-rv32-1.c
index c13f1348370..dad6ee06a2f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh-rv32-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh-rv32-1.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */
#include "cond_convert_float2int_zvfh-1.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh-rv32-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh-rv32-2.c
index ebb0a595425..733ee5e3698 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh-rv32-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh-rv32-2.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */
#include "cond_convert_float2int_zvfh-2.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh-rv64-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh-rv64-1.c
index 2405c7ff1e0..672b5956b45 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh-rv64-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh-rv64-1.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d --param riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */
+/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */
#include "cond_convert_float2int_zvfh-1.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh-rv64-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh-rv64-2.c
index 3b2455cb8ac..c55b4145216 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh-rv64-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh-rv64-2.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d --param riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */
+/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */
#include "cond_convert_float2int_zvfh-2.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh_run-1.c
index 00f01cadeb9..7f25a0c0a05 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh_run-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh_run-1.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_zvfh && riscv_zfh } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */
#include "cond_convert_float2int_zvfh-1.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh_run-2.c
index c3dc653d783..8e426748a01 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh_run-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh_run-2.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_zvfh && riscv_zfh } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */
#include "cond_convert_float2int_zvfh-2.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv32-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv32-1.c
index a211192e83f..764c860c709 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv32-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv32-1.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */
#include "cond_convert_int2float-2.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv32-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv32-2.c
index a211192e83f..764c860c709 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv32-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv32-2.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */
#include "cond_convert_int2float-2.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv64-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv64-1.c
index 4b3556988b7..f967914a958 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv64-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv64-1.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d --param riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */
+/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */
#include "cond_convert_int2float-1.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv64-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv64-2.c
index 42239ad2f6e..8c43bb1da81 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv64-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv64-2.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d --param riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */
+/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */
#include "cond_convert_int2float-2.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float_run-1.c
index cb7f35d5523..be31f3c1b72 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float_run-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float_run-1.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */
#include "cond_convert_int2float-1.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float_run-2.c
index 1ec6c591a81..1c53f17267d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float_run-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float_run-2.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */
#include "cond_convert_int2float-2.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv32-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv32-1.c
index 84988a70f7f..5eb6030e348 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv32-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv32-1.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */
#include "cond_convert_int2int-1.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv32-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv32-2.c
index 2b6c72fa192..aa6d6d4b7f1 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv32-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv32-2.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */
#include "cond_convert_int2int-2.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv64-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv64-1.c
index e800abe9cf4..33cb9918ef9 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv64-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv64-1.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d --param riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */
#include "cond_convert_int2int-1.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv64-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv64-2.c
index 904e01c918a..082d9e1ed9a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv64-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv64-2.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d --param riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */
#include "cond_convert_int2int-2.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int_run-1.c
index 07b28dc7f0a..d5080e19542 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int_run-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int_run-1.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */
#include "cond_convert_int2int-1.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int_run-2.c
index 3bf63dc98ed..e73300994a0 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int_run-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int_run-2.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */
#include "cond_convert_int2int-2.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_copysign-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_copysign-run.c
index f223ba23e91..d0c1d661ce1 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_copysign-run.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_copysign-run.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=zvl -ffast-math" } */
#include "cond_copysign-template.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_copysign-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_copysign-rv32gcv.c
index 7340cc9e1af..2d12dd10996 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_copysign-rv32gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_copysign-rv32gcv.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -O3 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */
+/* { dg-additional-options "-std=c99 -O3 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=zvl -ffast-math" } */
#include "cond_copysign-template.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_copysign-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_copysign-rv64gcv.c
index 471b56af7ad..b45e139403c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_copysign-rv64gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_copysign-rv64gcv.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -O3 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */
+/* { dg-additional-options "-std=c99 -O3 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=zvl -ffast-math" } */
#include "cond_copysign-template.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_copysign-zvfh-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_copysign-zvfh-run.c
index 79a51307034..ac85495c528 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_copysign-zvfh-run.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_copysign-zvfh-run.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v && riscv_zvfh } } } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=zvl -ffast-math" } */
#include "cond_copysign-template.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-1.c
index 6f37680f0b4..2d30805b287 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-1.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */
#include <stdint-gcc.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-2.c
index eba1ab5d00f..dd55e47f50e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-2.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */
#include <stdint-gcc.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-3.c
index c58eae9a2ca..f99ae2683a3 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-3.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */
#include <stdint-gcc.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-4.c
index 4ad7f720739..e4d67ee3dd0 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-4.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */
#include <stdint-gcc.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd_run-1.c
index daec93bdfb2..61f6457875b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd_run-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd_run-1.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */
#include "cond_fadd-1.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd_run-2.c
index 2908beadb64..aa1ab0240ea 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd_run-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd_run-2.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */
#include "cond_fadd-2.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd_run-3.c
index e35419ec2bd..e4ba2d97ade 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd_run-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd_run-3.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */
#include "cond_fadd-3.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd_run-4.c
index 515afb2f0c0..0a07658d0fe 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd_run-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd_run-4.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */
#include "cond_fadd-4.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-1.c
index b4df366fd6c..88a23aa50c0 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-1.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */
#include <stdint-gcc.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-2.c
index b2ac8e1844c..6c1236ace6b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-2.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */
#include <stdint-gcc.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-3.c
index 6941a7bf911..95f4f04f0cf 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-3.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */
#include <stdint-gcc.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-4.c
index 30cee819c6a..eb5f06800d0 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-4.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */
#include <stdint-gcc.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-5.c
index 9b6a03e43e8..009c613cfd5 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-5.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */
#include <stdint-gcc.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-6.c
index 345f6efd2f1..3b6161a6ca3 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-6.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */
#include <stdint-gcc.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-7.c
index 26a21793442..6ee57dbcb20 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-7.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */
#include <stdint-gcc.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-8.c
index f78fa094c81..eae930337b9 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-8.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */
#include <stdint-gcc.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-1.c
index e344485d1d3..090481e5cef 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-1.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */
#include "cond_fma_fnma-1.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-2.c
index 7517087905a..3551cc3461d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-2.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */
#include "cond_fma_fnma-2.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-3.c
index 98b3c48f7f7..e182d33864f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-3.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */
#include "cond_fma_fnma-3.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-4.c
index e56eea79849..7e7030f9021 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-4.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */
#include "cond_fma_fnma-4.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-5.c
index 0fddce1bdc1..a93775e28ad 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-5.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */
#include "cond_fma_fnma-5.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-6.c
index ea0c1057400..1d686e74a6a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-6.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */
#include "cond_fma_fnma-6.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-7.c
index d282772f8ea..8005504db2a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-7.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */
#include "cond_fma_fnma-7.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-8.c
index 735b8990610..714e5e2b249 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-8.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */
#include "cond_fma_fnma-8.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax-1.c
index fedee13aab8..1415d79c673 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax-1.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -fno-signaling-nans" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -fno-signaling-nans" } */
#include <stdint-gcc.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax-2.c
index 76f69e44f2c..20feebc6f76 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax-2.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -fno-signaling-nans" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -fno-signaling-nans" } */
#include <stdint-gcc.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax-3.c
index bb8d1ae61f1..998877de031 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax-3.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -fno-signaling-nans" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -fno-signaling-nans" } */
#include <stdint-gcc.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax-4.c
index e4bb3838cb7..c2def15327b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax-4.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -fno-signaling-nans" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -fno-signaling-nans" } */
#include <stdint-gcc.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_run-1.c
index 3dc1fb8bd46..0d12168b821 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_run-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_run-1.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -fno-signaling-nans" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -fno-signaling-nans" } */
#include "cond_fmax-1.c"
#include <math.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_run-2.c
index 0cf67561c4d..5283c5b8c2a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_run-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_run-2.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -fno-signaling-nans" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -fno-signaling-nans" } */
#include "cond_fmax-2.c"
#include <math.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_run-3.c
index df4a5ded974..0fb82a9e100 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_run-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_run-3.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -fno-signaling-nans" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -fno-signaling-nans" } */
#include "cond_fmax-3.c"
#include <math.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_run-4.c
index 1b949517637..aea43e62681 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_run-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_run-4.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -fno-signaling-nans" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -fno-signaling-nans" } */
#include "cond_fmax-4.c"
#include <math.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh-1.c
index 1afa2f2a6db..69356fa542c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh-1.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -fno-signaling-nans" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -fno-signaling-nans" } */
#include <stdint-gcc.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh-2.c
index 23762b799c4..819979195e2 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh-2.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -fno-signaling-nans" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -fno-signaling-nans" } */
#include <stdint-gcc.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh-3.c
index 1837fda2414..f9c118f333a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh-3.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -fno-signaling-nans" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -fno-signaling-nans" } */
#include <stdint-gcc.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh-4.c
index 766e42cab2e..69cf109abd3 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh-4.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -fno-signaling-nans" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -fno-signaling-nans" } */
#include <stdint-gcc.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh_run-1.c
index ae6381ab07b..8d29a9aa3ae 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh_run-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh_run-1.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_zvfh && riscv_zfh } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -fno-signaling-nans" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -fno-signaling-nans" } */
#include "cond_fmax_zvfh-1.c"
#include <math.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh_run-2.c
index 697abb2b599..551de890349 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh_run-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh_run-2.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_zvfh && riscv_zfh } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -fno-signaling-nans" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -fno-signaling-nans" } */
#include "cond_fmax_zvfh-2.c"
#include <math.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh_run-3.c
index d4ee99f2925..0b8b312c1a8 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh_run-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh_run-3.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_zvfh && riscv_zfh } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -fno-signaling-nans" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -fno-signaling-nans" } */
#include "cond_fmax_zvfh-3.c"
#include <math.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh_run-4.c
index c006c64f51e..7ad322647c5 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh_run-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh_run-4.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_zvfh && riscv_zfh } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -fno-signaling-nans" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -fno-signaling-nans" } */
#include "cond_fmax_zvfh-4.c"
#include <math.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin-1.c
index 59b22dbc8cf..3e00efa1f00 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin-1.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -fno-signaling-nans" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -fno-signaling-nans" } */
#include <stdint-gcc.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin-2.c
index 500c4bcf526..7d503bfad65 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin-2.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -fno-signaling-nans" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -fno-signaling-nans" } */
#include <stdint-gcc.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin-3.c
index 85b9238cee9..830af5343e3 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin-3.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -fno-signaling-nans" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -fno-signaling-nans" } */
#include <stdint-gcc.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin-4.c
index 5ec7fd7a023..23267416a56 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin-4.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -fno-signaling-nans" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -fno-signaling-nans" } */
#include <stdint-gcc.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_run-1.c
index 139f9f77b34..821333ac201 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_run-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_run-1.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -fno-signaling-nans" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -fno-signaling-nans" } */
#define FN(X) __builtin_fmin##X
#include "cond_fmax_run-1.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_run-2.c
index e9449b8adcb..800b931e1f2 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_run-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_run-2.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -fno-signaling-nans" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -fno-signaling-nans" } */
#define FN(X) __builtin_fmin##X
#include "cond_fmax_run-2.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_run-3.c
index f70c3440a21..82e52f922e0 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_run-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_run-3.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -fno-signaling-nans" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -fno-signaling-nans" } */
#define FN(X) __builtin_fmin##X
#include "cond_fmax_run-3.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_run-4.c
index fe700a2d5f6..823f9e5bc90 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_run-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_run-4.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -fno-signaling-nans" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -fno-signaling-nans" } */
#define FN(X) __builtin_fmin##X
#include "cond_fmax_run-4.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh-1.c
index a839dc3a1d3..c5fcbb82907 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh-1.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -fno-signaling-nans" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -fno-signaling-nans" } */
#include <stdint-gcc.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh-2.c
index 7a3fca26146..936316bd88d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh-2.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -fno-signaling-nans" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -fno-signaling-nans" } */
#include <stdint-gcc.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh-3.c
index ed0493691f7..faf7033bb45 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh-3.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -fno-signaling-nans" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -fno-signaling-nans" } */
#include <stdint-gcc.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh-4.c
index 3ba72d29095..7eafc53b5c0 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh-4.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -fno-signaling-nans" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -fno-signaling-nans" } */
#include <stdint-gcc.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh_run-1.c
index 01a7dfdeb36..a7604346c53 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh_run-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh_run-1.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_zvfh && riscv_zfh } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -fno-signaling-nans" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -fno-signaling-nans" } */
#define FN(X) __builtin_fmin##X
#include "cond_fmax_zvfh_run-1.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh_run-2.c
index c2d693e15a6..0aa57284e45 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh_run-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh_run-2.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_zvfh && riscv_zfh } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -fno-signaling-nans" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -fno-signaling-nans" } */
#define FN(X) __builtin_fmin##X
#include "cond_fmax_zvfh_run-2.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh_run-3.c
index 4c4696851e9..f72e418f491 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh_run-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh_run-3.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_zvfh && riscv_zfh } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -fno-signaling-nans" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -fno-signaling-nans" } */
#define FN(X) __builtin_fmin##X
#include "cond_fmax_zvfh_run-3.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh_run-4.c
index 49a0c671e8a..cd7f4ee2818 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh_run-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh_run-4.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_zvfh && riscv_zfh } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -fno-signaling-nans" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -fno-signaling-nans" } */
#define FN(X) __builtin_fmin##X
#include "cond_fmax_zvfh_run-4.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-1.c
index d3bf00e2a69..52770eee1a2 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-1.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */
#include <stdint-gcc.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-2.c
index f593d563972..586f33a934c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-2.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */
#include <stdint-gcc.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-3.c
index cc23b123853..e7b2d9d1d99 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-3.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */
#include <stdint-gcc.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-4.c
index bd7b27a060e..38597cce36b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-4.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */
#include <stdint-gcc.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-5.c
index bd7b27a060e..38597cce36b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-5.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */
#include <stdint-gcc.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-6.c
index bcb356e1df9..15975bb1a4d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-6.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */
#include <stdint-gcc.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms_run-1.c
index d86ceb86393..3dbc1c56876 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms_run-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms_run-1.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */
#include "cond_fms_fnms-1.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms_run-2.c
index 87c497acf79..83da5f7f316 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms_run-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms_run-2.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */
#include "cond_fms_fnms-2.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms_run-3.c
index 08de30fca8d..3412e975b5c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms_run-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms_run-3.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */
#include "cond_fms_fnms-3.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms_run-4.c
index 46c2157ed38..5f4866b969a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms_run-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms_run-4.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */
#include "cond_fms_fnms-4.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms_run-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms_run-5.c
index 266bee7a4cd..aaa8d983b84 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms_run-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms_run-5.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */
#include "cond_fms_fnms-5.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms_run-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms_run-6.c
index e325f9b74cd..91e1727a8b2 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms_run-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms_run-6.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */
#include "cond_fms_fnms-6.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-1.c
index 9c9ed434cd0..507645b561a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-1.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */
#include <stdint-gcc.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-2.c
index 3e7d1db7af2..880198b7671 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-2.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */
#include <stdint-gcc.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-3.c
index e3c306d589b..698bf20396f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-3.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */
#include <stdint-gcc.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-4.c
index 57163ef36c6..5be36127f00 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-4.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */
#include <stdint-gcc.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-5.c
index 2e031a96215..ae413311231 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-5.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */
#include <stdint-gcc.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul_run-1.c
index 29a75ce380e..9baf89b9c1a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul_run-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul_run-1.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */
#include "cond_fmul-1.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul_run-2.c
index 744f48aefbf..da777a8a6da 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul_run-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul_run-2.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */
#include "cond_fmul-2.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul_run-3.c
index edd940c9baa..975fc609108 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul_run-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul_run-3.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */
#include "cond_fmul-3.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul_run-4.c
index 4dea0861163..d092835db8c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul_run-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul_run-4.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */
#include "cond_fmul-4.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul_run-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul_run-5.c
index c3763b1f4bd..795473253f3 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul_run-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul_run-5.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */
#include "cond_fmul-5.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max-1.c
index f9027026372..80ef479135e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max-1.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */
#include <stdint-gcc.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max-2.c
index 70daec94847..852835d037a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max-2.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */
#include <stdint-gcc.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max-3.c
index 72d498ede21..20ddec09792 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max-3.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */
#include <stdint-gcc.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max-4.c
index a28bf57f183..bd7f14d69fb 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max-4.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */
#include <stdint-gcc.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max-5.c
index 03fb859af3e..6bb161975d0 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max-5.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */
#include <stdint-gcc.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max_run-1.c
index 9ef36ddef92..4d4752b190c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max_run-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max_run-1.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */
#include "cond_logical_min_max-1.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max_run-2.c
index 0d1aec2e2fe..29b1680cf72 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max_run-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max_run-2.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */
#include "cond_logical_min_max-2.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max_run-3.c
index caf9c6a8ae5..92fc5ecefee 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max_run-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max_run-3.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */
#include "cond_logical_min_max-3.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max_run-4.c
index bea7c98e296..2e9b828ad7f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max_run-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max_run-4.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */
#include "cond_logical_min_max-4.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max_run-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max_run-5.c
index bacceb38f45..8e589c460aa 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max_run-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max_run-5.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */
#include "cond_logical_min_max-5.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_mulh-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_mulh-1.c
index 6ff2dc580a4..e0bdf26154c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_mulh-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_mulh-1.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */
#include <stdint-gcc.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_mulh-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_mulh-2.c
index c4c2b50f203..aab3c8d11c2 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_mulh-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_mulh-2.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */
#include <stdint-gcc.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_mulh_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_mulh_run-1.c
index 5dd0b34ba38..6bcf2bf5897 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_mulh_run-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_mulh_run-1.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */
#include "cond_mulh-1.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_mulh_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_mulh_run-2.c
index 183542db486..b62d41d4d31 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_mulh_run-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_mulh_run-2.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */
#include "cond_mulh-2.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_narrow_shift-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_narrow_shift-1.c
index d068110a8a8..6d3748ee9d1 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_narrow_shift-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_narrow_shift-1.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */
#include <stdint-gcc.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_narrow_shift-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_narrow_shift-2.c
index 263799175c9..90c1f5977f6 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_narrow_shift-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_narrow_shift-2.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */
#include <stdint-gcc.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_narrow_shift-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_narrow_shift-3.c
index 17a640b97c7..8ad0ae1cd92 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_narrow_shift-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_narrow_shift-3.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */
#include <stdint-gcc.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_narrow_shift_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_narrow_shift_run-1.c
index ff3646a8d10..a0bfa6134e2 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_narrow_shift_run-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_narrow_shift_run-1.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */
#include "cond_narrow_shift-1.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_narrow_shift_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_narrow_shift_run-2.c
index f3ae207a297..3962dc40ed9 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_narrow_shift_run-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_narrow_shift_run-2.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */
#include "cond_narrow_shift-2.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_narrow_shift_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_narrow_shift_run-3.c
index 0fcf2c5ca0f..27e4147c34a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_narrow_shift_run-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_narrow_shift_run-3.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */
#include "cond_narrow_shift-3.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-1.c
index 1c8a4cacf78..7c9c54a16e3 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-1.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */
#include <stdint-gcc.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-2.c
index eb375ddb26d..cc7f33ee234 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-2.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */
#include <stdint-gcc.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-3.c
index ab1c9e99c05..f84e6ea891c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-3.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */
#include <stdint-gcc.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-4.c
index c7dd3dfc55d..bf429c3d0a0 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-4.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */
#include <stdint-gcc.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-5.c
index cdaa3e1fe55..b632bf2e19e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-5.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */
#include <stdint-gcc.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-6.c
index aa957ddaff9..f61c706df29 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-6.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */
#include <stdint-gcc.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-7.c
index 1f271c6dfb5..355154eff41 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-7.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */
#include <stdint-gcc.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-8.c
index f6dc7ff45bc..b3f29b675fc 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-8.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */
#include <stdint-gcc.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-9.c
index df3f390ea8d..ec3e645ba81 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-9.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-9.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */
#include <stdint-gcc.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-1.c
index 00c309c7677..5e088806406 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-1.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */
#include "cond_shift-1.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-2.c
index ec6f0f8e8de..44543c3e0b0 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-2.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */
#include "cond_shift-2.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-3.c
index 8c6282574b9..8615891cd97 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-3.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */
#include "cond_shift-3.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-4.c
index 32a6f6c42d8..5995912a3c2 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-4.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */
#include "cond_shift-4.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-5.c
index 0b0730ec080..3ca8e220a38 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-5.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */
#include "cond_shift-5.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-6.c
index 31f44eca9bf..a1ed9d1fdbd 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-6.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */
#include "cond_shift-6.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-7.c
index fdd225ec22d..3183efc42a3 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-7.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */
#include "cond_shift-7.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-8.c
index 8ab8e841350..0da7770da9a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-8.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */
#include "cond_shift-8.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-9.c
index fcaa1cdef9c..8a1618e70a6 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-9.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-9.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */
#include "cond_shift-9.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt-1.c
index d6b2f0f572f..175381762d1 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt-1.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv64gcv -mabi=lp64d --param riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */
+/* { dg-additional-options "-march=rv64gcv -mabi=lp64d -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */
#include <stdint-gcc.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt-2.c
index 1c5d3f0a1a4..081185ed0f0 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt-2.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv64gcv -mabi=lp64d --param riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */
+/* { dg-additional-options "-march=rv64gcv -mabi=lp64d -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */
#include <stdint-gcc.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt-zvfh-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt-zvfh-1.c
index c632d63ff7a..7c62bc45ca3 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt-zvfh-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt-zvfh-1.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d --param riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */
+/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */
#include <stdint-gcc.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt-zvfh-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt-zvfh-2.c
index 8e1bc60a0d1..fe6e669fb63 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt-zvfh-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt-zvfh-2.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d --param riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */
+/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */
#include <stdint-gcc.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt_run-1.c
index c3981c85b00..8c2492971e4 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt_run-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt_run-1.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math " } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math " } */
#include "cond_sqrt-1.c"
#include <stdio.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt_run-2.c
index a48e281cc0e..fc6bb6ddfa3 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt_run-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt_run-2.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */
#include "cond_sqrt-2.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt_run-zvfh-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt_run-zvfh-1.c
index e80ac755a92..f40c02345be 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt_run-zvfh-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt_run-zvfh-1.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_zvfh } } } */
-/* { dg-additional-options "--param riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math " } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math " } */
#include "cond_sqrt-zvfh-1.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt_run-zvfh-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt_run-zvfh-2.c
index 6f437b63468..c7e04e10a6c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt_run-zvfh-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt_run-zvfh-2.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_zvfh } } } */
-/* { dg-additional-options "--param riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */
#include "cond_sqrt-zvfh-2.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-1.c
index 28a5e025428..2233c6eeecb 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-1.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d --param riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */
#include <stdint-gcc.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-2.c
index e456e68e327..4886bff67d8 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-2.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d --param riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */
#include <stdint-gcc.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-3.c
index e2a87335079..a75bde9543a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-3.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d --param riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */
#include <stdint-gcc.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-4.c
index 37c7ccb0d97..ef2784bc5d7 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-4.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d --param riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */
#include <stdint-gcc.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-5.c
index 2b4857fadbd..3d90f7bbd8c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-5.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d --param riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */
#include <stdint-gcc.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-6.c
index 4519a56d213..da9740f536d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-6.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d --param riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */
#include <stdint-gcc.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-7.c
index 0368f1c9a3e..e0a799460f8 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-7.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d --param riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */
#include <stdint-gcc.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-8.c
index e3c19e46678..a70a1a32bdc 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-8.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d --param riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */
#include <stdint-gcc.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary_run-1.c
index 71e5196f9b3..803ec9c1fea 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary_run-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary_run-1.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */
#include "cond_unary-1.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary_run-2.c
index c2d68fca90f..2f3ffe25774 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary_run-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary_run-2.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */
#include "cond_unary-2.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary_run-3.c
index e1e38d9e5f1..97d495a32f9 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary_run-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary_run-3.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */
#include "cond_unary-3.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary_run-4.c
index 2f5b967244d..23be9f9938e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary_run-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary_run-4.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */
#include "cond_unary-4.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary_run-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary_run-5.c
index d507a38e235..95c411873bb 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary_run-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary_run-5.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */
#include "cond_unary-5.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary_run-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary_run-6.c
index fc6cbd2cf5a..776ce1132f4 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary_run-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary_run-6.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */
#include "cond_unary-6.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary_run-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary_run-7.c
index 1825372ffef..ff3bbcea72a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary_run-7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary_run-7.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */
#include "cond_unary-7.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary_run-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary_run-8.c
index 157310ea12d..c5c0aba09f9 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary_run-8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary_run-8.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */
#include "cond_unary-8.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-1.c
index c67593d0bbc..31491f3a503 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-1.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -ffast-math" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -ffast-math" } */
#include <stdint-gcc.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-2.c
index f8fdebbed51..d1997d577e4 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-2.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -ffast-math" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -ffast-math" } */
#include <stdint-gcc.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-3.c
index ef61a4f0393..d02a8e2dbb9 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-3.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -ffast-math" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -ffast-math" } */
#include <stdint-gcc.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-4.c
index 9aa6355f4ca..59ca5355872 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-4.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=scalable" } */
+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable" } */
#include <stdint-gcc.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-5.c
index efbd3d19796..c091ec3bf8b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-5.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -ffast-math" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -ffast-math" } */
#include <stdint-gcc.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-6.c
index 083571c3c3b..f8046967cbc 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-6.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=scalable" } */
+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable" } */
#include <stdint-gcc.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-7.c
index 41017c313a1..4a3f301be49 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-7.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -ffast-math" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -ffast-math" } */
#include <stdint-gcc.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-8.c
index 8aea32dbd99..dfac15656a4 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-8.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -ffast-math" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -ffast-math" } */
#include <stdint-gcc.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-9.c
index 9e322118631..4b431ce4efc 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-9.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-9.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -ffast-math" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -ffast-math" } */
#include <stdint-gcc.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc-1.c
index 47889f3a1cd..a80c3b9eded 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc-1.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv64gcv_zvfh_zvl128b -mabi=lp64d --param riscv-autovec-preference=fixed-vlmax --param riscv-autovec-lmul=m2 -fno-vect-cost-model -ffast-math" } */
+/* { dg-additional-options "-march=rv64gcv_zvfh_zvl128b -mabi=lp64d -mrvv-vector-bits=zvl --param riscv-autovec-lmul=m2 -fno-vect-cost-model -ffast-math" } */
#include <stdint-gcc.h>
#define TEST_TYPE(TYPE1, TYPE2, N) \
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc-2.c
index 662d1351215..c2a207db0e4 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc-2.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv64gcv_zvfh_zvl128b -mabi=lp64d --param riscv-autovec-preference=scalable --param riscv-autovec-lmul=m2 -fno-vect-cost-model -ffast-math" } */
+/* { dg-additional-options "-march=rv64gcv_zvfh_zvl128b -mabi=lp64d -mrvv-vector-bits=scalable --param riscv-autovec-lmul=m2 -fno-vect-cost-model -ffast-math" } */
#include "cond_widen_reduc-1.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc_run-1.c
index e738edeb4fc..9dbecee49d3 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc_run-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc_run-1.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param riscv-autovec-preference=fixed-vlmax --param riscv-autovec-lmul=m2 -fno-vect-cost-model -ffast-math" } */
+/* { dg-additional-options "-mrvv-vector-bits=zvl --param riscv-autovec-lmul=m2 -fno-vect-cost-model -ffast-math" } */
#include "cond_widen_reduc-1.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc_run-2.c
index 60f92cac291..7c319012156 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc_run-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc_run-2.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param riscv-autovec-preference=scalable --param riscv-autovec-lmul=m2 -fno-vect-cost-model -ffast-math" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable --param riscv-autovec-lmul=m2 -fno-vect-cost-model -ffast-math" } */
#include "cond_widen_reduc-2.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/pr111401.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/pr111401.c
index f593db3192a..08d983997e2 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/pr111401.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/pr111401.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param riscv-autovec-preference=scalable -fdump-tree-vect-details" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fdump-tree-vect-details" } */
double
__attribute__ ((noipa))
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vec-narrow-int64-float16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vec-narrow-int64-float16.c
index c24d66ae423..1611ea847a0 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vec-narrow-int64-float16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vec-narrow-int64-float16.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d --param=riscv-autovec-preference=scalable -fdump-tree-vect-details" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable -fdump-tree-vect-details" } */
/* This test ensures that we vectorize the conversion by having the vectorizer
create an intermediate type. */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vec-widen-float16-int64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vec-widen-float16-int64.c
index 3fd1260f743..91bcf2cde81 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vec-widen-float16-int64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vec-widen-float16-int64.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d --param=riscv-autovec-preference=scalable -fno-trapping-math -fdump-tree-vect-details" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable -fno-trapping-math -fdump-tree-vect-details" } */
/* This test ensures that we vectorize the conversion by having the vectorizer
create an intermediate type. */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt-itof-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt-itof-run.c
index 3098ba64a3f..ee822bf582e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt-itof-run.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt-itof-run.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=scalable" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=scalable" } */
#include "vfcvt-itof-template.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt-itof-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt-itof-rv32gcv.c
index dae14423fd3..12ac56b1a82 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt-itof-rv32gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt-itof-rv32gcv.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable" } */
#include "vfcvt-itof-template.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt-itof-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt-itof-rv64gcv.c
index ccb2bb5544d..1cecd1dbbd9 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt-itof-rv64gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt-itof-rv64gcv.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d --param=riscv-autovec-preference=scalable" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable" } */
#include "vfcvt-itof-template.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt-itof-zvfh-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt-itof-zvfh-run.c
index bd85f3f5814..4db500dc53e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt-itof-zvfh-run.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt-itof-zvfh-run.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v && riscv_zvfh } } } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=scalable" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=scalable" } */
#include "vfcvt-itof-template.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt_rtz-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt_rtz-run.c
index 2000cfdc4f8..e5197041caf 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt_rtz-run.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt_rtz-run.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=scalable" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=scalable" } */
#include "vfcvt_rtz-template.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt_rtz-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt_rtz-rv32gcv.c
index 0a79adf3510..9ee22e6f895 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt_rtz-rv32gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt_rtz-rv32gcv.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable" } */
#include "vfcvt_rtz-template.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt_rtz-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt_rtz-rv64gcv.c
index e74984798e6..3cf508381d8 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt_rtz-rv64gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt_rtz-rv64gcv.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d --param=riscv-autovec-preference=scalable" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable" } */
#include "vfcvt_rtz-template.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt_rtz-zvfh-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt_rtz-zvfh-run.c
index 3164fed03fb..a6a58e61681 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt_rtz-zvfh-run.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt_rtz-zvfh-run.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v && riscv_zvfh } } } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=scalable" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=scalable" } */
#include "vfcvt_rtz-template.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-ftoi-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-ftoi-run.c
index 5bec69949e6..64693ac6dde 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-ftoi-run.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-ftoi-run.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=scalable" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=scalable" } */
#include "vfncvt-ftoi-template.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-ftoi-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-ftoi-rv32gcv.c
index 43967af1cd5..8b40c7c219f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-ftoi-rv32gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-ftoi-rv32gcv.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d -fno-trapping-math --param=riscv-autovec-preference=scalable" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d -fno-trapping-math -mrvv-vector-bits=scalable" } */
#include "vfncvt-ftoi-template.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-ftoi-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-ftoi-rv64gcv.c
index d49370bb925..5dec77ea3d6 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-ftoi-rv64gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-ftoi-rv64gcv.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d -fno-trapping-math --param=riscv-autovec-preference=scalable" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d -fno-trapping-math -mrvv-vector-bits=scalable" } */
#include "vfncvt-ftoi-template.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-ftoi-zvfh-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-ftoi-zvfh-run.c
index dbbbb615cc1..ea654d70621 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-ftoi-zvfh-run.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-ftoi-zvfh-run.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v && riscv_zvfh } } } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=scalable" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=scalable" } */
#include "vfncvt-ftoi-template.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-itof-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-itof-run.c
index f516677f38b..e7d013f3761 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-itof-run.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-itof-run.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=scalable" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=scalable" } */
#include "vfncvt-itof-template.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-itof-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-itof-rv32gcv.c
index 73e4644658b..a5bd094b287 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-itof-rv32gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-itof-rv32gcv.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable" } */
#include "vfncvt-itof-template.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-itof-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-itof-rv64gcv.c
index e9d31a70e6a..cdecf9c306a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-itof-rv64gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-itof-rv64gcv.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d --param=riscv-autovec-preference=scalable" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable" } */
#include "vfncvt-itof-template.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-itof-zvfh-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-itof-zvfh-run.c
index 0342d147de0..7a110f0e0d9 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-itof-zvfh-run.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-itof-zvfh-run.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_zvfh && riscv_zfh} } } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=scalable" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=scalable" } */
#include "vfncvt-itof-template.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-run.c
index 41b8781e74d..3ec64d01314 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-run.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-run.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=zvl" } */
#include "vfncvt-template.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-rv32gcv.c
index 10fe75d2754..efdef9816d2 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-rv32gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-rv32gcv.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=zvl" } */
#include "vfncvt-template.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-rv64gcv.c
index fd40fa242e4..da8974c83ae 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-rv64gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-rv64gcv.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=zvl" } */
#include "vfncvt-template.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-zvfh-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-zvfh-run.c
index 6eb9f146704..2cf18cf5e10 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-zvfh-run.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-zvfh-run.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v && riscv_zvfh } } } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=scalable" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=scalable" } */
#include "vfncvt-template.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-ftoi-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-ftoi-run.c
index 333bd7a04dd..11a0a552a8d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-ftoi-run.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-ftoi-run.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=scalable" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=scalable" } */
#include "vfwcvt-ftoi-template.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-ftoi-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-ftoi-rv32gcv.c
index 0ab42af6d70..9581202c01c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-ftoi-rv32gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-ftoi-rv32gcv.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d -fno-trapping-math --param=riscv-autovec-preference=scalable" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d -fno-trapping-math -mrvv-vector-bits=scalable" } */
#include "vfwcvt-ftoi-template.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-ftoi-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-ftoi-rv64gcv.c
index e1a4b631423..7df211d361a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-ftoi-rv64gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-ftoi-rv64gcv.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d -fno-trapping-math --param=riscv-autovec-preference=scalable" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d -fno-trapping-math -mrvv-vector-bits=scalable" } */
#include "vfwcvt-ftoi-template.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-ftoi-zvfh-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-ftoi-zvfh-run.c
index 3d1165400d3..026ef264ef1 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-ftoi-zvfh-run.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-ftoi-zvfh-run.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v && riscv_zvfh } } } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=scalable" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=scalable" } */
#include "vfwcvt-ftoi-template.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-itof-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-itof-run.c
index adf67a8ce58..3f0ea5a6f92 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-itof-run.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-itof-run.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=scalable" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=scalable" } */
#include "vfwcvt-itof-template.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-itof-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-itof-rv32gcv.c
index cf180992c5d..6d2409f1220 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-itof-rv32gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-itof-rv32gcv.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable" } */
#include "vfwcvt-itof-template.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-itof-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-itof-rv64gcv.c
index b1153887bd8..acc36e59b82 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-itof-rv64gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-itof-rv64gcv.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d --param=riscv-autovec-preference=scalable" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable" } */
#include "vfwcvt-itof-template.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-itof-zvfh-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-itof-zvfh-run.c
index 8df59a9a91d..295cb3f6bb6 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-itof-zvfh-run.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-itof-zvfh-run.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v && riscv_zvfh } } } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=scalable" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=scalable" } */
#include "vfwcvt-itof-template.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-run.c
index bf369d6b058..0d9f8348fda 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-run.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-run.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=zvl" } */
#include "vfwcvt-template.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-rv32gcv.c
index 006bdb24c41..3f0a113fe3a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-rv32gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-rv32gcv.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=zvl" } */
#include "vfwcvt-template.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-rv64gcv.c
index 7ec710702c9..d48b6560d1b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-rv64gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-rv64gcv.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=zvl" } */
#include "vfwcvt-template.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-zvfh-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-zvfh-run.c
index 9f2c9835fd6..f4ca1720dff 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-zvfh-run.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-zvfh-run.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v && riscv_zvfh } } } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=scalable" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=scalable" } */
#include "vfwcvt-template.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vncvt-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vncvt-run.c
index 2dfd6eb148e..ac3ce595aac 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vncvt-run.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vncvt-run.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=zvl" } */
#include "vncvt-template.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vncvt-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vncvt-rv32gcv.c
index 2b5aa0051cf..cc3d6245e12 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vncvt-rv32gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vncvt-rv32gcv.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=zvl" } */
#include "vncvt-template.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vncvt-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vncvt-rv64gcv.c
index 29349b33da6..0b43787c13c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vncvt-rv64gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vncvt-rv64gcv.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv -mabi=lp64d -mrvv-vector-bits=zvl" } */
#include "vncvt-template.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vsext-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vsext-run.c
index ed1fa3598f5..c6409f8fb39 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vsext-run.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vsext-run.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=zvl" } */
#include "vsext-template.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vsext-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vsext-rv32gcv.c
index 538216ab9c3..7f40f5f5177 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vsext-rv32gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vsext-rv32gcv.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=zvl" } */
#include "vsext-template.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vsext-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vsext-rv64gcv.c
index 29348cc67e5..833f1da359b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vsext-rv64gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vsext-rv64gcv.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv -mabi=lp64d -mrvv-vector-bits=zvl" } */
#include "vsext-template.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vzext-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vzext-run.c
index 3770f83c35f..89ea3079a37 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vzext-run.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vzext-run.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=zvl" } */
#include "vzext-template.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vzext-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vzext-rv32gcv.c
index 3e92843a5c2..0ed4a14985f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vzext-rv32gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vzext-rv32gcv.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=zvl" } */
#include "vzext-template.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vzext-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vzext-rv64gcv.c
index cee0012d58c..9c60c0f8cae 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vzext-rv64gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vzext-rv64gcv.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv -mabi=lp64d -mrvv-vector-bits=zvl" } */
#include "vzext-template.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/fixed-vlmax-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/fixed-vlmax-1.c
index 61eac38e541..ee5f18c9f8b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/fixed-vlmax-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/fixed-vlmax-1.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -mpreferred-stack-boundary=3 -fno-schedule-insns -fno-schedule-insns2 -O3 --param riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -mpreferred-stack-boundary=3 -fno-schedule-insns -fno-schedule-insns2 -O3 -mrvv-vector-bits=zvl -Wno-psabi" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/fold-min-poly.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/fold-min-poly.c
index 3f524dba868..85917fe46bf 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/fold-min-poly.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/fold-min-poly.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options " -march=rv64gcv_zvl128b -mabi=lp64d -O3 --param riscv-autovec-preference=scalable --param riscv-autovec-lmul=m1" } */
+/* { dg-options " -march=rv64gcv_zvl128b -mabi=lp64d -O3 -mrvv-vector-bits=scalable --param riscv-autovec-lmul=m1" } */
void foo1 (int* restrict a, int* restrict b, int n)
{
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/strided_load-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/strided_load-1.c
index b1e6a17543f..53263d16ae2 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/strided_load-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/strided_load-1.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d -O3 --param riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math -fdump-tree-optimized-details" } */
+/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d -O3 -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math -fdump-tree-optimized-details" } */
#include <stdint-gcc.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/strided_load-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/strided_load-2.c
index 2c9e7dd14a8..6fef474cf8e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/strided_load-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/strided_load-2.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d -O3 --param riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math -fdump-tree-optimized-details" } */
+/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d -O3 -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math -fdump-tree-optimized-details" } */
#include <stdint-gcc.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/strided_store-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/strided_store-1.c
index 3e6a34029b3..ad23ed42129 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/strided_store-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/strided_store-1.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d -O3 --param riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math -fdump-tree-optimized-details" } */
+/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d -O3 -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math -fdump-tree-optimized-details" } */
#include <stdint-gcc.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/strided_store-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/strided_store-2.c
index 6906af17d84..65f3f00b8c2 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/strided_store-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/strided_store-2.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d -O3 --param riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math -fdump-tree-optimized-details" } */
+/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d -O3 -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math -fdump-tree-optimized-details" } */
#include <stdint-gcc.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/madd-split2-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/madd-split2-1.c
index e10a9e9d0f5..4f99a5f87c4 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/madd-split2-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/madd-split2-1.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64d -O3 -fno-cprop-registers -fno-dce --param riscv-autovec-preference=scalable" } */
+/* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64d -O3 -fno-cprop-registers -fno-dce -mrvv-vector-bits=scalable" } */
long
foo (long *__restrict a, long *__restrict b, long n)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/gimple_fold-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/gimple_fold-1.c
index 7021182f83a..cf6d742f98f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/gimple_fold-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/gimple_fold-1.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32d --param riscv-autovec-preference=fixed-vlmax --param riscv-autovec-lmul=m8 -O3 -fdump-tree-optimized-details" } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=zvl --param riscv-autovec-lmul=m8 -O3 -fdump-tree-optimized-details" } */
#include <stdint-gcc.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/live-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/live-1.c
index 15ce74a0c4c..84349fae9db 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/live-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/live-1.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -fno-vect-cost-model --param riscv-autovec-preference=scalable -fdump-tree-optimized-details" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -fno-vect-cost-model -mrvv-vector-bits=scalable -fdump-tree-optimized-details" } */
#include <stdint-gcc.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/live-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/live-2.c
index 69c2a44219a..020d08e9979 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/live-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/live-2.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -fno-vect-cost-model --param riscv-autovec-preference=scalable -fdump-tree-optimized-details" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -fno-vect-cost-model -mrvv-vector-bits=scalable -fdump-tree-optimized-details" } */
#include <stdint-gcc.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/live_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/live_run-1.c
index ecd3219d75c..06f3138b883 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/live_run-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/live_run-1.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param riscv-autovec-preference=scalable" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable" } */
#include "live-1.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/live_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/live_run-2.c
index 3724dac1aee..c25e8f83a14 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/live_run-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/live_run-2.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param riscv-autovec-preference=scalable" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable" } */
#include "live-2.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup-1.c
index 69cc3be78f7..3d8f6315e07 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup-1.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=zvl" } */
#include "multiple_rgroup-1.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup-2.c
index d1c41907547..8a485c869cc 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup-2.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=zvl" } */
#include "multiple_rgroup-2.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup-3.c
index 9579749c285..0efa7e7f67e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup-3.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=zvl" } */
#include <stdint-gcc.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup-4.c
index e87961e49ac..b572557bbd9 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup-4.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=zvl" } */
#include <stdint-gcc.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-1.c
index 43521408909..7ff46e4b07c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-1.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-additional-options "-mrvv-vector-bits=zvl" } */
#include "multiple_rgroup-1.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-2.c
index 13602c411fd..04789ff137e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-2.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-additional-options "-mrvv-vector-bits=zvl" } */
#include "multiple_rgroup-2.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-3.c
index 292a9af6b4d..f70fb2af7a5 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-3.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-additional-options "-mrvv-vector-bits=zvl" } */
#include "multiple_rgroup-3.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-4.c
index a7641612588..fda6bf70fbe 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-4.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-additional-options "-mrvv-vector-bits=zvl" } */
#include "multiple_rgroup-4.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_zbb.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_zbb.c
index 15178a2c848..a851229daac 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_zbb.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_zbb.c
@@ -1,5 +1,5 @@
/* { dg-do compile } *.
-/* { dg-options "-march=rv64gcv_zbb -mabi=lp64d -O2 --param riscv-autovec-preference=fixed-vlmax -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-march=rv64gcv_zbb -mabi=lp64d -O2 -mrvv-vector-bits=zvl -fno-schedule-insns -fno-schedule-insns2" } */
#include <stdint-gcc.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/select_vl-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/select_vl-1.c
index e27090d79cf..cac82dccdfb 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/select_vl-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/select_vl-1.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param riscv-autovec-preference=scalable -fno-vect-cost-model -fno-tree-loop-distribute-patterns -fdump-tree-optimized-details" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -fno-tree-loop-distribute-patterns -fdump-tree-optimized-details" } */
#include <stdint-gcc.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/select_vl-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/select_vl-2.c
index ca88d42cdf4..ce50d80e0bc 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/select_vl-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/select_vl-2.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d --param riscv-autovec-preference=scalable -fno-schedule-insns --param riscv-autovec-lmul=m1 -O3 -ftree-vectorize" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -mrvv-vector-bits=scalable -fno-schedule-insns --param riscv-autovec-lmul=m1 -O3 -ftree-vectorize" } */
/* { dg-final { check-function-bodies "**" "" } } */
#include <stdint-gcc.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/single_rgroup-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/single_rgroup-1.c
index 10cc698a7cd..9d0286916f5 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/single_rgroup-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/single_rgroup-1.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param riscv-autovec-preference=scalable -fno-vect-cost-model -fno-tree-loop-distribute-patterns -fdump-tree-vect-details" } */
+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -fno-tree-loop-distribute-patterns -fdump-tree-vect-details" } */
#include "single_rgroup-1.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/single_rgroup-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/single_rgroup-2.c
index 24490dc6bc7..1b2f1f821c7 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/single_rgroup-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/single_rgroup-2.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfhmin -mabi=ilp32d --param riscv-autovec-preference=fixed-vlmax -fdump-tree-vect-details" } */
+/* { dg-additional-options "-march=rv32gcv_zvfhmin -mabi=ilp32d -mrvv-vector-bits=zvl -fdump-tree-vect-details" } */
#include "single_rgroup-2.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/single_rgroup-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/single_rgroup-3.c
index 9cbae13de06..f7133b3a891 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/single_rgroup-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/single_rgroup-3.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfhmin -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-vect-details" } */
+/* { dg-additional-options "-march=rv32gcv_zvfhmin -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-vect-details" } */
#include "single_rgroup-3.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/single_rgroup_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/single_rgroup_run-1.c
index 52d21b2505e..103a12eec26 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/single_rgroup_run-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/single_rgroup_run-1.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "-fno-vect-cost-model -fno-tree-loop-distribute-patterns --param riscv-autovec-preference=scalable" } */
+/* { dg-additional-options "-fno-vect-cost-model -fno-tree-loop-distribute-patterns -mrvv-vector-bits=scalable" } */
#include "single_rgroup-1.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/single_rgroup_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/single_rgroup_run-2.c
index d753d56e97d..8971f48d2fa 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/single_rgroup_run-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/single_rgroup_run-2.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-additional-options "-mrvv-vector-bits=zvl" } */
#include "single_rgroup-2.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/single_rgroup_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/single_rgroup_run-3.c
index 04edbc712bb..79cb2b6af3a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/single_rgroup_run-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/single_rgroup_run-3.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param riscv-autovec-preference=scalable" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable" } */
#include "single_rgroup-3.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-1.c
index 0a1d1f72e6b..fae1ab590a3 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-1.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-optimized-details" } */
+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-optimized-details" } */
#include <stdint-gcc.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-10.c
index c5215611e53..ed371949824 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-10.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-10.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param riscv-autovec-preference=scalable -fno-vect-cost-model -fdump-tree-optimized-details" } */
+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -fdump-tree-optimized-details" } */
#include <stdint-gcc.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-11.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-11.c
index ccb5ab6831d..32def0b8dde 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-11.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-11.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param riscv-autovec-preference=scalable -fno-vect-cost-model -fdump-tree-optimized-details" } */
+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -fdump-tree-optimized-details" } */
#include <stdint-gcc.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-12.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-12.c
index 03529f4643a..41dc5746a98 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-12.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-12.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */
#include <stdint-gcc.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-13.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-13.c
index 807cb49a4c5..bed0e1a8ca3 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-13.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-13.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */
#include <stdint-gcc.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-14.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-14.c
index e0d089e5434..d75f461279f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-14.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-14.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */
#include <stdint-gcc.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-15.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-15.c
index 731b028b17a..7057e0dd588 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-15.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-15.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */
#include <stdint-gcc.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-16.c
index 05220c32c5d..02fb365f528 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-16.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-optimized-details" } */
+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-optimized-details" } */
#include <stdint-gcc.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-17.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-17.c
index 50d06d501ba..3adec12a60c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-17.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-17.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param riscv-autovec-preference=scalable -fno-vect-cost-model -fdump-tree-optimized-details" } */
+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -fdump-tree-optimized-details" } */
#include <stdint-gcc.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-18.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-18.c
index 06bf10e8c67..8f1a7e12c1f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-18.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-18.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-optimized-details -fno-vect-cost-model" } */
+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-optimized-details -fno-vect-cost-model" } */
#include <stdint-gcc.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-19.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-19.c
index dda2075a59b..2fa6168ca9c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-19.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-19.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-optimized-details -fno-vect-cost-model" } */
+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-optimized-details -fno-vect-cost-model" } */
#include <stdint-gcc.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-2.c
index 5605b1ba684..08ac776b4fe 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-2.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param riscv-autovec-preference=scalable -fno-vect-cost-model -fdump-tree-optimized-details" } */
+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -fdump-tree-optimized-details" } */
#include <stdint-gcc.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-3.c
index 5e64231b37d..88598e67626 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-3.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-optimized-details" } */
+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-optimized-details" } */
#include <stdint-gcc.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-4.c
index e18ebd3ae2f..7543ecad523 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-4.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param riscv-autovec-preference=scalable -fno-vect-cost-model -fdump-tree-optimized-details" } */
+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -fdump-tree-optimized-details" } */
#include <stdint-gcc.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-5.c
index c78b3709078..eaa580f8bb6 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-5.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-optimized-details" } */
+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-optimized-details" } */
#include <stdint-gcc.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-6.c
index 9fca6bdf5d0..324cae01069 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-6.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-optimized-details -fno-vect-cost-model" } */
+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-optimized-details -fno-vect-cost-model" } */
#include <stdint-gcc.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-7.c
index 3dd744b586e..fedbf29a23e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-7.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-optimized-details" } */
+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-optimized-details" } */
#include <stdint-gcc.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-8.c
index cf2fd1d656f..42c69239f08 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-8.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param riscv-autovec-preference=scalable -fno-vect-cost-model -fdump-tree-optimized-details" } */
+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -fdump-tree-optimized-details" } */
#include <stdint-gcc.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-9.c
index 1b99ffd4ffa..d7599bbb299 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-9.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-9.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv64gcv -mabi=lp64d --param riscv-autovec-preference=scalable -fno-vect-cost-model -fdump-tree-optimized-details" } */
+/* { dg-additional-options "-march=rv64gcv -mabi=lp64d -mrvv-vector-bits=scalable -fno-vect-cost-model -fdump-tree-optimized-details" } */
#include <stdint-gcc.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-1.c
index cb07c965254..715bd72d46f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-1.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param riscv-autovec-preference=scalable" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable" } */
#include "slp-1.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-10.c
index b7ba21c5ea9..b13828a61f0 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-10.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-10.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */
#include "slp-10.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-11.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-11.c
index 0f8bdad7e02..3c330d066b8 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-11.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-11.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */
#include "slp-11.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-12.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-12.c
index 75ec4193449..b2a853c754a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-12.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-12.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */
#include "slp-12.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-13.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-13.c
index 555a73fd976..b38f8ebd49f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-13.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-13.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */
#include "slp-13.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-14.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-14.c
index 0219528ff75..680240e8c5b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-14.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-14.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */
#include "slp-14.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-15.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-15.c
index 6d3218fc22b..76ebe066210 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-15.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-15.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */
#include "slp-15.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-16.c
index 490003e6e8e..c0a3b185be2 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-16.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param riscv-autovec-preference=scalable" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable" } */
#include "slp-16.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-17.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-17.c
index 1ea6a27505c..473ae6f3ad1 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-17.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-17.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param riscv-autovec-preference=scalable" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable" } */
#include "slp-17.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-18.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-18.c
index 6685e036904..a0f9cce84cd 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-18.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-18.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param riscv-autovec-preference=scalable" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable" } */
#include "slp-18.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-19.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-19.c
index 58de15ba924..7649a918a2f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-19.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-19.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param riscv-autovec-preference=scalable" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable" } */
#include "slp-19.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-2.c
index d3ee634e262..28c1ec4d9c4 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-2.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param riscv-autovec-preference=scalable" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable" } */
#include "slp-2.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-3.c
index d4dc241d86e..a59579501b8 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-3.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param riscv-autovec-preference=scalable" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable" } */
#include "slp-3.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-4.c
index 5a4b7680fb1..fea844daeae 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-4.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param riscv-autovec-preference=scalable" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable" } */
#include "slp-4.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-5.c
index 8084657da44..79747748b8e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-5.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param riscv-autovec-preference=scalable" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable" } */
#include "slp-5.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-6.c
index 881dc796c8f..46df36f1209 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-6.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param riscv-autovec-preference=scalable" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable" } */
#include "slp-6.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-7.c
index 886b9c4e959..269be8c1c11 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-7.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param riscv-autovec-preference=scalable" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable" } */
#include "slp-7.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-8.c
index 7e41733268d..cc336ba774c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-8.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */
#include "slp-8.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-9.c
index c0105644e26..ee2d2b37da0 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-9.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-9.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */
#include "slp-9.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/post-ra-avl.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/post-ra-avl.c
index bff6dcb1c38..ceb25240310 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/post-ra-avl.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/post-ra-avl.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-O3 -march=rv64gcv -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-options "-O3 -march=rv64gcv -mabi=lp64d -mrvv-vector-bits=zvl" } */
int a, b, c, e;
short d[7][7] = {};
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr110950.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr110950.c
index 17dd4397341..49d96800f81 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr110950.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr110950.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d --param=riscv-autovec-preference=scalable -Ofast -fno-vect-cost-model" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -mrvv-vector-bits=scalable -Ofast -fno-vect-cost-model" } */
int a;
void b() {
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr110964.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr110964.c
index cf2d1fb5f1d..eee205aff1b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr110964.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr110964.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d --param=riscv-autovec-preference=scalable -Ofast" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -mrvv-vector-bits=scalable -Ofast" } */
int *a;
long b, c;
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr110989.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr110989.c
index 6e163a55c56..5922279b9e2 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr110989.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr110989.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d --param=riscv-autovec-preference=scalable -Ofast -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -mrvv-vector-bits=scalable -Ofast -fno-schedule-insns -fno-schedule-insns2" } */
int a, b, c;
double *d;
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr111232.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr111232.c
index edad1402154..3875eead4e4 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr111232.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr111232.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d --param=riscv-autovec-preference=scalable -Ofast -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -mrvv-vector-bits=scalable -Ofast -fno-schedule-insns -fno-schedule-insns2" } */
#include <stdint-gcc.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr111295.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr111295.c
index fa20a21338a..7a0b67118bc 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr111295.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr111295.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -Ofast -ftree-vectorize --param=riscv-autovec-preference=scalable -Wno-implicit-function-declaration" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -Ofast -ftree-vectorize -mrvv-vector-bits=scalable -Wno-implicit-function-declaration" } */
#include <stdbool.h>
int a, b, c, e, f, g, h, i, j, k;
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr111313.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr111313.c
index a4f8c37f95d..4a9f9469fbc 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr111313.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr111313.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d --param=riscv-autovec-preference=scalable -O3 -fno-schedule-insns -fno-schedule-insns2 -fno-vect-cost-model" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -mrvv-vector-bits=scalable -O3 -fno-schedule-insns -fno-schedule-insns2 -fno-vect-cost-model" } */
#define K 32
short in[2*K][K];
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112326.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112326.c
index 2ad50139cb2..1a853f6c3fb 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112326.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112326.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-vect-cost-model -mrvv-vector-bits=zvl" } */
void
f (int *__restrict y, int *__restrict x, int *__restrict z, int n)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112552.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112552.c
index 4ef76cd3506..7ee4ad3e384 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112552.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112552.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-O3 -march=rv64gcv -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax -w -Wno-incompatible-pointer-types" } */
+/* { dg-options "-O3 -march=rv64gcv -mabi=lp64d -mrvv-vector-bits=zvl -w -Wno-incompatible-pointer-types" } */
int a, c, d;
void (*b)();
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112554.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112554.c
index 4afa7c2b15c..05aae279c85 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112554.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112554.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 --param=riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -mrvv-vector-bits=zvl" } */
int a;
void b() {
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112561.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112561.c
index 25e61fa12c0..01945b29680 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112561.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112561.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-options "-O3 -ftree-vectorize --param=riscv-autovec-preference=fixed-vlmax -mcmodel=medlow" } */
+/* { dg-options "-O3 -ftree-vectorize -mrvv-vector-bits=zvl -mcmodel=medlow" } */
int printf(char *, ...);
int a, b, c, e;
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112597-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112597-1.c
index 73aa3ee2f51..fc67bb47828 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112597-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112597-1.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv32gcv_zvl256b -mabi=ilp32d -O3 --param riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-options "-march=rv32gcv_zvl256b -mabi=ilp32d -O3 -mrvv-vector-bits=zvl" } */
#include <stdint-gcc.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112599-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112599-1.c
index 911b6922b4a..441736caf48 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112599-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112599-1.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zfh_zvl1024b -mabi=lp64d -O3 --param=riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-options "-march=rv64gcv_zvfh_zfh_zvl1024b -mabi=lp64d -O3 -mrvv-vector-bits=zvl" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112599-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112599-3.c
index 0954fe2b2c1..8721d35cc4e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112599-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112599-3.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zfh_zvl1024b -mabi=lp64d -O3 --param=riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-options "-march=rv64gcv_zvfh_zfh_zvl1024b -mabi=lp64d -O3 -mrvv-vector-bits=zvl" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112694-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112694-1.c
index f50df658a9a..3743ac82510 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112694-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112694-1.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv32gc_zve64d_zvfh_zfh -mabi=ilp32d -mcmodel=medany -fdiagnostics-plain-output -ftree-vectorize -O2 --param riscv-autovec-lmul=m1 -std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */
+/* { dg-options "-march=rv32gc_zve64d_zvfh_zfh -mabi=ilp32d -mcmodel=medany -fdiagnostics-plain-output -ftree-vectorize -O2 --param riscv-autovec-lmul=m1 -std=c99 -fno-vect-cost-model -mrvv-vector-bits=zvl -ffast-math" } */
#include <stdint-gcc.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112854.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112854.c
index 8f7f13f9dc1..d0c6744a3f1 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112854.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112854.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv32gcv_zvl1024b -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-options "-march=rv32gcv_zvl1024b -mabi=ilp32d -mrvv-vector-bits=zvl" } */
short a, b;
void c(int d) {
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112872.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112872.c
index 5c1d2188e12..61c9f01339f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112872.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112872.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvl1024b -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax -O3" } */
+/* { dg-options "-march=rv64gcv_zvl1024b -mabi=lp64d -mrvv-vector-bits=zvl -O3" } */
int a, c;
char b;
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112999.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112999.c
index c049c5a0386..a1244c1317a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112999.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112999.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvl512b -mabi=lp64d --param=riscv-autovec-lmul=m8 --param=riscv-autovec-preference=fixed-vlmax -O3 -fno-vect-cost-model -fno-tree-loop-distribute-patterns" } */
+/* { dg-options "-march=rv64gcv_zvl512b -mabi=lp64d --param=riscv-autovec-lmul=m8 -mrvv-vector-bits=zvl -O3 -fno-vect-cost-model -fno-tree-loop-distribute-patterns" } */
int a[1024];
int b[1024];
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr113393-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr113393-1.c
index 57c5cff637b..d65fe78b942 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr113393-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr113393-1.c
@@ -1,5 +1,5 @@
/* { dg-do run } */
-/* { dg-options "-O3 --param=riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-options "-O3 -mrvv-vector-bits=zvl" } */
/* { dg-require-effective-target riscv_v } */
#define SIZE 128
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr113393-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr113393-2.c
index c36a16d91ac..2d203ea95d4 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr113393-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr113393-2.c
@@ -1,5 +1,5 @@
/* { dg-do run } */
-/* { dg-options "-O3 --param=riscv-autovec-preference=fixed-vlmax --param=riscv-autovec-lmul=m2" } */
+/* { dg-options "-O3 -mrvv-vector-bits=zvl --param=riscv-autovec-lmul=m2" } */
/* { dg-require-effective-target riscv_v } */
__attribute__((noinline, noclone)) static int
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr113393-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr113393-3.c
index 063cf854329..b34b528d6d0 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr113393-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr113393-3.c
@@ -1,5 +1,5 @@
/* { dg-do run } */
-/* { dg-options "-O3 --param=riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-options "-O3 -mrvv-vector-bits=zvl" } */
/* { dg-require-effective-target riscv_v } */
#include "pr113393-2.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-1.c
index 6c86f29e7d4..10787310c52 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-1.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -fno-vect-cost-model -fdump-tree-optimized" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=zvl -fno-vect-cost-model -fdump-tree-optimized" } */
#define N 32
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-10.c
index c5fe5204763..a0bee1cb518 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-10.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-10.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -fdump-tree-optimized" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -fdump-tree-optimized" } */
#include "extract_last-9.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-11.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-11.c
index 85547c8bd76..b3a1ecbad92 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-11.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-11.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -fno-vect-cost-model -fdump-tree-optimized" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=zvl -fno-vect-cost-model -fdump-tree-optimized" } */
#define N 32
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-12.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-12.c
index c165cb33ce4..29ed2fa3373 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-12.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-12.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -fdump-tree-optimized" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -fdump-tree-optimized" } */
#include "extract_last-11.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-13.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-13.c
index 9a04af6c266..779d0513c39 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-13.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-13.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -fno-vect-cost-model -fdump-tree-optimized" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=zvl -fno-vect-cost-model -fdump-tree-optimized" } */
#define TYPE double
#include "extract_last-11.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-14.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-14.c
index 88f8a4c056a..dfebfa5ea7e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-14.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-14.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -fdump-tree-optimized" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -fdump-tree-optimized" } */
#include "extract_last-13.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-2.c
index b1eea0db0cd..f572dd85907 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-2.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -fdump-tree-optimized" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -fdump-tree-optimized" } */
#include "extract_last-1.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-3.c
index 2c94ef58a47..73d99b4b622 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-3.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -fno-vect-cost-model -fdump-tree-optimized" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=zvl -fno-vect-cost-model -fdump-tree-optimized" } */
#include <stdint-gcc.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-4.c
index a9ac667edd3..6021a9ee1ad 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-4.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -fdump-tree-optimized" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -fdump-tree-optimized" } */
#include "extract_last-3.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-5.c
index dc7fa639786..6f2d1c4296e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-5.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -fno-vect-cost-model -fdump-tree-optimized" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=zvl -fno-vect-cost-model -fdump-tree-optimized" } */
#define TYPE uint8_t
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-6.c
index 4e434a1813d..8bb262e5960 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-6.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -fdump-tree-optimized" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -fdump-tree-optimized" } */
#include "extract_last-5.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-7.c
index e75e9b21ed3..927d758a38a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-7.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -fno-vect-cost-model -fdump-tree-optimized" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=zvl -fno-vect-cost-model -fdump-tree-optimized" } */
#define TYPE int16_t
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-8.c
index a37eb26f5a4..3fc2580b4f0 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-8.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -fdump-tree-optimized" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -fdump-tree-optimized" } */
#include "extract_last-7.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-9.c
index c7ae0d747cc..c5899d2454d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-9.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-9.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -fno-vect-cost-model -fdump-tree-optimized" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=zvl -fno-vect-cost-model -fdump-tree-optimized" } */
#define TYPE uint64_t
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-1.c
index 741531039b6..407db8434a3 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-1.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=fixed-vlmax -fno-vect-cost-model" } */
+/* { dg-additional-options "-mrvv-vector-bits=zvl -fno-vect-cost-model" } */
#include "extract_last-1.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-10.c
index 367fa232c7e..3df4bbdbfa3 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-10.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-10.c
@@ -1,4 +1,4 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */
#include "extract_last_run-9.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-11.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-11.c
index cff23b5333e..7ac371ee521 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-11.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-11.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=fixed-vlmax -fno-vect-cost-model" } */
+/* { dg-additional-options "-mrvv-vector-bits=zvl -fno-vect-cost-model" } */
#include "extract_last-11.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-12.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-12.c
index fa05d111401..77aa1201c49 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-12.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-12.c
@@ -1,4 +1,4 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */
#include "extract_last_run-11.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-13.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-13.c
index 90a0ff5657a..42e28f9e388 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-13.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-13.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=fixed-vlmax -fno-vect-cost-model" } */
+/* { dg-additional-options "-mrvv-vector-bits=zvl -fno-vect-cost-model" } */
#include "extract_last-13.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-14.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-14.c
index 77ef98304e0..080450e29c9 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-14.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-14.c
@@ -1,4 +1,4 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */
#include "extract_last_run-13.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-2.c
index e969f100fa7..6985b9a5bb6 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-2.c
@@ -1,4 +1,4 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */
#include "extract_last_run-1.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-3.c
index 6433f108773..007e645af85 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-3.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=fixed-vlmax -fno-vect-cost-model" } */
+/* { dg-additional-options "-mrvv-vector-bits=zvl -fno-vect-cost-model" } */
#include "extract_last-3.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-4.c
index ad620c2640d..4a8aa026ef8 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-4.c
@@ -1,4 +1,4 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */
#include "extract_last_run-3.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-5.c
index 1d984b1da19..8383cfb0633 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-5.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=fixed-vlmax -fno-vect-cost-model" } */
+/* { dg-additional-options "-mrvv-vector-bits=zvl -fno-vect-cost-model" } */
#include "extract_last-5.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-6.c
index 03391023256..53a7df0e8e7 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-6.c
@@ -1,4 +1,4 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */
#include "extract_last_run-5.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-7.c
index 2f078e2b9a7..1cfdf7a7e7c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-7.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=fixed-vlmax -fno-vect-cost-model" } */
+/* { dg-additional-options "-mrvv-vector-bits=zvl -fno-vect-cost-model" } */
#include "extract_last-7.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-8.c
index eac1b5315c6..a577712c38a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-8.c
@@ -1,4 +1,4 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */
#include "extract_last_run-7.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-9.c
index d23fe74eafc..6318033d4a6 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-9.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-9.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=fixed-vlmax -fno-vect-cost-model" } */
+/* { dg-additional-options "-mrvv-vector-bits=zvl -fno-vect-cost-model" } */
#include "extract_last-9.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-1.c
index 0d543af13ca..82a5c15fb47 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-1.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -ffast-math -fno-vect-cost-model" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -ffast-math -fno-vect-cost-model" } */
#include <stdint-gcc.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-10.c
index be339bdd550..645a7607905 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-10.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-10.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable --param vect-epilogues-nomask=0 -fno-signaling-nans" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable --param vect-epilogues-nomask=0 -fno-signaling-nans" } */
#include <stdint-gcc.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-2.c
index 136a8a378bf..4af592150a2 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-2.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -ffast-math -fno-vect-cost-model" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -ffast-math -fno-vect-cost-model" } */
#include <stdint-gcc.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-3.c
index c3638344f80..d882e362d62 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-3.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=scalable -ffast-math -fno-vect-cost-model" } */
+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable -ffast-math -fno-vect-cost-model" } */
#include <stdint-gcc.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-4.c
index f00a12826c6..57f47eb3030 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-4.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=scalable -ffast-math -fno-vect-cost-model" } */
+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable -ffast-math -fno-vect-cost-model" } */
#include <stdint-gcc.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-5.c
index e973041f166..0af893d9c4c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-5.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -ffast-math -fno-vect-cost-model" } */
+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=zvl -ffast-math -fno-vect-cost-model" } */
#include <stdint-gcc.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-6.c
index 30961f0cfc5..cc44a06174f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-6.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=scalable -ffast-math -fno-vect-cost-model -fdump-tree-optimized-details" } */
+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable -ffast-math -fno-vect-cost-model -fdump-tree-optimized-details" } */
#include "reduc-5.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-7.c
index e2e65be498b..d91382c5772 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-7.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=scalable -ffast-math -fno-vect-cost-model -fdump-tree-optimized-details" } */
+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable -ffast-math -fno-vect-cost-model -fdump-tree-optimized-details" } */
void __attribute__((noipa))
add_loop (unsigned int *x, int n, unsigned int *res)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-8.c
index 4cbcccdee58..fe47aa3648d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-8.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=scalable -ffast-math -fno-vect-cost-model -fdump-tree-optimized-details" } */
+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable -ffast-math -fno-vect-cost-model -fdump-tree-optimized-details" } */
int __attribute__((noipa))
add_loop (int *x, int n, int res)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-9.c
index 68105616f15..6630d302721 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-9.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-9.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=scalable -ffast-math -fno-vect-cost-model -fdump-tree-optimized-details" } */
+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable -ffast-math -fno-vect-cost-model -fdump-tree-optimized-details" } */
float __attribute__((noipa))
add_loop (float *x, int n, float res)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_call-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_call-1.c
index 1a3ca9cdf11..d736a894ca3 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_call-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_call-1.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */
double foo (double *a, double *b, double *c)
{
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_call-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_call-2.c
index 17a6b6f27fd..55cb6eb41da 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_call-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_call-2.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */
// PR113249
/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_call-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_call-3.c
index 91004e7760f..0aa66abb2d8 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_call-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_call-3.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -fno-vect-cost-model" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=zvl -fno-vect-cost-model" } */
#include "reduc_call-1.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_call-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_call-4.c
index 83beabeff97..1a99df6adf6 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_call-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_call-4.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -fno-vect-cost-model -ffast-math" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=zvl -fno-vect-cost-model -ffast-math" } */
#include "reduc_call-1.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_call-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_call-5.c
index 3523c0f5cd5..3222f2049d9 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_call-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_call-5.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */
double
foo (double *restrict r, const double *restrict a, const double *restrict b,
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-1.c
index f52af7aa789..37d669b3623 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-1.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math -fno-vect-cost-model" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math -fno-vect-cost-model" } */
#include "reduc-1.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-10.c
index 6dc372f5fb6..2ff247df626 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-10.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-10.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-signaling-nans" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-signaling-nans" } */
#include <math.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-2.c
index 36ba4b19526..511dab8fdc6 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-2.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable" } */
#include "reduc-2.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-3.c
index dceb88e3050..bf6b8a21101 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-3.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math -fno-vect-cost-model" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math -fno-vect-cost-model" } */
#include "reduc-3.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-4.c
index 772003a4559..591b23c794a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-4.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math -fno-vect-cost-model" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math -fno-vect-cost-model" } */
#include "reduc-4.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-5.c
index c47e3fc9104..ee1c25e210a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-5.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=fixed-vlmax -ffast-math -fno-vect-cost-model" } */
+/* { dg-additional-options "-mrvv-vector-bits=zvl -ffast-math -fno-vect-cost-model" } */
#define N 0x1100
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-6.c
index ec526c00b7b..d98c2a4fcf8 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-6.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math -fno-vect-cost-model" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math -fno-vect-cost-model" } */
#define N 0x1100
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-7.c
index c9ffd8cffd8..0ace3a769a4 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-7.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math -fno-vect-cost-model" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math -fno-vect-cost-model" } */
#define N 0x1100
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-8.c
index 29200df8d9a..7726b46f652 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-8.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math -fno-vect-cost-model" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math -fno-vect-cost-model" } */
#define N 0x1100
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_strict-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_strict-1.c
index c293e9ae746..5146b8692e1 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_strict-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_strict-1.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */
#include <stdint-gcc.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_strict-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_strict-2.c
index 2e1e7ab674d..fc173d6f24c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_strict-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_strict-2.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */
#define NUM_ELEMS(TYPE) ((int) (5 * (256 / sizeof (TYPE)) + 3))
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_strict-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_strict-3.c
index f559d40e60f..e259f3e15e3 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_strict-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_strict-3.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */
double mat[100][2];
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_strict-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_strict-4.c
index 428d371d9cf..94f9670f4de 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_strict-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_strict-4.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */
double mat[100][8];
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_strict-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_strict-5.c
index 24add2291f1..e826118339f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_strict-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_strict-5.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */
double mat[100][12];
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_strict-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_strict-6.c
index c1567b067ba..607d8beee7e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_strict-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_strict-6.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -fdump-tree-vect-details" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -fdump-tree-vect-details" } */
float
double_reduc (float (*i)[16])
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_strict-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_strict-7.c
index f742a824bb2..f55088f9d59 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_strict-7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_strict-7.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -fdump-tree-vect-details" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -fdump-tree-vect-details" } */
float
double_reduc (float *i, float *j)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_strict_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_strict_run-1.c
index 74b989da941..d22a3a26b78 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_strict_run-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_strict_run-1.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */
#include "reduc_strict-1.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_strict_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_strict_run-2.c
index 340d56bfa76..59e8ab061aa 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_strict_run-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_strict_run-2.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */
#include "reduc_strict-2.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_zvfh-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_zvfh-10.c
index b3bba249c04..272b459e5a0 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_zvfh-10.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_zvfh-10.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable --param vect-epilogues-nomask=0 -fno-signaling-nans" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable --param vect-epilogues-nomask=0 -fno-signaling-nans" } */
#include <stdint-gcc.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_zvfh_run-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_zvfh_run-10.c
index ab047d7077d..fb77955435d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_zvfh_run-10.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_zvfh_run-10.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_zvfh && riscv_zfh } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-signaling-nans" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-signaling-nans" } */
#include <math.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/scalable-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/scalable-1.c
index 3c03a87377d..3ae1fc6d5da 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/scalable-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/scalable-1.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv32gc_zve64d -mabi=ilp32 -O3 -fno-vect-cost-model --param=riscv-autovec-preference=scalable -fdump-tree-vect-details" } */
+/* { dg-options "-march=rv32gc_zve64d -mabi=ilp32 -O3 -fno-vect-cost-model -mrvv-vector-bits=scalable -fdump-tree-vect-details" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/series-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/series-1.c
index 1c697228e9b..43da34eb4e3 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/series-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/series-1.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32d --param riscv-autovec-preference=fixed-vlmax --param riscv-autovec-lmul=m4" } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=zvl --param riscv-autovec-lmul=m4" } */
#include <stdint-gcc.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/series_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/series_run-1.c
index 2a9ffbc4b10..b318364fa35 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/series_run-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/series_run-1.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-options "--param riscv-autovec-preference=fixed-vlmax --param riscv-autovec-lmul=m4" } */
+/* { dg-options "-mrvv-vector-bits=zvl --param riscv-autovec-lmul=m4" } */
#include "series-1.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/slp-mask-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/slp-mask-1.c
index ee1baa58d63..d82a673d670 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/slp-mask-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/slp-mask-1.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-std=gnu99 -O3 -march=rv64gcv -mabi=lp64d --param=riscv-autovec-preference=scalable -fdump-tree-slp-details" } */
+/* { dg-additional-options "-std=gnu99 -O3 -march=rv64gcv -mabi=lp64d -mrvv-vector-bits=scalable -fdump-tree-slp-details" } */
void
__attribute__ ((noipa))
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/slp-mask-run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/slp-mask-run-1.c
index b7d86c6fbb5..5b0e541545a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/slp-mask-run-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/slp-mask-run-1.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "-std=gnu99 -O3 --param=riscv-autovec-preference=scalable" } */
+/* { dg-additional-options "-std=gnu99 -O3 -mrvv-vector-bits=scalable" } */
#include <malloc.h>
#include <stdio.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load-1.c
index e5dc10aea88..f8c9f83beed 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load-1.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */
#include <stdint-gcc.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load-2.c
index 9d61a85267a..8426bc33c1b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load-2.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */
#include <stdint-gcc.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load-3.c
index a686236793a..581a2dd690a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load-3.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */
#include <stdint-gcc.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load-4.c
index e3c48df5d3b..4bb06a2a0ba 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load-4.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */
#include <stdint-gcc.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load-5.c
index 81f1a7a5ef4..87502f37154 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load-5.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */
#include <stdint-gcc.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load-6.c
index 911af2a853d..c6085fd7dbf 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load-6.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */
#include <stdint-gcc.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load-7.c
index 112facee5ad..042dec489be 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load-7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load-7.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */
#include <stdint-gcc.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-1.c
index cf29d647bca..23b85f137aa 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-1.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */
#include "mask_struct_load-1.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-2.c
index c8c8742b7f6..fde20063b1a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-2.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */
#include "mask_struct_load-2.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-3.c
index 5a6a4deb251..fddc038d242 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-3.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */
#include "mask_struct_load-3.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-4.c
index c6c2b6bf5d8..8a476dd7dae 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-4.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */
#include "mask_struct_load-4.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-5.c
index aa2642a1953..4ef9d939ada 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-5.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */
#include "mask_struct_load-5.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-6.c
index eeecb0305b5..67bbdfe147b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-6.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */
#include "mask_struct_load-6.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-7.c
index 1153362250e..72247bbbbe2 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-7.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */
#include "mask_struct_load-7.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store-1.c
index 6df5f08dbc0..79c97a20219 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store-1.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */
#include <stdint-gcc.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store-2.c
index 532b4580b20..f6fe53accf4 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store-2.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */
#include <stdint-gcc.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store-3.c
index 92ed2361e37..05851d00dbe 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store-3.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */
#include <stdint-gcc.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store-4.c
index 4a4048f6921..ee84d132358 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store-4.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */
#include <stdint-gcc.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store-5.c
index eca8d5aa003..6bde96d035e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store-5.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */
#include <stdint-gcc.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store-6.c
index 3cce1620930..cec7e30f73d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store-6.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */
#include <stdint-gcc.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store-7.c
index 9d0073bcf0e..49f5cb68343 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store-7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store-7.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */
#include <stdint-gcc.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-1.c
index d4e9895beeb..a700519dc28 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-1.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */
#include "mask_struct_store-1.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-2.c
index 02a28fa5b1b..9e5a4067ecc 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-2.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */
#include "mask_struct_store-2.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-3.c
index c07df7e0433..ce87627d204 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-3.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */
#include "mask_struct_store-3.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-4.c
index 4c1314b52e6..c105abcf289 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-4.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */
#include "mask_struct_store-4.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-5.c
index 51528757661..a695259f4fd 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-5.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */
#include "mask_struct_store-5.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-6.c
index 3b0419103ad..1a29b46e114 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-6.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */
#include "mask_struct_store-6.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-7.c
index 2ffe9434eb2..c94f1b09069 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-7.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */
#include "mask_struct_store-7.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-1.c
index f49d92d7430..b4673780a6b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-1.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -funroll-all-loops -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=zvl -funroll-all-loops -fno-schedule-insns -fno-schedule-insns2" } */
#include <stdint-gcc.h>
#ifndef TYPE
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-10.c
index dc4d6512f23..b80e174f6e0 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-10.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-10.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */
#define TYPE _Float16
#define ITYPE int16_t
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-11.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-11.c
index 36ade63dd9e..1b976ca85b1 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-11.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-11.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */
#define TYPE float
#define ITYPE int32_t
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-12.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-12.c
index a2a93c432c6..b36ca8dd7f9 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-12.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-12.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -march=rv64gcv_zvfh -mabi=lp64d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-std=c99 -march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */
#define TYPE double
#define ITYPE int64_t
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-13.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-13.c
index 4da1c4148bb..76b3996743b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-13.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-13.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -march=rv64gcv_zvfh -mabi=lp64d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-std=c99 -march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */
#include <stdint-gcc.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-14.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-14.c
index f652a35bae4..1abce7ad9ca 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-14.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-14.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -march=rv64gcv_zvfh -mabi=lp64d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-std=c99 -march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */
#include <stdint-gcc.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-15.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-15.c
index 29d32ab29dc..dfd51b23a91 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-15.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-15.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -march=rv64gcv_zvfh -mabi=lp64d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-std=c99 -march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */
#include <stdint-gcc.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-16.c
index 15de93ec66f..10088bd1395 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-16.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -march=rv64gcv_zvfh -mabi=lp64d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-std=c99 -march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */
#include <stdint-gcc.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-17.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-17.c
index 44eb0725a8e..f460ec282d2 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-17.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-17.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -march=rv64gcv_zvfh -mabi=lp64d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-std=c99 -march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */
#include <stdint-gcc.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-18.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-18.c
index f6f559e4c2d..3cb01ddaa96 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-18.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-18.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -march=rv64gcv_zvfh -mabi=lp64d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-std=c99 -march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */
#include <stdint-gcc.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-2.c
index 2a61a79c620..52ded08faf5 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-2.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -funroll-all-loops -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=zvl -funroll-all-loops -fno-schedule-insns -fno-schedule-insns2" } */
#define TYPE uint16_t
#include "struct_vect-1.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-3.c
index 3d818dad10f..48395e99320 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-3.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -funroll-all-loops -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=zvl -funroll-all-loops -fno-schedule-insns -fno-schedule-insns2" } */
#define TYPE uint32_t
#include "struct_vect-1.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-4.c
index b5ad45e8f82..03829dd8381 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-4.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -funroll-all-loops -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=zvl -funroll-all-loops -fno-schedule-insns -fno-schedule-insns2" } */
#define TYPE uint64_t
#include "struct_vect-1.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-5.c
index 63b83dfab2c..aef9cb77fd5 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-5.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -funroll-all-loops -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=zvl -funroll-all-loops -fno-schedule-insns -fno-schedule-insns2" } */
#define TYPE float
#include "struct_vect-1.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-6.c
index 2494744d8b4..59020b06daf 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-6.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */
#include <stdint-gcc.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-7.c
index dd01769d98d..c13f1e77102 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-7.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */
#define TYPE uint16_t
#define ITYPE int16_t
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-8.c
index bedf17a6ee0..7a30314f89e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-8.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */
#define TYPE uint32_t
#define ITYPE int32_t
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-9.c
index 8b608224a4f..85a90220166 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-9.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-9.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -march=rv64gcv_zvfh -mabi=lp64d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-std=c99 -march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */
#define TYPE uint64_t
#define ITYPE int64_t
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-1.c
index a499c7ca320..dafa5655e7e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-1.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "-std=c99 --param=riscv-autovec-preference=fixed-vlmax -funroll-all-loops -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-additional-options "-std=c99 -mrvv-vector-bits=zvl -funroll-all-loops -fno-schedule-insns -fno-schedule-insns2" } */
#include "struct_vect-1.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-10.c
index 049280baee5..a8ff07db26f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-10.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-10.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v && riscv_zvfh } } } */
-/* { dg-additional-options "-std=gnu99 --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-std=gnu99 -mrvv-vector-bits=scalable -fno-vect-cost-model" } */
#define TYPE _Float16
#define ITYPE int16_t
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-11.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-11.c
index 387d69709a6..93bd2544d4a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-11.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-11.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "-std=c99 --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-std=c99 -mrvv-vector-bits=scalable -fno-vect-cost-model" } */
#define TYPE float
#define ITYPE int32_t
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-12.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-12.c
index 391caa4e516..6d4f54d2858 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-12.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-12.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "-std=c99 --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-std=c99 -mrvv-vector-bits=scalable -fno-vect-cost-model" } */
#define TYPE double
#define ITYPE int64_t
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-13.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-13.c
index 711ea443023..1b19b01ec3f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-13.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-13.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */
#include "struct_vect-13.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-14.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-14.c
index bb66c5f6f2b..7e51b9e7743 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-14.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-14.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */
#include "struct_vect-14.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-15.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-15.c
index 07d6c08710c..2007c004e95 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-15.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-15.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */
#include "struct_vect-15.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-16.c
index d2a00462bfe..21506dbf107 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-16.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */
#include "struct_vect-16.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-17.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-17.c
index c34a8ababf7..8e30b33a600 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-17.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-17.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */
#include "struct_vect-17.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-18.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-18.c
index 5346c90b813..126edb477c2 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-18.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-18.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */
#include "struct_vect-18.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-2.c
index 6ac6182b0d4..4cf09059121 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-2.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "-std=c99 --param=riscv-autovec-preference=fixed-vlmax -funroll-all-loops -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-additional-options "-std=c99 -mrvv-vector-bits=zvl -funroll-all-loops -fno-schedule-insns -fno-schedule-insns2" } */
#define TYPE uint16_t
#include "struct_vect_run-1.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-3.c
index f64174ba4b0..1075b374b46 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-3.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "-std=c99 --param=riscv-autovec-preference=fixed-vlmax -funroll-all-loops -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-additional-options "-std=c99 -mrvv-vector-bits=zvl -funroll-all-loops -fno-schedule-insns -fno-schedule-insns2" } */
#define TYPE uint32_t
#include "struct_vect_run-1.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-4.c
index 610ee8e0fac..9f4790cbebc 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-4.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "-std=c99 --param=riscv-autovec-preference=fixed-vlmax -funroll-all-loops -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-additional-options "-std=c99 -mrvv-vector-bits=zvl -funroll-all-loops -fno-schedule-insns -fno-schedule-insns2" } */
#define TYPE uint64_t
#include "struct_vect_run-1.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-5.c
index 5dfa0bade4a..980f506ee81 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-5.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "-std=c99 --param=riscv-autovec-preference=fixed-vlmax -funroll-all-loops -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-additional-options "-std=c99 -mrvv-vector-bits=zvl -funroll-all-loops -fno-schedule-insns -fno-schedule-insns2" } */
#define TYPE float
#include "struct_vect_run-1.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-6.c
index c836bcddb7e..72d29b7ffee 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-6.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "-std=c99 --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-std=c99 -mrvv-vector-bits=scalable -fno-vect-cost-model" } */
#include "struct_vect-6.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-7.c
index 2023b338464..18b6192f389 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-7.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "-std=c99 --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-std=c99 -mrvv-vector-bits=scalable -fno-vect-cost-model" } */
#define TYPE uint16_t
#define ITYPE int16_t
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-8.c
index 476c54acd3d..728f9aa4a13 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-8.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "-std=c99 --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-std=c99 -mrvv-vector-bits=scalable -fno-vect-cost-model" } */
#define TYPE uint32_t
#define ITYPE int32_t
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-9.c
index 2cb2efa910d..db6f1f139e8 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-9.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-9.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "-std=c99 --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-std=c99 -mrvv-vector-bits=scalable -fno-vect-cost-model" } */
#define TYPE uint64_t
#define ITYPE int64_t
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-1.c
index 38e48150a71..6da2cd259f5 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-1.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -ffast-math -fno-vect-cost-model" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -ffast-math -fno-vect-cost-model" } */
#include <stdint-gcc.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-10.c
index 413086911b9..05cf2752e72 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-10.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-10.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -ffast-math -fno-vect-cost-model" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -ffast-math -fno-vect-cost-model" } */
#include <stdint-gcc.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-11.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-11.c
index a8685c62c57..e8929bd37ed 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-11.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-11.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-schedule-insns -ffast-math -fno-vect-cost-model" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-schedule-insns -ffast-math -fno-vect-cost-model" } */
#include <stdint-gcc.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-12.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-12.c
index d13ab41edc5..9d71890064c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-12.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-12.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -ffast-math -fno-vect-cost-model" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -ffast-math -fno-vect-cost-model" } */
#include <stdint-gcc.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-2.c
index f00c6087164..c13401d33f1 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-2.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-schedule-insns -ffast-math -fno-vect-cost-model" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-schedule-insns -ffast-math -fno-vect-cost-model" } */
#include <stdint-gcc.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-3.c
index 1886fc262aa..fa64ce0d6c4 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-3.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -ffast-math -fno-vect-cost-model" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -ffast-math -fno-vect-cost-model" } */
#include <stdint-gcc.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-4.c
index fff51911020..c43d0b3c982 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-4.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -ffast-math -fno-vect-cost-model" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -ffast-math -fno-vect-cost-model" } */
#include <stdint-gcc.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-5.c
index 238cd5d7f41..a1ca5ca2d53 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-5.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-schedule-insns -ffast-math -fno-vect-cost-model" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-schedule-insns -ffast-math -fno-vect-cost-model" } */
#include <stdint-gcc.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-6.c
index 8d9e63c2a4b..b75ae25135c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-6.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -ffast-math -fno-vect-cost-model" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -ffast-math -fno-vect-cost-model" } */
#include <stdint-gcc.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-7.c
index 7fdf5127c5b..88905ead320 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-7.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -ffast-math -fno-vect-cost-model" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -ffast-math -fno-vect-cost-model" } */
#include <stdint-gcc.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-8.c
index a73e04bff8d..701d84db0ee 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-8.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-schedule-insns -ffast-math -fno-vect-cost-model" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-schedule-insns -ffast-math -fno-vect-cost-model" } */
#include <stdint-gcc.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-9.c
index b5ee009a363..ef9958be0ca 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-9.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-9.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -ffast-math -fno-vect-cost-model" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -ffast-math -fno-vect-cost-model" } */
#include <stdint-gcc.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-1.c
index c5fab3f1f38..a30ddf93bb2 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-1.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fdump-tree-optimized-details -fno-vect-cost-model" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-optimized-details -fno-vect-cost-model" } */
#include "ternop-1.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-10.c
index a65c398cba3..b1d117cc9b7 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-10.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-10.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fdump-tree-optimized-details -fno-vect-cost-model" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-optimized-details -fno-vect-cost-model" } */
#include "ternop-10.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-11.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-11.c
index 9725cfad7ca..fbe53f8d639 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-11.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-11.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fdump-tree-optimized-details -fno-vect-cost-model" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-optimized-details -fno-vect-cost-model" } */
#include "ternop-11.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-12.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-12.c
index 97be71c4bd2..6f23bcc21a2 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-12.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-12.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fdump-tree-optimized-details -fno-schedule-insns -fno-vect-cost-model" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-optimized-details -fno-schedule-insns -fno-vect-cost-model" } */
#include "ternop-12.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-2.c
index 13367423751..ba005e614f9 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-2.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fdump-tree-optimized-details -fno-vect-cost-model" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-optimized-details -fno-vect-cost-model" } */
#include "ternop-2.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-3.c
index de6d40431f8..f749ef30a29 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-3.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fdump-tree-optimized-details -fno-schedule-insns -fno-vect-cost-model" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-optimized-details -fno-schedule-insns -fno-vect-cost-model" } */
#include "ternop-3.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-4.c
index 4d73a541b0b..00b793d32fc 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-4.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fdump-tree-optimized-details -fno-vect-cost-model" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-optimized-details -fno-vect-cost-model" } */
#include "ternop-4.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-5.c
index 6fa28a23f3f..34b8b4b7fc7 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-5.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fdump-tree-optimized-details -fno-vect-cost-model" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-optimized-details -fno-vect-cost-model" } */
#include "ternop-5.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-6.c
index 33faf0582a7..7bdf19e4d8f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-6.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fdump-tree-optimized-details -fno-schedule-insns -fno-vect-cost-model" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-optimized-details -fno-schedule-insns -fno-vect-cost-model" } */
#include "ternop-6.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-7.c
index 44807993c33..89e4938ab56 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-7.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fdump-tree-optimized-details -fno-vect-cost-model" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-optimized-details -fno-vect-cost-model" } */
#include "ternop-7.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-8.c
index c89f5836bcb..d31c9bd0f3b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-8.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fdump-tree-optimized-details -fno-vect-cost-model" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-optimized-details -fno-vect-cost-model" } */
#include "ternop-8.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-9.c
index 2de649b1db8..221b03e9b8d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-9.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-9.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fdump-tree-optimized-details -fno-schedule-insns -fno-vect-cost-model" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-optimized-details -fno-schedule-insns -fno-vect-cost-model" } */
#include "ternop-9.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-1.c
index af6d5c66e6a..afb988e97c9 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-1.c
@@ -1,4 +1,4 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable" } */
#include "ternop_run-1.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-10.c
index f4a2060505a..b4761bf149a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-10.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-10.c
@@ -1,4 +1,4 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable" } */
#include "ternop_run-10.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-11.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-11.c
index 0060592033b..1b9efa967d9 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-11.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-11.c
@@ -1,4 +1,4 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable" } */
#include "ternop_run-11.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-12.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-12.c
index f295e871321..bc21c30735c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-12.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-12.c
@@ -1,4 +1,4 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable" } */
#include "ternop_run-12.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-2.c
index 9dedaa92508..170d9762178 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-2.c
@@ -1,4 +1,4 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable" } */
#include "ternop_run-2.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-3.c
index 09e44bbea58..b885801842e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-3.c
@@ -1,4 +1,4 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable" } */
#include "ternop_run-3.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-4.c
index 3a2bdcc888e..87be031eed9 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-4.c
@@ -1,4 +1,4 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable" } */
#include "ternop_run-4.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-5.c
index e672fc19939..3de31dc182f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-5.c
@@ -1,4 +1,4 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable" } */
#include "ternop_run-5.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-6.c
index 1a259286f22..f54d96c5034 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-6.c
@@ -1,4 +1,4 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable" } */
#include "ternop_run-6.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-7.c
index c6ebc12beff..28713621e09 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-7.c
@@ -1,4 +1,4 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable" } */
#include "ternop_run-7.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-8.c
index e7647231c47..047aefc8ac0 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-8.c
@@ -1,4 +1,4 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable" } */
#include "ternop_run-8.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-9.c
index 05878d089b3..a744bd5020f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-9.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-9.c
@@ -1,4 +1,4 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable" } */
#include "ternop_run-9.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-1.c
index 56599d7dd0f..01dd791a000 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-1.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */
#include "ternop-1.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-10.c
index d4492f96d12..9db0d23419c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-10.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-10.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */
#include "ternop-10.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-11.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-11.c
index dd6e6f73aec..08dcb3aef3f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-11.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-11.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */
#include "ternop-11.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-12.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-12.c
index 8bdc4e9511e..08eb3b5a525 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-12.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-12.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */
#include "ternop-12.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-2.c
index 7817134010f..0db89cfd54f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-2.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */
#include "ternop-2.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-3.c
index 3e966884409..344871b8111 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-3.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */
#include "ternop-3.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-4.c
index f6a07a99479..39108aaf4b2 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-4.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */
#include "ternop-4.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-5.c
index 4de012423de..d2122da8918 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-5.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */
#include "ternop-5.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-6.c
index 9e79c03a651..652d5fe24bb 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-6.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */
#include "ternop-6.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-7.c
index 61b97f1ca90..950936a74a4 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-7.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */
#include "ternop-7.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-8.c
index 52ef2625f32..f4292a0386e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-8.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */
#include "ternop-8.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-9.c
index 2bc4d963b5a..0636dd66e31 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-9.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-9.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */
#include "ternop-9.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-1.c
index 6c707e3c6ad..cbda6c46829 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-1.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v && riscv_zvfh } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */
#include "ternop-1.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-10.c
index 4d57fe56e5b..90efe8a76f7 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-10.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-10.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v && riscv_zvfh } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */
#include "ternop-10.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-11.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-11.c
index 80f1d54aefa..2bf3c3a6df5 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-11.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-11.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v && riscv_zvfh } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */
#include "ternop-11.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-12.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-12.c
index 29b1683ff67..0f858927741 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-12.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-12.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v && riscv_zvfh } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */
#include "ternop-12.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-2.c
index 3f9036c2868..581fab528ac 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-2.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v && riscv_zvfh } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */
#include "ternop-2.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-3.c
index e9ad951e62f..b71ea15d8fa 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-3.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v && riscv_zvfh } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */
#include "ternop-3.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-4.c
index fb0cb1fef6b..c6892aaef6f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-4.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v && riscv_zvfh } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */
#include "ternop-4.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-5.c
index 06f6dbd1dbf..c148155d7de 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-5.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v && riscv_zvfh } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */
#include "ternop-5.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-6.c
index b7f931e9d78..f546964e6ec 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-6.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v && riscv_zvfh } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */
#include "ternop-6.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-7.c
index 3a712fd0dcb..b17970bf178 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-7.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v && riscv_zvfh } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */
#include "ternop-7.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-8.c
index f01cf6d9645..b72f2a7a569 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-8.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v && riscv_zvfh } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */
#include "ternop-8.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-9.c
index eb8a105d0f1..5a190aa8f69 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-9.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-9.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v && riscv_zvfh } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */
#include "ternop-9.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-run.c
index 49cdffea71b..f3be58ec493 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-run.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-run.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=zvl -ffast-math" } */
#include "abs-template.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-rv32gcv.c
index dea790ccc2d..85751912e33 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-rv32gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-rv32gcv.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=zvl -ffast-math" } */
#include "abs-template.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-rv64gcv.c
index b58f1aa3496..d1bd43ae9db 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-rv64gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-rv64gcv.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=zvl -ffast-math" } */
#include "abs-template.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-zvfh-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-zvfh-run.c
index f0c00de9f8f..22b5f6096e1 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-zvfh-run.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-zvfh-run.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v && riscv_zvfh } } } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=zvl -ffast-math" } */
#include "abs-template.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/popcount-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/popcount-1.c
index 9c065bedb87..fad528a842e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/popcount-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/popcount-1.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv64gcv -mabi=lp64d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -fdump-tree-vect-details" } */
+/* { dg-additional-options "-march=rv64gcv -mabi=lp64d -mrvv-vector-bits=scalable -fno-vect-cost-model -fdump-tree-vect-details" } */
#include <stdint-gcc.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/popcount-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/popcount-2.c
index 5719d9c1b55..0199f8cb515 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/popcount-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/popcount-2.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv64gcv -mabi=lp64d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -fdump-tree-slp-details" } */
+/* { dg-additional-options "-march=rv64gcv -mabi=lp64d -mrvv-vector-bits=scalable -fno-vect-cost-model -fdump-tree-slp-details" } */
int x[8];
int y[8];
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vfsqrt-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vfsqrt-run.c
index 739d1973229..67753d5c4b0 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vfsqrt-run.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vfsqrt-run.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=zvl -ffast-math" } */
#include "vfsqrt-template.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vfsqrt-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vfsqrt-rv32gcv.c
index dc3f7c49e24..5a1f910cac3 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vfsqrt-rv32gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vfsqrt-rv32gcv.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=zvl -ffast-math" } */
#include "vfsqrt-template.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vfsqrt-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vfsqrt-rv64gcv.c
index 31d99756f02..3799f98bd19 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vfsqrt-rv64gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vfsqrt-rv64gcv.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=zvl -ffast-math" } */
#include "vfsqrt-template.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vfsqrt-zvfh-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vfsqrt-zvfh-run.c
index c974ef090ba..a1ecd4de640 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vfsqrt-zvfh-run.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vfsqrt-zvfh-run.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_zvfh && riscv_zfh } } } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=zvl -ffast-math" } */
#include "vfsqrt-template.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-run.c
index 1429731d59f..100b8ac8591 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-run.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-run.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=zvl -ffast-math" } */
#include "vneg-template.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-rv32gcv.c
index 4a9ceb5faf2..66b512eee20 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-rv32gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-rv32gcv.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=zvl -ffast-math" } */
#include "vneg-template.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-rv64gcv.c
index 2c5e2bd2a0b..d32c6a187c1 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-rv64gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-rv64gcv.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=zvl -ffast-math" } */
#include "vneg-template.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-zvfh-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-zvfh-run.c
index 38c8c7ae83d..6e233c11262 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-zvfh-run.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-zvfh-run.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v && riscv_zvfh } } } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=zvl -ffast-math" } */
#include "vneg-template.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vnot-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vnot-run.c
index 6df15bc8f0c..2941a34dc63 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vnot-run.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vnot-run.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=zvl" } */
#include "vnot-template.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vnot-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vnot-rv32gcv.c
index ecc4316bd4f..9f9f5d97a06 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vnot-rv32gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vnot-rv32gcv.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=zvl" } */
#include "vnot-template.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vnot-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vnot-rv64gcv.c
index 67e28af2cd8..6bdb55841eb 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vnot-rv64gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vnot-rv64gcv.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv -mabi=lp64d -mrvv-vector-bits=zvl" } */
#include "vnot-template.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/v-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/v-1.c
index ebbe5e210c5..00a602a69b5 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/v-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/v-1.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-vect-details" } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-vect-details" } */
#include "template-1.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/v-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/v-2.c
index 66d8ea15f5b..3968e53b970 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/v-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/v-2.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32d -fno-vect-cost-model --param riscv-autovec-preference=fixed-vlmax -fdump-tree-vect-details" } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -fno-vect-cost-model -mrvv-vector-bits=zvl -fdump-tree-vect-details" } */
#include "template-1.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-1.c
index 24daca50622..64a114e517a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-1.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3" } */
+/* { dg-options "-mrvv-vector-bits=zvl -O3" } */
#include <stdint-gcc.h>
#include <assert.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-10.c
index 264a096519f..f1600e0a7d6 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-10.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-10.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3 --param riscv-autovec-lmul=m2" } */
+/* { dg-options "-mrvv-vector-bits=zvl -O3 --param riscv-autovec-lmul=m2" } */
#include <stdint-gcc.h>
#include <assert.h>
#define N 16
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-11.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-11.c
index 06521d19352..44fe7aae82f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-11.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-11.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3" } */
+/* { dg-options "-mrvv-vector-bits=zvl -O3" } */
#include <stdint-gcc.h>
#include <assert.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-12.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-12.c
index 1690615ee2d..c41f11bfa85 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-12.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-12.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3 --param riscv-autovec-lmul=m2" } */
+/* { dg-options "-mrvv-vector-bits=zvl -O3 --param riscv-autovec-lmul=m2" } */
#include <stdint-gcc.h>
#include <assert.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-13.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-13.c
index 10b292b4b27..12174f73488 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-13.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-13.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3 --param riscv-autovec-lmul=m4" } */
+/* { dg-options "-mrvv-vector-bits=zvl -O3 --param riscv-autovec-lmul=m4" } */
#include <stdint-gcc.h>
#include <assert.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-14.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-14.c
index f7e6765b10b..7ecfc802583 100644
--- a/gcc/testsuite/gcc.targe[...]
[diff truncated at 524288 bytes]
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