[gcc r15-1562] [PATCH] RISC-V: Fix unresolved mcpu-[67].c tests

[Jeff Law]

https://gcc.gnu.org/g:77f3b3419d476e90a2b82dff2204466aba3b9c2c

commit r15-1562-g77f3b3419d476e90a2b82dff2204466aba3b9c2c
Author: Craig Blackmore <craig.blackmore@embecosm.com>
Date:   Sat Jun 22 22:07:06 2024 -0600

    [PATCH] RISC-V: Fix unresolved mcpu-[67].c tests
    
    These tests check the sched2 dump, so skip them for optimization levels
    that do not enable sched2.
    
    gcc/testsuite/ChangeLog:
    
            * gcc.target/riscv/mcpu-6.c: Skip for -O0, -O1, -Og.
            * gcc.target/riscv/mcpu-7.c: Likewise.

Diff:
---
 gcc/testsuite/gcc.target/riscv/mcpu-6.c | 1 +
 gcc/testsuite/gcc.target/riscv/mcpu-7.c | 1 +
 2 files changed, 2 insertions(+)

diff --git a/gcc/testsuite/gcc.target/riscv/mcpu-6.c b/gcc/testsuite/gcc.target/riscv/mcpu-6.c
index 96faa01653e..0126011939f 100644
--- a/gcc/testsuite/gcc.target/riscv/mcpu-6.c
+++ b/gcc/testsuite/gcc.target/riscv/mcpu-6.c
@@ -1,4 +1,5 @@
 /* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-O1" "-Og" } } */
 /* Verify -mtune has higher priority than -mcpu for pipeline model .  */
 /* { dg-options "-mcpu=sifive-u74 -mtune=rocket -fdump-rtl-sched2-details -march=rv32i -mabi=ilp32" } */
 /* { dg-final { scan-rtl-dump "simple_return\[ \]+:alu" "sched2" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/mcpu-7.c b/gcc/testsuite/gcc.target/riscv/mcpu-7.c
index 6832323e529..656436343bd 100644
--- a/gcc/testsuite/gcc.target/riscv/mcpu-7.c
+++ b/gcc/testsuite/gcc.target/riscv/mcpu-7.c
@@ -1,4 +1,5 @@
 /* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-O1" "-Og" } } */
 /* Verify -mtune has higher priority than -mcpu for pipeline model .  */
 /* { dg-options "-mcpu=sifive-s21 -mtune=sifive-u74 -fdump-rtl-sched2-details -march=rv32i -mabi=ilp32" } */
 /* { dg-final { scan-rtl-dump "simple_return\[ \]+:sifive_7_B" "sched2" } } */