[gcc(refs/users/meissner/heads/work169-tar)] Change TAR debug options.

[Michael Meissner]

https://gcc.gnu.org/g:c0d135dce0787d4516b19615b9743260ea0a1924

commit c0d135dce0787d4516b19615b9743260ea0a1924
Author: Michael Meissner <meissner@linux.ibm.com>
Date:   Sat Jun 22 12:07:03 2024 -0400

    Change TAR debug options.
    
    2024-06-22  Michael Meissner  <meissner@linux.ibm.com>
    
            * config/rs6000/rs6000.cc (rs6000_hard_regno_mode_ok_uncached): Delete
            -mqispr, -mhispr, -msispr, -mfpspr, -mdfspr.  Add -mintspr and -mfpspr.
            (rs6000_debug_reg_global): Likewise.
            * config/rs6000/rs6000.opt (-mqispr): Delete.
            (-mhispr): Likewise.
            (-msispr): Likewise.
            (-msfspr): Likewise.
            (-mdfspr): Likewise.
            (-mintspr): New option.
            (-mfpspr): Likewise.

Diff:
---
 gcc/config/rs6000/rs6000.cc  | 54 ++++++++++----------------------------------
 gcc/config/rs6000/rs6000.opt | 26 ++++++---------------
 2 files changed, 19 insertions(+), 61 deletions(-)

diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index d96adf12c5d..7bd7e2f2181 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -1954,34 +1954,16 @@ rs6000_hard_regno_mode_ok_uncached (int regno, machine_mode mode)
       if (orig_complex_p)
 	return 0;
 
-      if (GET_MODE_CLASS (mode) == MODE_CC)
-	return TARGET_CCSPR != 0;
-
-      switch (mode)
-	{
-	case E_QImode:
-	  return TARGET_QISPR != 0;
-
-	case E_HImode:
-	  return TARGET_HISPR != 0;
-
-	case E_SImode:
-	  return TARGET_SISPR || !TARGET_POWERPC64;
-
-	case E_DImode:
-	  return TARGET_POWERPC64 != 0;
-
-	case E_SFmode:
-	  return TARGET_SFSPR != 0;
+      if (GET_MODE_SIZE (mode) > UNITS_PER_WORD)
+	return 0;
 
-	case E_DFmode:
-	  return TARGET_DFSPR && TARGET_POWERPC64;
+      if (SCALAR_INT_MODE_P (mode))
+	return (mode == Pmode || TARGET_INTSPR);
 
-	default:
-	  break;
-	}
+      if (SCALAR_FLOAT_MODE_P (mode))
+	return TARGET_FPSPR != 0;
 
-      return false;
+      return (TARGET_CCSPR && GET_MODE_CLASS (mode) == MODE_CC);
 
     default:
       break;
@@ -2646,26 +2628,14 @@ rs6000_debug_reg_global (void)
     fprintf (stderr, DEBUG_FMT_D, "VSX easy 64-bit mfvsrld element",
 	     (int)VECTOR_ELEMENT_MFVSRLD_64BIT);
 
-  fprintf (stderr, DEBUG_FMT_S, "Condition modes in SPR",
+  fprintf (stderr, DEBUG_FMT_S, "Condition code modes in SPRs",
 	   TARGET_CCSPR ? "yes" : "no");
 
-  fprintf (stderr, DEBUG_FMT_S, "QImode in SPR",
-	   TARGET_QISPR ? "yes" : "no");
-
-  fprintf (stderr, DEBUG_FMT_S, "HImode in SPR",
-	   TARGET_HISPR ? "yes" : "no");
-
-  fprintf (stderr, DEBUG_FMT_S, "SImode in SPR",
-	   TARGET_SISPR || !TARGET_POWERPC64 ? "yes" : "no");
-
-  fprintf (stderr, DEBUG_FMT_S, "DImode in SPR",
-	   TARGET_POWERPC64 ? "yes" : "no");
-
-  fprintf (stderr, DEBUG_FMT_S, "SFmode in SPR",
-	   TARGET_SFSPR ? "yes" : "no");
+  fprintf (stderr, DEBUG_FMT_S, "Small integer modes in SPRs",
+	   TARGET_INTSPR ? "yes" : "no");
 
-  fprintf (stderr, DEBUG_FMT_S, "DFmode in SPR",
-	   TARGET_DFSPR ? "yes" : "no");
+  fprintf (stderr, DEBUG_FMT_S, "Floating point modes in SPRs",
+	   TARGET_FPSPR ? "yes" : "no");
 }
 
 
diff --git a/gcc/config/rs6000/rs6000.opt b/gcc/config/rs6000/rs6000.opt
index 27f873972b5..e5657003e27 100644
--- a/gcc/config/rs6000/rs6000.opt
+++ b/gcc/config/rs6000/rs6000.opt
@@ -636,27 +636,15 @@ Allow (do not allow) use the TAR register.
 
 mccspr
 Target Undocumented Var(TARGET_CCSPR) Init(0)
-Allow (do not allow) condition modes to be in the CTR or TAR registers.
+Allow (do not allow) condition modes to be in the LR, CTR or TAR registers.
 
-mqispr
-Target Undocumented Var(TARGET_QISPR) Init(1)
-Allow (do not allow) 8-bit integers to be in the CTR or TAR registers.
+mintspr
+Target Undocumented Var(TARGET_INTSPR) Init(0)
+Allow (do not allow) small integers to be in the LR, CTR or TAR registers.
 
-mhispr
-Target Undocumented Var(TARGET_HISPR) Init(1)
-Allow (do not allow) 16-bit integers to be in the CTR or TAR registers.
-
-msispr
-Target Undocumented Var(TARGET_SISPR) Init(1)
-Allow (do not allow) 32-bit integers to be in the CTR or TAR registers.
-
-msfspr
-Target Undocumented Var(TARGET_SFSPR) Init(0)
-Allow (do not allow) 32-bit floating point to be in the CTR or TAR registers.
-
-mdfspr
-Target Undocumented Var(TARGET_DFSPR) Init(0)
-Allow (do not allow) 64-bit floating point to be in the CTR or TAR registers.
+mfpspr
+Target Undocumented Var(TARGET_FPSPR) Init(0)
+Allow (do not allow) floating point to be in the LR, CTR or TAR registers.
 
 ; Documented parameters