[gcc(refs/users/meissner/heads/work169-tar)] Add SPR debug options.

[Michael Meissner]

https://gcc.gnu.org/g:98b15f63fd14383a7d28f637d03bdafe5d19880a

commit 98b15f63fd14383a7d28f637d03bdafe5d19880a
Author: Michael Meissner <meissner@linux.ibm.com>
Date:   Thu Jun 20 21:02:04 2024 -0400

    Add SPR debug options.
    
    2024-06-20  Michael Meissner  <meissner@linux.ibm.com>
    
    gcc/
    
            * config/rs6000/rs6000.cc (rs6000_hard_regno_mode_ok_uncached): Add
            support for SPR debug options.
            * config/rs6000/rs6000.opt (-mccspr): New debug option.
            (-mqispr): Likewise.
            (-mhispr): Likewise.
            (-msispr): Likewise.
            (-mintspr): Likewise.
            (-msfspr): Likewise.
            (-mdfspr): Likewise.
            (-mfpspr): Likewise.

Diff:
---
 gcc/config/rs6000/rs6000.cc  | 63 ++++++++++++++++++++++++++++++++++++++------
 gcc/config/rs6000/rs6000.opt | 32 ++++++++++++++++++++++
 2 files changed, 87 insertions(+), 8 deletions(-)

diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index c106e13b8adf..2eaa88a6d633 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -1946,18 +1946,44 @@ rs6000_hard_regno_mode_ok_uncached (int regno, machine_mode mode)
     {
     case VRSAVE_REGNO:
     case VSCR_REGNO:
+      return (!orig_complex_p && mode == SImode);
+
     case LR_REGNO:
+      return (!orig_complex_p && mode == Pmode);
+
     case CTR_REGNO:
     case TAR_REGNO:
-      {
-	unsigned reg_size = ((regno == VRSAVE_REGNO || regno == VSCR_REGNO)
-			     ? 4
-			     : UNITS_PER_WORD);
+      if (orig_complex_p)
+	return 0;
 
-	return (!orig_complex_p
-		&& GET_MODE_SIZE (mode) <= reg_size
-		&& SCALAR_INT_MODE_P (mode));
-      }
+      if (GET_MODE_CLASS (mode) == MODE_CC)
+	return TARGET_CCSPR != 0;
+
+      switch (mode)
+	{
+	case E_QImode:
+	  return (TARGET_QISPR || TARGET_INTSPR);
+
+	case E_HImode:
+	  return (TARGET_HISPR || TARGET_INTSPR);
+
+	case E_SImode:
+	  return (TARGET_SISPR || TARGET_INTSPR || !TARGET_POWERPC64);
+
+	case E_DImode:
+	  return TARGET_POWERPC64;
+
+	case E_SFmode:
+	  return (TARGET_SFSPR || TARGET_FPSPR);
+
+	case E_DFmode:
+	  return ((TARGET_DFSPR || TARGET_FPSPR) && TARGET_POWERPC64);
+
+	default:
+	  break;
+	}
+
+      return false;
 
     default:
       break;
@@ -2621,6 +2647,27 @@ rs6000_debug_reg_global (void)
   if (TARGET_DIRECT_MOVE_128)
     fprintf (stderr, DEBUG_FMT_D, "VSX easy 64-bit mfvsrld element",
 	     (int)VECTOR_ELEMENT_MFVSRLD_64BIT);
+
+  fprintf (stderr, DEBUG_FMT_S, "Condition modes in SPR",
+	   TARGET_CCSPR ? "yes" : "no");
+
+  fprintf (stderr, DEBUG_FMT_S, "QImode in SPR",
+	   (TARGET_QISPR || TARGET_INTSPR) ? "yes" : "no");
+
+  fprintf (stderr, DEBUG_FMT_S, "HImode in SPR",
+	   TARGET_HISPR || TARGET_INTSPR ? "yes" : "no");
+
+  fprintf (stderr, DEBUG_FMT_S, "SImode in SPR",
+	   TARGET_SISPR || TARGET_INTSPR || !TARGET_POWERPC64 ? "yes" : "no");
+
+  fprintf (stderr, DEBUG_FMT_S, "DImode in SPR",
+	   TARGET_POWERPC64 ? "yes" : "no");
+
+  fprintf (stderr, DEBUG_FMT_S, "SFmode in SPR",
+	   TARGET_SFSPR || TARGET_FPSPR ? "yes" : "no");
+
+  fprintf (stderr, DEBUG_FMT_S, "DFmode in SPR",
+	   TARGET_DFSPR || TARGET_FPSPR ? "yes" : "no");
 }
 
 
diff --git a/gcc/config/rs6000/rs6000.opt b/gcc/config/rs6000/rs6000.opt
index 7f7a283bc993..f339e1bed39a 100644
--- a/gcc/config/rs6000/rs6000.opt
+++ b/gcc/config/rs6000/rs6000.opt
@@ -634,6 +634,38 @@ mtar
 Target Undocumented Mask(TAR) Var(rs6000_isa_flags)
 Allow (do not allow) use the TAR register.
 
+mccspr
+Target Undocumented Var(TARGET_CCSPR) Init(0)
+Allow (do not allow) condition modes to be in the CTR or TAR registers.
+
+mqispr
+Target Undocumented Var(TARGET_QISPR) Init(1)
+Allow (do not allow) 8-bit integers to be in the CTR or TAR registers.
+
+mhispr
+Target Undocumented Var(TARGET_HISPR) Init(1)
+Allow (do not allow) 16-bit integers to be in the CTR or TAR registers.
+
+msispr
+Target Undocumented Var(TARGET_SISPR) Init(1)
+Allow (do not allow) 32-bit integers to be in the CTR or TAR registers.
+
+mintspr
+Target Undocumented Var(TARGET_INTSPR) Init(0)
+Allow (do not allow) small integers to be in the CTR or TAR registers.
+
+msfspr
+Target Undocumented Var(TARGET_SFSPR) Init(0)
+Allow (do not allow) 32-bit floating point to be in the CTR or TAR registers.
+
+mdfspr
+Target Undocumented Var(TARGET_DFSPR) Init(0)
+Allow (do not allow) 64-bit floating point to be in the CTR or TAR registers.
+
+mfpspr
+Target Undocumented Var(TARGET_FPSPR) Init(0)
+Allow (do not allow) floating point values to be in the CTR or TAR registers.
+
 ; Documented parameters
 
 -param=rs6000-vect-unroll-limit=