[gcc r15-1008] invoke.texi: Clarify -march=lujiazui

[Jakub Jelinek]

https://gcc.gnu.org/g:09b4ab53155ea16e1fb12c2afcd9b6fe29a31c74

commit r15-1008-g09b4ab53155ea16e1fb12c2afcd9b6fe29a31c74
Author: Jakub Jelinek <jakub@redhat.com>
Date:   Tue Jun 4 12:20:13 2024 +0200

    invoke.texi: Clarify -march=lujiazui
    
    I was recently searching which exact CPUs are affected by the PR114576
    wrong-code issue and went from the PTA_* bitmasks in GCC, so arrived
    at the goldmont, goldmont-plus, tremont and lujiazui CPUs (as -march=
    cases which do enable -maes and don't enable -mavx).
    But when double-checking that against the invoke.texi documentation,
    that was true for the first 3, but lujiazui said it supported AVX.
    I was really confused by that, until I found the
    https://gcc.gnu.org/pipermail/gcc-patches/2022-October/604407.html
    explanation.  So, seems the CPUs do have AVX and F16C but -march=lujiazui
    doesn't enable those and even activelly attempts to filter those out from
    the announced CPUID features, in glibc as well as e.g. in libgcc.
    
    Thus, I think we should document what actually happens, otherwise
    users could assume that
    gcc -march=lujiazui predefines __AVX__ and __F16C__, which it doesn't.
    
    2024-06-04  Jakub Jelinek  <jakub@redhat.com>
    
            * doc/invoke.texi (lujiazui): Clarify that while the CPUs do support
            AVX and F16C, -march=lujiazui actually doesn't enable those.

Diff:
---
 gcc/doc/invoke.texi | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index 45115b5fbed..4e8967fd8ab 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -34808,8 +34808,10 @@ instruction set support.
 
 @item lujiazui
 ZHAOXIN lujiazui CPU with x86-64, MOVBE, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1,
-SSE4.2, AVX, POPCNT, AES, PCLMUL, RDRND, XSAVE, XSAVEOPT, FSGSBASE, CX16,
-ABM, BMI, BMI2, F16C, FXSR, RDSEED instruction set support.
+SSE4.2, POPCNT, AES, PCLMUL, RDRND, XSAVE, XSAVEOPT, FSGSBASE, CX16,
+ABM, BMI, BMI2, FXSR, RDSEED instruction set support.  While the CPUs
+do support AVX and F16C, these aren't enabled by @code{-march=lujiazui}
+for performance reasons.
 
 @item yongfeng
 ZHAOXIN yongfeng CPU with x86-64, MOVBE, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1,