[gcc r14-8192] RISC-V: RVV: add toggle to control vsetvl pass behavior

[Vineet Gupta]

https://gcc.gnu.org/g:7ee7e07d0fb996d9632178f5b9790842096351ae

commit r14-8192-g7ee7e07d0fb996d9632178f5b9790842096351ae
Author: Vineet Gupta <vineetg@rivosinc.com>
Date:   Tue Jan 16 13:17:27 2024 -0800

    RISC-V: RVV: add toggle to control vsetvl pass behavior
    
    RVV requires VSET?VL? instructions to dynamically configure VLEN at
    runtime. There's a custom pass to do that which has a simple mode
    which generates a VSETVL for each V insn and a lazy/optimal mode which
    uses LCM dataflow to move VSETVL around, identify/delete the redundant
    ones.
    
    Currently simple mode is default for !optimize invocations while lazy
    mode being the default.
    
    This patch allows simple mode to be forced via a toggle independent of
    the optimization level. A lot of gcc developers are currently doing this
    in some form in their local setups, as in the initial phase of autovec
    development issues are expected. It makes sense to provide this facility
    upstream. It could potentially also be used by distro builder for any
    quick workarounds in autovec bugs of future.
    
    gcc/ChangeLog:
            * config/riscv/riscv.opt: New -param=vsetvl-strategy.
            * config/riscv/riscv-opts.h: New enum vsetvl_strategy_enum.
            * config/riscv/riscv-vsetvl.cc
            (pre_vsetvl::pre_global_vsetvl_info): Use vsetvl_strategy.
            (pass_vsetvl::execute): Use vsetvl_strategy.
    
    Signed-off-by: Vineet Gupta <vineetg@rivosinc.com>

Diff:
---
 gcc/config/riscv/riscv-opts.h    |  9 +++++++++
 gcc/config/riscv/riscv-vsetvl.cc |  2 +-
 gcc/config/riscv/riscv.opt       | 14 ++++++++++++++
 3 files changed, 24 insertions(+), 1 deletion(-)

diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h
index ff4406ab8ea..ca57dddf1d9 100644
--- a/gcc/config/riscv/riscv-opts.h
+++ b/gcc/config/riscv/riscv-opts.h
@@ -116,6 +116,15 @@ enum stringop_strategy_enum {
   STRATEGY_AUTO = STRATEGY_SCALAR | STRATEGY_VECTOR
 };
 
+/* Behavior of VSETVL Pass.  */
+enum vsetvl_strategy_enum {
+  /* Simple: Insert a vsetvl* instruction for each Vector instruction.  */
+  VSETVL_SIMPLE = 1,
+  /* Optimized: Run LCM dataflow analysis to reduce vsetvl* insns and
+     delete any redundant ones generated in the process.  */
+  VSETVL_OPT = 2
+};
+
 #define TARGET_ZICOND_LIKE (TARGET_ZICOND || (TARGET_XVENTANACONDOPS && TARGET_64BIT))
 
 /* Bit of riscv_zvl_flags will set contintuly, N-1 bit will set if N-bit is
diff --git a/gcc/config/riscv/riscv-vsetvl.cc b/gcc/config/riscv/riscv-vsetvl.cc
index df7ed149388..78a2f7b38fa 100644
--- a/gcc/config/riscv/riscv-vsetvl.cc
+++ b/gcc/config/riscv/riscv-vsetvl.cc
@@ -3671,7 +3671,7 @@ pass_vsetvl::execute (function *)
   if (!has_vector_insn (cfun))
     return 0;
 
-  if (!optimize)
+  if (!optimize || vsetvl_strategy & VSETVL_SIMPLE)
     simple_vsetvl ();
   else
     lazy_vsetvl ();
diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt
index 44ed6d69da2..fd4f1a4df20 100644
--- a/gcc/config/riscv/riscv.opt
+++ b/gcc/config/riscv/riscv.opt
@@ -546,6 +546,20 @@ Target Undocumented Bool Var(riscv_vector_abi) Init(0)
 Enable the use of vector registers for function arguments and return value.
 This is an experimental switch and may be subject to change in the future.
 
+Enum
+Name(vsetvl_strategy) Type(enum vsetvl_strategy_enum)
+Valid arguments to -param=vsetvl-strategy=:
+
+EnumValue
+Enum(vsetvl_strategy) String(simple) Value(VSETVL_SIMPLE)
+
+EnumValue
+Enum(vsetvl_strategy) String(optim) Value(VSETVL_OPT)
+
+-param=vsetvl-strategy=
+Target Undocumented RejectNegative Joined Enum(vsetvl_strategy) Var(vsetvl_strategy) Init(VSETVL_OPT)
+-param=vsetvl-strategy=<string>	Set the optimization level of VSETVL insert pass.
+
 Enum
 Name(stringop_strategy) Type(enum stringop_strategy_enum)
 Valid arguments to -mstringop-strategy=: