[gcc r14-7091] rs6000: Eliminate zext fed by vclzlsbb [PR111480]

[Kewen Lin]

https://gcc.gnu.org/g:6660904c3f5872262f466b5cbbd48fb11e9fe966

commit r14-7091-g6660904c3f5872262f466b5cbbd48fb11e9fe966
Author: Kewen Lin <linkw@linux.ibm.com>
Date:   Tue Jan 9 23:06:13 2024 -0600

    rs6000: Eliminate zext fed by vclzlsbb [PR111480]
    
    As PR111480 shows, commit r14-4079 only optimizes the case
    of vctzlsbb but not for the similar vclzlsbb.  This patch
    is to consider vclzlsbb as well and avoid the failure on
    the reported test case.  It also simplifies the patterns
    with iterator and attribute.
    
            PR target/111480
    
    gcc/ChangeLog:
    
            * config/rs6000/vsx.md (VCZLSBB): New int iterator.
            (vczlsbb_char): New int attribute.
            (vclzlsbb_<mode>, vctzlsbb_<mode>): Merge to ...
            (vc<vczlsbb_char>zlsbb_<mode>): ... this.
            (*vctzlsbb_zext_<mode>): Rename to ...
            (*vc<vczlsbb_char>zlsbb_zext_<mode>): ... this, and extend it to
            cover vclzlsbb.

Diff:
---
 gcc/config/rs6000/vsx.md | 41 ++++++++++++++++++-----------------------
 1 file changed, 18 insertions(+), 23 deletions(-)

diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index 4c1725a7ecd..6111cc90eb7 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -411,6 +411,12 @@
 			   (V2DF  "d")
 			   (V4SF  "w")])
 
+;; Iterator and attribute for vector count leading/trailing
+;; zero least-significant bits byte
+(define_int_iterator VCZLSBB [UNSPEC_VCLZLSBB
+			      UNSPEC_VCTZLSBB])
+(define_int_attr vczlsbb_char [(UNSPEC_VCLZLSBB "l")
+			       (UNSPEC_VCTZLSBB "t")])
 
 ;; VSX moves
 
@@ -5855,35 +5861,24 @@
   "vcmpnezw %0,%1,%2"
   [(set_attr "type" "vecsimple")])
 
-;; Vector Count Leading Zero Least-Significant Bits Byte
-(define_insn "vclzlsbb_<mode>"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(unspec:SI
-	 [(match_operand:VSX_EXTRACT_I 1 "altivec_register_operand" "v")]
-	 UNSPEC_VCLZLSBB))]
-  "TARGET_P9_VECTOR"
-  "vclzlsbb %0,%1"
-  [(set_attr "type" "vecsimple")])
-
-;; Vector Count Trailing Zero Least-Significant Bits Byte
-(define_insn "*vctzlsbb_zext_<mode>"
+;; Vector Count Leading/Trailing Zero Least-Significant Bits Byte
+(define_insn "*vc<vczlsbb_char>zlsbb_zext_<mode>"
   [(set (match_operand:DI 0 "register_operand" "=r")
-	(zero_extend:DI
-	(unspec:SI
-	 [(match_operand:VSX_EXTRACT_I 1 "altivec_register_operand" "v")]
-	 UNSPEC_VCTZLSBB)))]
+	  (zero_extend:DI
+	    (unspec:SI
+	      [(match_operand:VSX_EXTRACT_I 1 "altivec_register_operand" "v")]
+	      VCZLSBB)))]
   "TARGET_P9_VECTOR"
-  "vctzlsbb %0,%1"
+  "vc<vczlsbb_char>zlsbb %0,%1"
   [(set_attr "type" "vecsimple")])
 
-;; Vector Count Trailing Zero Least-Significant Bits Byte
-(define_insn "vctzlsbb_<mode>"
+(define_insn "vc<vczlsbb_char>zlsbb_<mode>"
   [(set (match_operand:SI 0 "register_operand" "=r")
-        (unspec:SI
-         [(match_operand:VSX_EXTRACT_I 1 "altivec_register_operand" "v")]
-         UNSPEC_VCTZLSBB))]
+	  (unspec:SI
+	    [(match_operand:VSX_EXTRACT_I 1 "altivec_register_operand" "v")]
+	    VCZLSBB))]
   "TARGET_P9_VECTOR"
-  "vctzlsbb %0,%1"
+  "vc<vczlsbb_char>zlsbb %0,%1"
   [(set_attr "type" "vecsimple")])
 
 ;; Vector Extract Unsigned Byte Left-Indexed