[gcc(refs/users/meissner/heads/work153-dmf)] PowerPC: Add -mcpu=future.
Michael Meissner
meissner@gcc.gnu.org
Tue Jan 9 17:55:45 GMT 2024
https://gcc.gnu.org/g:dd9450c2d7ab661c745871b0cf93da88cbd98a0b
commit dd9450c2d7ab661c745871b0cf93da88cbd98a0b
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Tue Jan 9 12:46:43 2024 -0500
PowerPC: Add -mcpu=future.
This patch implements support for a potential future PowerPC cpu. Features
added with -mcpu=future, may or may not be added to new PowerPC processors.
This patch adds support for the -mcpu=future option. If you use -mcpu=future,
the macro __ARCH_PWR_FUTURE__ is defined, and the assembler .machine directive
"future" is used. Future patches in this series will add support for new
instructions that may be present in future PowerPC processors.
This particular patch does not any new features. It exists as a ground work
for future patches to support for a possible PowerPC processor in the future.
This patch does not implement any differences in tuning when -mcpu=future is
used compared to -mcpu=power10. If -mcpu=future is used, GCC will use power10
tuning. If you explicitly use -mtune=future, you will get a warning that
-mtune=future is not supported, and default tuning will be set for power10.
The patches have been tested on both little and big endian systems. Can I check
it into the master branch?
2024-01-09 Michael Meissner <meissner@linux.ibm.com>
gcc/
* config/rs6000/rs6000-c.cc (rs6000_target_modify_macros): Define
__ARCH_PWR_FUTURE__ if -mcpu=future.
* config/rs6000/rs6000-cpus.def (ISA_FUTURE_MASKS): New macro.
(POWERPC_MASKS): Add -mcpu=future support.
* config/rs6000/rs6000-opts.h (enum processor_type): Add
PROCESSOR_FUTURE.
* config/rs6000/rs6000-tables.opt: Regenerate.
* config/rs6000/rs6000.cc (rs600_cpu_index_lookup): New helper
function.
(rs6000_option_override_internal): Make -mcpu=future set
-mtune=power10. If the user explicitly uses -mtune=future, give a
warning and reset the tuning to power10.
(rs6000_option_override_internal): Use power10 costs for future
machine.
(rs6000_machine_from_flags): Add support for -mcpu=future.
(rs6000_opt_masks): Likewise.
* config/rs6000/rs6000.h (ASM_CPU_SUPPORT): Likewise.
* config/rs6000/rs6000.md (cpu attribute): Likewise.
* config/rs6000/rs6000.opt (-mfuture): New undocumented debug switch.
* doc/invoke.texi (IBM RS/6000 and PowerPC Options): Document -mcpu=future.
Diff:
---
gcc/ChangeLog.dmf | 149 ++++++++++++++++++++++++++++++++++++
gcc/config/rs6000/rs6000-c.cc | 2 +
gcc/config/rs6000/rs6000-cpus.def | 6 ++
gcc/config/rs6000/rs6000-opts.h | 4 +-
gcc/config/rs6000/rs6000-tables.opt | 3 +
gcc/config/rs6000/rs6000.cc | 58 +++++++++++---
gcc/config/rs6000/rs6000.h | 1 +
gcc/config/rs6000/rs6000.md | 2 +-
gcc/config/rs6000/rs6000.opt | 4 +
gcc/doc/invoke.texi | 2 +-
10 files changed, 218 insertions(+), 13 deletions(-)
diff --git a/gcc/ChangeLog.dmf b/gcc/ChangeLog.dmf
index 48ff92a36fb..0410309d6c9 100644
--- a/gcc/ChangeLog.dmf
+++ b/gcc/ChangeLog.dmf
@@ -1,5 +1,154 @@
+==================== Branch work153-dmf, work153 patch #2 ====================
+
+PR target/112886, Add %S<n> to print_operand for vector pair support.
+
+In looking at support for load vector pair and store vector pair for the
+PowerPC in GCC, I noticed that we were missing a print_operand output modifier
+if you are dealing with vector pairs to print the 2nd register in the vector
+pair.
+
+If the instruction inside of the asm used the Altivec encoding, then we could
+use the %L<n> modifier:
+
+ __vector_pair *p, *q, *r;
+ // ...
+ __asm__ ("vaddudm %0,%1,%2\n\tvaddudm %L0,%L1,%L2"
+ : "=v" (*p)
+ : "v" (*q), "v" (*r));
+
+Likewise if we know the value to be in a tradiational FPR register, %L<n> will
+work for instructions that use the VSX encoding:
+
+ __vector_pair *p, *q, *r;
+ // ...
+ __asm__ ("xvadddp %x0,%x1,%x2\n\txvadddp %L0,%L1,%L2"
+ : "=f" (*p)
+ : "f" (*q), "f" (*r));
+
+But if have a value that is in a traditional Altivec register, and the
+instruction uses the VSX encoding, %L<n> will a value between 0 and 31, when it
+should give a value between 32 and 63.
+
+This patch adds %S<n> that acts like %x<n>, except that it adds 1 to the
+register number.
+
+I have tested this on power10 and power9 little endian systems and on a power9
+big endian system. There were no regressions in the patch. Can I apply it to
+the trunk?
+
+It would be nice if I could apply it to the open branches. Can I backport it
+after a burn-in period?
+
+2024-01-09 Michael Meissner <meissner@linux.ibm.com>
+
+gcc/
+
+ PR target/112886
+ * config/rs6000/rs6000.cc (print_operand): Add %S<n> output modifier.
+ * doc/md.texi (Modifiers): Mention %S can be used like %x.
+
+gcc/testsuite/
+
+ PR target/112886
+ * /gcc.target/powerpc/pr112886.c: New test.
+
+==================== Branch work153-dmf, work153 patch #1 ====================
+
+Power10: Add options to disable load and store vector pair.
+
+This is version 2 of the patch to add -mno-load-vector-pair and
+-mno-store-vector-pair undocumented tuning switches.
+
+The differences between the first version of the patch and this version is that
+I added explicit RTL abi attributes for when the compiler can generate the load
+vector pair and store vector pair instructions. By having this attribute, the
+movoo insn has separate alternatives for when we generate the instruction and
+when we want to split the instruction into 2 separate vector loads or stores.
+
+In the first version of the patch, I had previously provided built-in functions
+that would always generate load vector pair and store vector pair instructions
+even if these instructions are normally disabled. I found these built-ins
+weren't specified like the other vector pair built-ins, and I didn't include
+documentation for the built-in functions. If we want such built-in functions,
+we can add them as a separate patch later.
+
+In addition, since both versions of the patch adds #pragma target and attribute
+support to change the results for individual functions, we can select on a
+function by function basis what the defaults for load/store vector pair is.
+
+The original text for the patch is:
+
+In working on some future patches that involve utilizing vector pair
+instructions, I wanted to be able to tune my program to enable or disable using
+the vector pair load or store operations while still keeping the other
+operations on the vector pair.
+
+This patch adds two undocumented tuning options. The -mno-load-vector-pair
+option would tell GCC to generate two load vector instructions instead of a
+single load vector pair. The -mno-store-vector-pair option would tell GCC to
+generate two store vector instructions instead of a single store vector pair.
+
+If either -mno-load-vector-pair is used, GCC will not generate the indexed
+stxvpx instruction. Similarly if -mno-store-vector-pair is used, GCC will not
+generate the indexed lxvpx instruction. The reason for this is to enable
+splitting the {,p}lxvp or {,p}stxvp instructions after reload without needing a
+scratch GPR register.
+
+The default for -mcpu=power10 is that both load vector pair and store vector
+pair are enabled.
+
+I added code so that the user code can modify these settings using either a
+'#pragma GCC target' directive or used __attribute__((__target__(...))) in the
+function declaration.
+
+I added tests for the switches, #pragma, and attribute options.
+
+I have built this on both little endian power10 systems and big endian power9
+systems doing the normal bootstrap and test. There were no regressions in any
+of the tests, and the new tests passed. Can I check this patch into the master
+branch?
+
+2024-01-09 Michael Meissner <meissner@linux.ibm.com>
+
+gcc/
+
+ * config/rs6000/mma.md (movoo): Add support for -mno-load-vector-pair and
+ -mno-store-vector-pair.
+ * config/rs6000/rs6000-cpus.def (OTHER_POWER10_MASKS): Add support for
+ -mload-vector-pair and -mstore-vector-pair.
+ (POWERPC_MASKS): Likewise.
+ * config/rs6000/rs6000.cc (rs6000_setup_reg_addr_masks): Only allow
+ indexed mode for OOmode if we are generating both load vector pair and
+ store vector pair instructions.
+ (rs6000_option_override_internal): Add support for -mno-load-vector-pair
+ and -mno-store-vector-pair.
+ (rs6000_opt_masks): Likewise.
+ * config/rs6000/rs6000.md (isa attribute): Add lxvp and stxvp
+ attributes.
+ (enabled attribute): Likewise.
+ * config/rs6000/rs6000.opt (-mload-vector-pair): New option.
+ (-mstore-vector-pair): Likewise.
+
+gcc/testsuite/
+
+ * gcc.target/powerpc/vector-pair-attribute.c: New test.
+ * gcc.target/powerpc/vector-pair-pragma.c: New test.
+ * gcc.target/powerpc/vector-pair-switch1.c: New test.
+ * gcc.target/powerpc/vector-pair-switch2.c: New test.
+ * gcc.target/powerpc/vector-pair-switch3.c: New test.
+ * gcc.target/powerpc/vector-pair-switch4.c: New test.
+
==================== Branch work153-dmf, baseline ====================
+Add ChangeLog.dmf and update REVISION.
+
+2024-01-09 Michael Meissner <meissner@linux.ibm.com>
+
+gcc/
+
+ * ChangeLog.dmf: New file for branch.
+ * REVISION: Update.
+
2024-01-09 Michael Meissner <meissner@linux.ibm.com>
Clone branch
diff --git a/gcc/config/rs6000/rs6000-c.cc b/gcc/config/rs6000/rs6000-c.cc
index ce0b14a8d37..f2fb5bef678 100644
--- a/gcc/config/rs6000/rs6000-c.cc
+++ b/gcc/config/rs6000/rs6000-c.cc
@@ -447,6 +447,8 @@ rs6000_target_modify_macros (bool define_p, HOST_WIDE_INT flags)
rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR9");
if ((flags & OPTION_MASK_POWER10) != 0)
rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR10");
+ if ((flags & OPTION_MASK_FUTURE) != 0)
+ rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR_FUTURE");
if ((flags & OPTION_MASK_SOFT_FLOAT) != 0)
rs6000_define_or_undefine_macro (define_p, "_SOFT_FLOAT");
if ((flags & OPTION_MASK_RECIP_PRECISION) != 0)
diff --git a/gcc/config/rs6000/rs6000-cpus.def b/gcc/config/rs6000/rs6000-cpus.def
index d28cc87eb2a..8754635f3d9 100644
--- a/gcc/config/rs6000/rs6000-cpus.def
+++ b/gcc/config/rs6000/rs6000-cpus.def
@@ -88,6 +88,10 @@
| OPTION_MASK_POWER10 \
| OTHER_POWER10_MASKS)
+/* Flags for a potential future processor that may or may not be delivered. */
+#define ISA_FUTURE_MASKS (ISA_3_1_MASKS_SERVER \
+ | OPTION_MASK_FUTURE)
+
/* Flags that need to be turned off if -mno-power9-vector. */
#define OTHER_P9_VECTOR_MASKS (OPTION_MASK_FLOAT128_HW \
| OPTION_MASK_P9_MINMAX)
@@ -135,6 +139,7 @@
| OPTION_MASK_LOAD_VECTOR_PAIR \
| OPTION_MASK_POWER10 \
| OPTION_MASK_P10_FUSION \
+ | OPTION_MASK_FUTURE \
| OPTION_MASK_HTM \
| OPTION_MASK_ISEL \
| OPTION_MASK_MFCRF \
@@ -267,3 +272,4 @@ RS6000_CPU ("powerpc64", PROCESSOR_POWERPC64, OPTION_MASK_PPC_GFXOPT
RS6000_CPU ("powerpc64le", PROCESSOR_POWER8, MASK_POWERPC64
| ISA_2_7_MASKS_SERVER | OPTION_MASK_HTM)
RS6000_CPU ("rs64", PROCESSOR_RS64A, OPTION_MASK_PPC_GFXOPT | MASK_POWERPC64)
+RS6000_CPU ("future", PROCESSOR_FUTURE, MASK_POWERPC64 | ISA_FUTURE_MASKS)
diff --git a/gcc/config/rs6000/rs6000-opts.h b/gcc/config/rs6000/rs6000-opts.h
index 33fd0efc936..25890ae3034 100644
--- a/gcc/config/rs6000/rs6000-opts.h
+++ b/gcc/config/rs6000/rs6000-opts.h
@@ -67,7 +67,9 @@ enum processor_type
PROCESSOR_MPCCORE,
PROCESSOR_CELL,
PROCESSOR_PPCA2,
- PROCESSOR_TITAN
+ PROCESSOR_TITAN,
+
+ PROCESSOR_FUTURE
};
diff --git a/gcc/config/rs6000/rs6000-tables.opt b/gcc/config/rs6000/rs6000-tables.opt
index 65f46709716..97fa98a2e65 100644
--- a/gcc/config/rs6000/rs6000-tables.opt
+++ b/gcc/config/rs6000/rs6000-tables.opt
@@ -197,3 +197,6 @@ Enum(rs6000_cpu_opt_value) String(powerpc64le) Value(55)
EnumValue
Enum(rs6000_cpu_opt_value) String(rs64) Value(56)
+EnumValue
+Enum(rs6000_cpu_opt_value) String(future) Value(57)
+
diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index 6353a7ccfb2..3dc312318db 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -1809,6 +1809,18 @@ rs6000_cpu_name_lookup (const char *name)
return -1;
}
+/* Look up the index for a specific processor. */
+
+static int
+rs600_cpu_index_lookup (enum processor_type processor)
+{
+ for (size_t i = 0; i < ARRAY_SIZE (processor_target_table); i++)
+ if (processor_target_table[i].processor == processor)
+ return i;
+
+ return -1;
+}
+
/* Return number of consecutive hard regs needed starting at reg REGNO
to hold something of mode MODE.
@@ -3756,23 +3768,45 @@ rs6000_option_override_internal (bool global_init_p)
rs6000_isa_flags &= ~OPTION_MASK_POWERPC64;
#endif
+ /* At the moment, we don't have explict -mtune=future support. If the user
+ explicitly tried to use -mtune=future, give a warning. If not, use the
+ power10 tuning until future tuning is added. */
if (rs6000_tune_index >= 0)
- tune_index = rs6000_tune_index;
+ {
+ enum processor_type cur_proc
+ = processor_target_table[rs6000_tune_index].processor;
+
+ if (cur_proc == PROCESSOR_FUTURE)
+ {
+ static bool issued_future_tune_warning = false;
+ if (!issued_future_tune_warning)
+ {
+ issued_future_tune_warning = true;
+ warning (0, "%qs is not currently supported", "-mtune=future");
+ }
+
+ rs6000_tune_index = rs600_cpu_index_lookup (PROCESSOR_POWER10);
+ }
+ tune_index = rs6000_tune_index;
+ }
else if (cpu_index >= 0)
- rs6000_tune_index = tune_index = cpu_index;
+ {
+ enum processor_type cur_cpu
+ = processor_target_table[cpu_index].processor;
+
+ rs6000_tune_index = tune_index
+ = (cur_cpu == PROCESSOR_FUTURE
+ ? rs600_cpu_index_lookup (PROCESSOR_POWER10)
+ : cpu_index);
+ }
else
{
- size_t i;
enum processor_type tune_proc
= (TARGET_POWERPC64 ? PROCESSOR_DEFAULT64 : PROCESSOR_DEFAULT);
- tune_index = -1;
- for (i = 0; i < ARRAY_SIZE (processor_target_table); i++)
- if (processor_target_table[i].processor == tune_proc)
- {
- tune_index = i;
- break;
- }
+ tune_index = rs600_cpu_index_lookup (tune_proc == PROCESSOR_FUTURE
+ ? PROCESSOR_POWER10
+ : tune_proc);
}
if (cpu_index >= 0)
@@ -4785,6 +4819,7 @@ rs6000_option_override_internal (bool global_init_p)
break;
case PROCESSOR_POWER10:
+ case PROCESSOR_FUTURE:
rs6000_cost = &power10_cost;
break;
@@ -5944,6 +5979,8 @@ rs6000_machine_from_flags (void)
/* Disable the flags that should never influence the .machine selection. */
flags &= ~(OPTION_MASK_PPC_GFXOPT | OPTION_MASK_PPC_GPOPT | OPTION_MASK_ISEL);
+ if ((flags & (ISA_FUTURE_MASKS & ~ISA_3_1_MASKS_SERVER)) != 0)
+ return "future";
if ((flags & (ISA_3_1_MASKS_SERVER & ~ISA_3_0_MASKS_SERVER)) != 0)
return "power10";
if ((flags & (ISA_3_0_MASKS_SERVER & ~ISA_2_7_MASKS_SERVER)) != 0)
@@ -24504,6 +24541,7 @@ static struct rs6000_opt_mask const rs6000_opt_masks[] =
{ "float128-hardware", OPTION_MASK_FLOAT128_HW, false, true },
{ "fprnd", OPTION_MASK_FPRND, false, true },
{ "power10", OPTION_MASK_POWER10, false, true },
+ { "future", OPTION_MASK_FUTURE, false, true },
{ "hard-dfp", OPTION_MASK_DFP, false, true },
{ "htm", OPTION_MASK_HTM, false, true },
{ "isel", OPTION_MASK_ISEL, false, true },
diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h
index 2291fe8d3a3..43209f9a6e7 100644
--- a/gcc/config/rs6000/rs6000.h
+++ b/gcc/config/rs6000/rs6000.h
@@ -163,6 +163,7 @@
mcpu=e5500: -me5500; \
mcpu=e6500: -me6500; \
mcpu=titan: -mtitan; \
+ mcpu=future: -mfuture; \
!mcpu*: %{mpower9-vector: -mpower9; \
mpower8-vector|mcrypto|mdirect-move|mhtm: -mpower8; \
mvsx: -mpower7; \
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 969d34b69e6..a125fd8fc99 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -351,7 +351,7 @@
ppc403,ppc405,ppc440,ppc476,
ppc8540,ppc8548,ppce300c2,ppce300c3,ppce500mc,ppce500mc64,ppce5500,ppce6500,
power4,power5,power6,power7,power8,power9,power10,
- rs64a,mpccore,cell,ppca2,titan"
+ rs64a,mpccore,cell,ppca2,titan,future"
(const (symbol_ref "(enum attr_cpu) rs6000_tune")))
;; The ISA we implement.
diff --git a/gcc/config/rs6000/rs6000.opt b/gcc/config/rs6000/rs6000.opt
index 60b923f5e4b..775ba830eac 100644
--- a/gcc/config/rs6000/rs6000.opt
+++ b/gcc/config/rs6000/rs6000.opt
@@ -628,6 +628,10 @@ mieee128-constant
Target Var(TARGET_IEEE128_CONSTANT) Init(1) Save
Generate (do not generate) code that uses the LXVKQ instruction.
+mfuture
+Target Undocumented Mask(FUTURE) Var(rs6000_isa_flags)
+Generate (do not generate) future instructions.
+
; Documented parameters
-param=rs6000-vect-unroll-limit=
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index a494420e24e..e4762286047 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -30432,7 +30432,7 @@ Supported values for @var{cpu_type} are @samp{401}, @samp{403},
@samp{titan}, @samp{power3}, @samp{power4}, @samp{power5}, @samp{power5+},
@samp{power6}, @samp{power6x}, @samp{power7}, @samp{power8},
@samp{power9}, @samp{power10}, @samp{powerpc}, @samp{powerpc64},
-@samp{powerpc64le}, @samp{rs64}, and @samp{native}.
+@samp{powerpc64le}, @samp{rs64}, @samp{future}, and @samp{native}.
@option{-mcpu=powerpc}, @option{-mcpu=powerpc64}, and
@option{-mcpu=powerpc64le} specify pure 32-bit PowerPC (either
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