[gcc r14-6914] Revert "RISC-V: Make liveness estimation be aware of .vi variant"

[Pan Li]

https://gcc.gnu.org/g:4831ad982c08a7d926263666c62cd6e52674f885

commit r14-6914-g4831ad982c08a7d926263666c62cd6e52674f885
Author: Pan Li <pan2.li@intel.com>
Date:   Thu Jan 4 18:17:38 2024 +0800

    Revert "RISC-V: Make liveness estimation be aware of .vi variant"
    
    This reverts commit b1342247a44c410ad6a44dfd82813fafe2ea7c1d.

Diff:
---
 gcc/config/riscv/riscv-vector-costs.cc             | 30 ++-------
 .../vect/costmodel/riscv/rvv/dynamic-lmul8-13.c    | 74 ----------------------
 2 files changed, 7 insertions(+), 97 deletions(-)

diff --git a/gcc/config/riscv/riscv-vector-costs.cc b/gcc/config/riscv/riscv-vector-costs.cc
index e4435032035..21f8a81c89c 100644
--- a/gcc/config/riscv/riscv-vector-costs.cc
+++ b/gcc/config/riscv/riscv-vector-costs.cc
@@ -255,29 +255,6 @@ variable_vectorized_p (stmt_vec_info stmt_info, tree var, bool lhs_p)
 	    return false;
 	}
     }
-  else if (is_gimple_assign (stmt))
-    {
-      tree_code tcode = gimple_assign_rhs_code (stmt);
-      /* vi variant doesn't need to allocate such statement.
-	 E.g. tmp_15 = _4 + 1; will be transformed into vadd.vi
-	 so the INTEGER_CST '1' doesn't need a vector register.  */
-      switch (tcode)
-	{
-	case PLUS_EXPR:
-	case BIT_IOR_EXPR:
-	case BIT_XOR_EXPR:
-	case BIT_AND_EXPR:
-	  return TREE_CODE (var) != INTEGER_CST
-		 || !IN_RANGE (tree_to_shwi (var), -16, 15);
-	case MINUS_EXPR:
-	  return TREE_CODE (var) != INTEGER_CST
-		 || !IN_RANGE (tree_to_shwi (var), -16, 15)
-		 || gimple_assign_rhs1 (stmt) != var;
-	default:
-	  break;
-	}
-    }
-
   if (lhs_p)
     return is_gimple_reg (var)
 	   && (!POINTER_TYPE_P (TREE_TYPE (var))
@@ -354,6 +331,13 @@ compute_local_live_ranges (
 	      for (i = 0; i < gimple_num_args (stmt); i++)
 		{
 		  tree var = gimple_arg (stmt, i);
+		  /* Both IMM and REG are included since a VECTOR_CST may be
+		     potentially held in a vector register.  However, it's not
+		     accurate, since a PLUS_EXPR can be vectorized into vadd.vi
+		     if IMM is -16 ~ 15.
+
+		     TODO: We may elide the cases that the unnecessary IMM in
+		     the future.  */
 		  if (variable_vectorized_p (program_point.stmt_info, var,
 					     false))
 		    {
diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul8-13.c b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul8-13.c
deleted file mode 100644
index baef4e39014..00000000000
--- a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul8-13.c
+++ /dev/null
@@ -1,74 +0,0 @@
-/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize --param riscv-autovec-lmul=dynamic -fdump-tree-vect-details" } */
-
-void
-f (int *restrict a, int *restrict b, int *restrict c, int *restrict d, int n)
-{
-  for (int i = 0; i < n; i++)
-    {
-      int tmp = b[i] + 15;
-      int tmp2 = tmp + b[i];
-      c[i] = tmp2 + b[i];
-      d[i] = tmp + tmp2 + b[i];
-    }
-}
-
-void
-f2 (int *restrict a, int *restrict b, int *restrict c, int *restrict d, int n)
-{
-  for (int i = 0; i < n; i++)
-    {
-      int tmp = 15 - b[i];
-      int tmp2 = tmp * b[i];
-      c[i] = tmp2 * b[i];
-      d[i] = tmp * tmp2 * b[i];
-    }
-}
-
-void
-f3 (int *restrict a, int *restrict b, int *restrict c, int *restrict d, int n)
-{
-  for (int i = 0; i < n; i++)
-    {
-      int tmp = b[i] & 15;
-      int tmp2 = tmp * b[i];
-      c[i] = tmp2 * b[i];
-      d[i] = tmp * tmp2 * b[i];
-    }
-}
-
-void
-f4 (int *restrict a, int *restrict b, int *restrict c, int *restrict d, int n)
-{
-  for (int i = 0; i < n; i++)
-    {
-      int tmp = b[i] | 15;
-      int tmp2 = tmp * b[i];
-      c[i] = tmp2 * b[i];
-      d[i] = tmp * tmp2 * b[i];
-    }
-}
-
-void
-f5 (int *restrict a, int *restrict b, int *restrict c, int *restrict d, int n)
-{
-  for (int i = 0; i < n; i++)
-    {
-      int tmp = b[i] ^ 15;
-      int tmp2 = tmp * b[i];
-      c[i] = tmp2 * b[i];
-      d[i] = tmp * tmp2 * b[i];
-    }
-}
-
-/* { dg-final { scan-assembler-times {e32,m8} 5 } } */
-/* { dg-final { scan-assembler-not {csrr} } } */
-/* { dg-final { scan-assembler-not {jr} } } */
-/* { dg-final { scan-assembler-not {e32,m4} } } */
-/* { dg-final { scan-assembler-not {e32,m2} } } */
-/* { dg-final { scan-assembler-not {e32,m1} } } */
-/* { dg-final { scan-assembler-times {ret} 5 } } */
-/* { dg-final { scan-tree-dump-not "Preferring smaller LMUL loop because it has unexpected spills" "vect" } } */
-/* { dg-final { scan-tree-dump-times "Maximum lmul = 8" 5 "vect" } } */
-/* { dg-final { scan-tree-dump-times "Maximum lmul = 4" 5 "vect" } } */
-/* { dg-final { scan-tree-dump-times "Maximum lmul = 2" 5 "vect" } } */