[gcc r14-3828] RISC-V: Avoid unnecessary slideup in compress pattern of vec_perm

[Pan Li]

https://gcc.gnu.org/g:e390872aebcfebb7c9bc95d8fb7e44f2bec996d3

commit r14-3828-ge390872aebcfebb7c9bc95d8fb7e44f2bec996d3
Author: Juzhe-Zhong <juzhe.zhong@rivai.ai>
Date:   Sun Sep 10 22:07:10 2023 +0800

    RISC-V: Avoid unnecessary slideup in compress pattern of vec_perm
    
    gcc/ChangeLog:
    
            * config/riscv/riscv-v.cc (shuffle_compress_patterns): Avoid unnecessary slideup.

Diff:
---
 gcc/config/riscv/riscv-v.cc | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
index 1ca3f1dc8df5..8a548f5d1a27 100644
--- a/gcc/config/riscv/riscv-v.cc
+++ b/gcc/config/riscv/riscv-v.cc
@@ -2647,7 +2647,8 @@ shuffle_compress_patterns (struct expand_vec_perm_d *d)
 
 	    For index = { 0, 2, 5, 6}, we need to slide op1 up before
 	    we apply compress approach.  */
-  bool need_slideup_p = maybe_ne (d->perm[vlen - 1], 2 * vec_len - 1);
+  bool need_slideup_p = maybe_ne (d->perm[vlen - 1], 2 * vec_len - 1)
+			&& !const_vec_duplicate_p (d->op1);
 
   /* If we leave it directly be handled by general gather,
      the code sequence will be: