[gcc/egallager/heads/CI] (81 commits) Merge branch 'me/CI' of github.com:cooljeanius/gcc into me/

[Eric Gallager]

The branch 'egallager/heads/CI' was updated to point to:

 0b38d181dea8... Merge branch 'me/CI' of github.com:cooljeanius/gcc into me/

It previously pointed to:

 d38fe5f4c4cf... Update linux.yaml

Diff:

Summary of changes (added commits):
-----------------------------------

  0b38d18... Merge branch 'me/CI' of github.com:cooljeanius/gcc into me/
  a9b9ba3... Update linux.yaml
  3ab36d8... Merge branch 'TalR/gcc_ci_cooljeanius' into me/CI
  59d859a... Add linux ci
  0308461... Daily bump. (*)
  b20dbdd... Fix expansion of `(a & 2) != 1` (*)
  879c91f... [c] Fix PR 101364: ICE after error due to diagnose_arglist_ (*)
  11e6bce... Fix ICE due to c_safe_arg_type_equiv_p not checking for err (*)
  3ec8ecb... PR111648: Fix wrong code-gen due to incorrect VEC_PERM_EXPR (*)
  fe9767e... pru: Implement TARGET_INSN_COST (*)
  67f7bf7... LibF7: Implement mul_mant for devices without MUL instructi (*)
  ff05a3e... aarch64: Replace duplicated selftests (*)
  bc4bd69... cse: Workaround GCC < 5 bug in cse_insn [PR111852] (*)
  ef10cb8... diagnostic: add permerror variants with opt (*)
  af4bb22... OpenMP: Avoid ICE with LTO and 'omp allocate' (*)
  f1744dd... tree-ssa-math-opts: Fix up match_uaddc_usubc [PR111845] (*)
  d396176... nvptx: Use fatal_error when -march= is missing not an asser (*)
  a4184c8... Darwin: Check as for .build_version support and use it if a (*)
  dd28f90... ifcvt: rewrite args handling to remove lookups (*)
  04227ac... AArch64: Rewrite simd move immediate patterns to new syntax (*)
  b0fe8f2... middle-end: ifcvt: Allow any const IFN in conditional block (*)
  4b39aee... middle-end: Fold vec_cond into conditional ternary or binar (*)
  b588dcb... LoongArch: Use fcmp.caf.s instead of movgr2cf for zeroing a (*)
  b0372ef... Re-instantiate integer mask to traditional vector mask supp (*)
  60c231c... middle-end: maintain LCSSA throughout loop peeling (*)
  0c85228... middle-end: updated niters analysis to handle multiple exit (*)
  d65e38e... middle-end: Refactor vectorizer loop conditionals and separ (*)
  46937e1... middle-end: refactor vectorizable_comparison to make the ma (*)
  c51040c... RISC-V: Optimize consecutive permutation index pattern by v (*)
  372c5da... fortran/intrinsic.texi: Add 'intrinsic' to SIGNAL example (*)
  f019251... Initial Panther Lake Support (*)
  2aa97c0... x86: Add m_CORE_HYBRID for hybrid clients tuning (*)
  7370c47... Initial Clearwater Forest Support (*)
  cead92b... Support 32/64-bit vectorization for _Float16 fma related op (*)
  cf7739d... RISC-V: Enable more tests for dynamic LMUL and bug fix[PR11 (*)
  fb69acf... Daily bump. (*)
  773306e... aarch64: Put LR save slot first in more cases (*)
  5758585... aarch64: Use vecs to store register save order (*)
  aeb3f04... Handle epilogues that contain jumps (*)
  5e4abf4... ssa_name_has_boolean_range vs signed-boolean:31 types (*)
  1fbb7d7... c++: accepts-invalid with =delete("") [PR111840] (*)
  765c3b8... c++: Fix compile-time-hog in cp_fold_immediate_r [PR111660] (*)
  bac21b7... c++: mangling tweaks (*)
  4f87000... c++: Add missing auto_diagnostic_groups to constexpr.cc (*)
  9cad427... RISC-V/testsuite/pr111466.c: update test and expected outpu (*)
  1f186f6... c: error for function with external and internal linkage [P (*)
  5ac63ec... Fortran: out of bounds access with nested implied-do IO [PR (*)
  43c2f85... fortran/intrinsic.texi: Improve SIGNAL intrinsic entry (*)
  b18d1ca... MATCH: [PR111432] Simplify `a & (x | CST)` to a when we kno (*)
  da65efe... LibF7: Re-generate f7-renames.h to pick up white-space from (*)
  305034e... tree-cfg: Add count information when creating new bb in mov (*)
  ef6696a... PR modula2/111756: Re-building all-gcc after source changes (*)
  323209c... tree-optimization/111846 - put simd-clone-info into SLP tre (*)
  fbdf88a... wide-int-print: Don't print large numbers hexadecimally for (*)
  5bb79a4... RISC-V: Fix failed testcase when use -cmodel=medany (*)
  c4e773b... LibF7: Implement fma / fmal. (*)
  ce55521... middle-end/111818 - failed DECL_NOT_GIMPLE_REG_P setting of (*)
  3aaf704... tree-optimization/111807 - ICE in verify_sra_access_forest (*)
  8eb9cdd... expr: don't clear SUBREG_PROMOTED_VAR_P flag for a promoted (*)
  38ad4ad... LoongArch: Fix vec_initv32qiv16qi template to avoid ICE. (*)
  7b93be5... Merge branch 'gcc-mirror:master' into me/CI
  b20c7ee... LoongArch: Delete macro definition ASM_OUTPUT_ALIGN_WITH_NO (*)
  b25b43c... RISC-V: Fix unexpected big LMUL choosing in dynamic LMUL mo (*)
  ef8f7e3... d: Forbid taking the address of an intrinsic with no implem (*)
  e16ace7... Daily bump. (*)
  b626751... Fix minor problem in stack probing (*)
  04013e4... diagnostics: special-case -fdiagnostics-text-art-charset=as (*)
  f8644b6... diagnostics: fix missing initialization of context->extra_o (*)
  1a64156... i386: Allow -mlarge-data-threshold with -mcmodel=large (*)
  3287456... RISC-V: NFC: Move scalar block move expansion code into ris (*)
  c927377... RISC-V/testsuite: add a default march (lacking zfa) to some (*)
  04c9cf5... Implement new RTL optimizations pass: fold-mem-offsets (*)
  964fd40... d: Merge upstream dmd, druntime 4c18eed967, phobos d945686a (*)
  c7609ac... MATCH: Improve `A CMP 0 ? A : -A` set of patterns to use bi (*)
  29a4453... [PR31531] MATCH: Improve ~a < ~b and ~a < CST, allow a nop  (*)
  7550130... c++: improve fold-expr location (*)
  a22eeac... c++: fix truncated diagnostic in C++23 [PR111272] (*)
  817a701... ARC: Split asl dst,1,src into bset dst,0,src to implement 1 (*)
  d6ebe61... s390: Fix expander popcountv8hi2_vx (*)
  a5fe9f0... RISC-V: Use VLS modes if the NITERS is known and smaller th (*)
  b7a28c0... use more get_range_query (*)

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