[gcc(refs/users/meissner/heads/work138)] Revert patches
Michael Meissner
meissner@gcc.gnu.org
Mon Oct 9 16:08:59 GMT 2023
https://gcc.gnu.org/g:00bb555efa95c8cadba6cc847f90e7dd7aae7326
commit 00bb555efa95c8cadba6cc847f90e7dd7aae7326
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Mon Oct 9 12:08:55 2023 -0400
Revert patches
Diff:
---
gcc/config/rs6000/mma.md | 17 ++-----
gcc/config/rs6000/rs6000-cpus.def | 8 +---
gcc/config/rs6000/rs6000.cc | 30 +-----------
gcc/config/rs6000/rs6000.opt | 8 ----
.../gcc.target/powerpc/vector-pair-attribute.c | 39 ---------------
.../gcc.target/powerpc/vector-pair-pragma.c | 55 ----------------------
.../gcc.target/powerpc/vector-pair-switch1.c | 16 -------
.../gcc.target/powerpc/vector-pair-switch2.c | 17 -------
.../gcc.target/powerpc/vector-pair-switch3.c | 17 -------
.../gcc.target/powerpc/vector-pair-switch4.c | 17 -------
10 files changed, 9 insertions(+), 215 deletions(-)
diff --git a/gcc/config/rs6000/mma.md b/gcc/config/rs6000/mma.md
index b6cc7b28956..575751d477e 100644
--- a/gcc/config/rs6000/mma.md
+++ b/gcc/config/rs6000/mma.md
@@ -298,19 +298,12 @@
"TARGET_MMA
&& (gpc_reg_operand (operands[0], OOmode)
|| gpc_reg_operand (operands[1], OOmode))"
-{
- if (MEM_P (operands[0]))
- return TARGET_STORE_VECTOR_PAIR ? "stxvp%X0 %x1,%0" : "#";
-
- if (MEM_P (operands[1]))
- return TARGET_LOAD_VECTOR_PAIR ? "lxvp%X1 %x0,%1" : "#";
-
- return "#";
-}
+ "@
+ lxvp%X1 %x0,%1
+ stxvp%X0 %x1,%0
+ #"
"&& reload_completed
- && ((MEM_P (operands[0]) && !TARGET_STORE_VECTOR_PAIR)
- || (MEM_P (operands[1]) && !TARGET_LOAD_VECTOR_PAIR)
- || (!MEM_P (operands[0]) && !MEM_P (operands[1])))"
+ && (!MEM_P (operands[0]) && !MEM_P (operands[1]))"
[(const_int 0)]
{
rs6000_split_multireg_move (operands[0], operands[1]);
diff --git a/gcc/config/rs6000/rs6000-cpus.def b/gcc/config/rs6000/rs6000-cpus.def
index 8c530a22da8..4f350da378c 100644
--- a/gcc/config/rs6000/rs6000-cpus.def
+++ b/gcc/config/rs6000/rs6000-cpus.def
@@ -77,12 +77,10 @@
/* Flags that need to be turned off if -mno-power10. */
/* We comment out PCREL_OPT here to disable it by default because SPEC2017
performance was degraded by it. */
-#define OTHER_POWER10_MASKS (OPTION_MASK_LOAD_VECTOR_PAIR \
- | OPTION_MASK_MMA \
+#define OTHER_POWER10_MASKS (OPTION_MASK_MMA \
| OPTION_MASK_PCREL \
/* | OPTION_MASK_PCREL_OPT */ \
- | OPTION_MASK_PREFIXED \
- | OPTION_MASK_STORE_VECTOR_PAIR)
+ | OPTION_MASK_PREFIXED)
#define ISA_3_1_MASKS_SERVER (ISA_3_0_MASKS_SERVER \
| OPTION_MASK_POWER10 \
@@ -136,7 +134,6 @@
| OPTION_MASK_P10_FUSION \
| OPTION_MASK_HTM \
| OPTION_MASK_ISEL \
- | OPTION_MASK_LOAD_VECTOR_PAIR \
| OPTION_MASK_MFCRF \
| OPTION_MASK_MMA \
| OPTION_MASK_MODULO \
@@ -159,7 +156,6 @@
| OPTION_MASK_QUAD_MEMORY_ATOMIC \
| OPTION_MASK_RECIP_PRECISION \
| OPTION_MASK_SOFT_FLOAT \
- | OPTION_MASK_STORE_VECTOR_PAIR \
| OPTION_MASK_STRICT_ALIGN_OPTIONAL \
| OPTION_MASK_VSX)
diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index 39ec2257b05..cc9253bb040 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -2711,9 +2711,7 @@ rs6000_setup_reg_addr_masks (void)
/* Vector pairs can do both indexed and offset loads if the
instructions are enabled, otherwise they can only do offset loads
since it will be broken into two vector moves. Vector quads can
- only do offset loads. If the user restricted generation of either
- of the LXVP or STXVP instructions, do not allow indexed mode so
- that we can split the load/store. */
+ only do offset loads. */
else if ((addr_mask != 0) && TARGET_MMA
&& (m2 == OOmode || m2 == XOmode))
{
@@ -2721,9 +2719,7 @@ rs6000_setup_reg_addr_masks (void)
if (rc == RELOAD_REG_FPR || rc == RELOAD_REG_VMX)
{
addr_mask |= RELOAD_REG_QUAD_OFFSET;
- if (m2 == OOmode
- && TARGET_LOAD_VECTOR_PAIR
- && TARGET_STORE_VECTOR_PAIR)
+ if (m2 == OOmode)
addr_mask |= RELOAD_REG_INDEXED;
}
}
@@ -4409,26 +4405,6 @@ rs6000_option_override_internal (bool global_init_p)
rs6000_isa_flags &= ~OPTION_MASK_MMA;
}
- /* Warn if -m-load-vector-pair or -m-store-vector-pair are used and MMA is
- not set. */
- if (!TARGET_MMA && TARGET_LOAD_VECTOR_PAIR)
- {
- if ((rs6000_isa_flags_explicit & OPTION_MASK_LOAD_VECTOR_PAIR) != 0)
- warning (0, "%qs should not be used unless you use %qs",
- "-mload-vector-pair", "-mmma");
-
- rs6000_isa_flags &= ~OPTION_MASK_LOAD_VECTOR_PAIR;
- }
-
- if (!TARGET_MMA && TARGET_STORE_VECTOR_PAIR)
- {
- if ((rs6000_isa_flags_explicit & OPTION_MASK_STORE_VECTOR_PAIR) != 0)
- warning (0, "%qs should not be used unless you use %qs",
- "-mstore-vector-pair", "-mmma");
-
- rs6000_isa_flags &= OPTION_MASK_STORE_VECTOR_PAIR;
- }
-
/* Enable power10 fusion if we are tuning for power10, even if we aren't
generating power10 instructions. */
if (!(rs6000_isa_flags_explicit & OPTION_MASK_P10_FUSION))
@@ -24253,7 +24229,6 @@ static struct rs6000_opt_mask const rs6000_opt_masks[] =
{ "hard-dfp", OPTION_MASK_DFP, false, true },
{ "htm", OPTION_MASK_HTM, false, true },
{ "isel", OPTION_MASK_ISEL, false, true },
- { "load-vector-pair", OPTION_MASK_LOAD_VECTOR_PAIR, false, true },
{ "mfcrf", OPTION_MASK_MFCRF, false, true },
{ "mfpgpr", 0, false, true },
{ "mma", OPTION_MASK_MMA, false, true },
@@ -24278,7 +24253,6 @@ static struct rs6000_opt_mask const rs6000_opt_masks[] =
{ "quad-memory-atomic", OPTION_MASK_QUAD_MEMORY_ATOMIC, false, true },
{ "recip-precision", OPTION_MASK_RECIP_PRECISION, false, true },
{ "save-toc-indirect", OPTION_MASK_SAVE_TOC_INDIRECT, false, true },
- { "store-vector-pair", OPTION_MASK_STORE_VECTOR_PAIR, false, true },
{ "string", 0, false, true },
{ "update", OPTION_MASK_NO_UPDATE, true , true },
{ "vsx", OPTION_MASK_VSX, false, true },
diff --git a/gcc/config/rs6000/rs6000.opt b/gcc/config/rs6000/rs6000.opt
index 369095df9ed..bde6d3ff664 100644
--- a/gcc/config/rs6000/rs6000.opt
+++ b/gcc/config/rs6000/rs6000.opt
@@ -597,14 +597,6 @@ mmma
Target Mask(MMA) Var(rs6000_isa_flags)
Generate (do not generate) MMA instructions.
-mload-vector-pair
-Target Undocumented Mask(LOAD_VECTOR_PAIR) Var(rs6000_isa_flags)
-Generate (do not generate) load vector pair instructions.
-
-mstore-vector-pair
-Target Undocumented Mask(STORE_VECTOR_PAIR) Var(rs6000_isa_flags)
-Generate (do not generate) store vector pair instructions.
-
mrelative-jumptables
Target Undocumented Var(rs6000_relative_jumptables) Init(1) Save
diff --git a/gcc/testsuite/gcc.target/powerpc/vector-pair-attribute.c b/gcc/testsuite/gcc.target/powerpc/vector-pair-attribute.c
deleted file mode 100644
index 985a44aca85..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vector-pair-attribute.c
+++ /dev/null
@@ -1,39 +0,0 @@
-/* { dg-do compile } */
-/* { dg-require-effective-target power10_ok } */
-/* { dg-options "-mdejagnu-cpu=power10 -O2" } */
-
-/* Test if we can control generating load and store vector pair via the target
- attribute. */
-
-__attribute__((__target__("load-vector-pair,store-vector-pair")))
-void
-test_load_store (__vector_pair *p, __vector_pair *q)
-{
- *p = *q; /* 1 lxvp, 1 stxvp. */
-}
-
-__attribute__((__target__("load-vector-pair,no-store-vector-pair")))
-void
-test_load_no_store (__vector_pair *p, __vector_pair *q)
-{
- *p = *q; /* 1 lxvp, 2 stxv. */
-}
-
-__attribute__((__target__("no-load-vector-pair,store-vector-pair")))
-void
-test_store_no_load (__vector_pair *p, __vector_pair *q)
-{
- *p = *q; /* 2 lxv, 1 stxvp. */
-}
-
-__attribute__((__target__("no-load-vector-pair,no-store-vector-pair")))
-void
-test_no_load_or_store (__vector_pair *p, __vector_pair *q)
-{
- *p = *q; /* 2 lxv, 2 stxv. */
-}
-
-/* { dg-final { scan-assembler-times {\mp?lxvpx?\M} 2 } } */
-/* { dg-final { scan-assembler-times {\mp?stxvpx?\M} 2 } } */
-/* { dg-final { scan-assembler-times {\mp?lxvx?\M} 4 } } */
-/* { dg-final { scan-assembler-times {\mp?stxvx?\M} 4 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vector-pair-pragma.c b/gcc/testsuite/gcc.target/powerpc/vector-pair-pragma.c
deleted file mode 100644
index 74c6baf8185..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vector-pair-pragma.c
+++ /dev/null
@@ -1,55 +0,0 @@
-/* { dg-do compile } */
-/* { dg-require-effective-target power10_ok } */
-/* { dg-options "-mdejagnu-cpu=power10 -O2" } */
-
-/* Test if we can control generating load and store vector pair via the #pragma
- directive. */
-
-#pragma gcc push_options
-#pragma GCC target("load-vector-pair,store-vector-pair")
-
-void
-test_load_store (__vector_pair *p, __vector_pair *q)
-{
- *p = *q; /* 1 lxvp, 1 stxvp. */
-}
-
-#pragma gcc pop_options
-
-#pragma gcc push_options
-#pragma GCC target("load-vector-pair,no-store-vector-pair")
-
-void
-test_load_no_store (__vector_pair *p, __vector_pair *q)
-{
- *p = *q; /* 1 lxvp, 2 stxv. */
-}
-
-#pragma gcc pop_options
-
-#pragma gcc push_options
-#pragma GCC target("no-load-vector-pair,store-vector-pair")
-
-void
-test_store_no_load (__vector_pair *p, __vector_pair *q)
-{
- *p = *q; /* 2 lxv, 1 stxvp. */
-}
-
-#pragma gcc pop_options
-
-#pragma gcc push_options
-#pragma GCC target("no-load-vector-pair,no-store-vector-pair")
-
-void
-test_no_load_or_store (__vector_pair *p, __vector_pair *q)
-{
- *p = *q; /* 2 lxv, 2 stxv. */
-}
-
-#pragma gcc pop_options
-
-/* { dg-final { scan-assembler-times {\mp?lxvpx?\M} 2 } } */
-/* { dg-final { scan-assembler-times {\mp?stxvpx?\M} 2 } } */
-/* { dg-final { scan-assembler-times {\mp?lxvx?\M} 4 } } */
-/* { dg-final { scan-assembler-times {\mp?stxvx?\M} 4 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vector-pair-switch1.c b/gcc/testsuite/gcc.target/powerpc/vector-pair-switch1.c
deleted file mode 100644
index 5b575e7befa..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vector-pair-switch1.c
+++ /dev/null
@@ -1,16 +0,0 @@
-/* { dg-do compile } */
-/* { dg-require-effective-target power10_ok } */
-/* { dg-options "-mdejagnu-cpu=power10 -O2" } */
-
-/* Test if we generate load and store vector pair by default on power 10. */
-
-void
-test (__vector_pair *p, __vector_pair *q)
-{
- *p = *q;
-}
-
-/* { dg-final { scan-assembler-times {\mp?lxvpx?\M} 1 } } */
-/* { dg-final { scan-assembler-times {\mp?stxvpx?\M} 1 } } */
-/* { dg-final { scan-assembler-not {\mp?lxvx?\M} } } */
-/* { dg-final { scan-assembler-not {\mp?stxvx?\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vector-pair-switch2.c b/gcc/testsuite/gcc.target/powerpc/vector-pair-switch2.c
deleted file mode 100644
index 7097168bb07..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vector-pair-switch2.c
+++ /dev/null
@@ -1,17 +0,0 @@
-/* { dg-do compile } */
-/* { dg-require-effective-target power10_ok } */
-/* { dg-options "-mdejagnu-cpu=power10 -O2 -mno-store-vector-pair" } */
-
-/* Test if we generate load vector pair but not store vector pair if
- -mno-store-vector-pair is used on power10. */
-
-void
-test (__vector_pair *p, __vector_pair *q)
-{
- *p = *q;
-}
-
-/* { dg-final { scan-assembler-times {\mp?lxvpx?\M} 1 } } */
-/* { dg-final { scan-assembler-not {\mp?stxvpx?\M} } } */
-/* { dg-final { scan-assembler-not {\mp?lxvx?\M} } } */
-/* { dg-final { scan-assembler-times {\mp?stxvx?\M} 2 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vector-pair-switch3.c b/gcc/testsuite/gcc.target/powerpc/vector-pair-switch3.c
deleted file mode 100644
index d056fb82ee0..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vector-pair-switch3.c
+++ /dev/null
@@ -1,17 +0,0 @@
-/* { dg-do compile } */
-/* { dg-require-effective-target power10_ok } */
-/* { dg-options "-mdejagnu-cpu=power10 -O2 -mno-load-vector-pair" } */
-
-/* Test if we do not generate load vector pair but generate store vector pair
- if -mno-load-vector-pair is used on power10. */
-
-void
-test (__vector_pair *p, __vector_pair *q)
-{
- *p = *q;
-}
-
-/* { dg-final { scan-assembler-not {\mp?lxvpx?\M} } } */
-/* { dg-final { scan-assembler-times {\mp?stxvpx?\M} 1 } } */
-/* { dg-final { scan-assembler-times {\mp?lxvx?\M} 2 } } */
-/* { dg-final { scan-assembler-not {\mp?stxvx?\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vector-pair-switch4.c b/gcc/testsuite/gcc.target/powerpc/vector-pair-switch4.c
deleted file mode 100644
index 1d2d48e5f3b..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vector-pair-switch4.c
+++ /dev/null
@@ -1,17 +0,0 @@
-/* { dg-do compile } */
-/* { dg-require-effective-target power10_ok } */
-/* { dg-options "-mdejagnu-cpu=power10 -O2 -mno-load-vector-pair -mno-store-vector-pair" } */
-
-/* Test if we do not generate load and store vector pair if directed to on
- power 10. */
-
-void
-test (__vector_pair *p, __vector_pair *q)
-{
- *p = *q;
-}
-
-/* { dg-final { scan-assembler-not {\mp?lxvpx?\M} } } */
-/* { dg-final { scan-assembler-not {\mp?stxvpx?\M} } } */
-/* { dg-final { scan-assembler-times {\mp?lxvx?\M} 2 } } */
-/* { dg-final { scan-assembler-times {\mp?stxvx?\M} 2 } } */
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