[gcc(refs/users/meissner/heads/work121)] Allow variable element vec_extract to be loaded into vector registers.

[Michael Meissner]

https://gcc.gnu.org/g:29a9b204b3bae53f0a74ee9d3922e1334f6106b6

commit 29a9b204b3bae53f0a74ee9d3922e1334f6106b6
Author: Michael Meissner <meissner@linux.ibm.com>
Date:   Fri May 12 17:51:36 2023 -0400

    Allow variable element vec_extract to be loaded into vector registers.
    
    This patch allows vec_extract of V4SI, V8HI, and V16QI vector types with a
    variable element number to be loaded into vector registers directly.
    
    2023-05-12   Michael Meissner  <meissner@linux.ibm.com>
    
    gcc/
    
            * config/rs6000/vsx.md (VSX_EX_ISA): New mode attribute.
            (vsx_extract_<mode>_var_load): Allow vector registers to be loaded.

Diff:
---
 gcc/config/rs6000/vsx.md | 24 ++++++++++++++++--------
 1 file changed, 16 insertions(+), 8 deletions(-)

diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index 8687a316b9d..b873e600ad2 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -223,6 +223,12 @@
 			  (V8HI  "v")
 			  (V4SI  "wa")])
 
+;; Mode attribute to give the isa constraint for accessing Altivec registers
+;; with vector extract and insert operations.
+(define_mode_attr VSX_EX_ISA [(V16QI "p9v")
+			      (V8HI  "p9v")
+			      (V4SI  "p8v")])
+
 ;; Mode iterator for binary floating types other than double to
 ;; optimize convert to that floating point type from an extract
 ;; of an integer type
@@ -4046,23 +4052,25 @@
 }
   [(set_attr "isa" "p9v,*")])
 
-;; Variable V16QI/V8HI/V4SI extract from memory
+;; Variable V16QI/V8HI/V4SI extract from memory.
 (define_insn_and_split "*vsx_extract_<mode>_var_load"
-  [(set (match_operand:<VEC_base> 0 "gpc_reg_operand" "=r")
+  [(set (match_operand:<VEC_base> 0 "gpc_reg_operand" "=r,wa")
 	(unspec:<VEC_base>
-	 [(match_operand:VSX_EXTRACT_I 1 "memory_operand" "Q")
-	  (match_operand:DI 2 "gpc_reg_operand" "r")]
+	 [(match_operand:VSX_EXTRACT_I 1 "memory_operand" "Q,Q")
+	  (match_operand:DI 2 "gpc_reg_operand" "r,r")]
 	 UNSPEC_VSX_EXTRACT))
-   (clobber (match_scratch:DI 3 "=&b"))]
+   (clobber (match_scratch:DI 3 "=&b,&b"))]
   "VECTOR_MEM_VSX_P (<MODE>mode) && TARGET_DIRECT_MOVE_64BIT"
   "#"
   "&& reload_completed"
   [(set (match_dup 0) (match_dup 4))]
 {
-  operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
-					   operands[3], <VEC_base>mode);
+  operands[4] = rs6000_adjust_vec_address (operands[0], operands[1],
+					   operands[2], operands[3],
+					   <VEC_base>mode);
 }
-  [(set_attr "type" "load")])
+  [(set_attr "type" "load,fpload")
+   (set_attr "isa" "*,<VSX_EX_ISA>")])
 
 ;; Variable V4SI extract from memory with sign or zero conversion to DImode.
 (define_insn_and_split "*vsx_extract_v4si_var_load_to_<su>di"