[gcc/devel/jlaw/crc] NFC: Formatting fixes

[Jeff Law]

https://gcc.gnu.org/g:ea6aa4d94659e28881465532ca3b0d5a67bb166f

commit ea6aa4d94659e28881465532ca3b0d5a67bb166f
Author: Jeff Law <jlaw@ventanamicro>
Date:   Tue Mar 21 09:18:44 2023 -0600

    NFC: Formatting fixes

Diff:
---
 gcc/config/riscv/bitmanip.md | 66 +++++++++++++++++++++++---------------------
 1 file changed, 35 insertions(+), 31 deletions(-)

diff --git a/gcc/config/riscv/bitmanip.md b/gcc/config/riscv/bitmanip.md
index 2a9202d60d2..974bf0b6270 100644
--- a/gcc/config/riscv/bitmanip.md
+++ b/gcc/config/riscv/bitmanip.md
@@ -658,8 +658,8 @@
 
 (define_insn "clmul<mode>3"
 [(set (match_operand:X 0 "register_operand" "=r")
-(clmul:X (match_operand:X 1 "register_operand" "r")
-(match_operand:X 2 "register_operand"  "r")))]
+      (clmul:X (match_operand:X 1 "register_operand" "r")
+               (match_operand:X 2 "register_operand"  "r")))]
 "TARGET_ZBC"
 "clmul\t%0,%1,%2"
 [(set_attr "type" "bitmanip")])
@@ -667,8 +667,8 @@
 
 (define_insn "clmulh<mode>3"
 [(set (match_operand:X 0 "register_operand" "=r")
-(plus:X (match_operand:X 1 "register_operand" " r")
-(match_operand:X 2 "register_operand" "r")))]
+      (plus:X (match_operand:X 1 "register_operand" " r")
+              (match_operand:X 2 "register_operand" "r")))]
 "TARGET_ZBC"
 "clmulh\t%0,%1,%2"
 [(set_attr "type" "bitmanip")])
@@ -676,38 +676,42 @@
 
 (define_insn "clmulr<mode>3"
 [(set (match_operand:X 0 "register_operand" "=r")
-(clmulr:X (match_operand:X 1 "register_operand" "r")
-(match_operand:X 2 "register_operand" "r")))]
+      (clmulr:X (match_operand:X 1 "register_operand" "r")
+                (match_operand:X 2 "register_operand" "r")))]
 "TARGET_ZBC"
 "clmulr\t%0,%1,%2"
 [(set_attr "type" "bitmanip")])
 
 (define_expand "crcqihi4"
 [(match_operand:HI 1)
-(match_operand:QI 2)
-(match_operand:HI 3)]
+ (match_operand:QI 2)
+ (match_operand:HI 3)]
 ""
 {
-if (TARGET_ZBC)
-  {
-     // Instruction sequence from slides.  Sizes need to be fixed.
-     rtx a0 = operands[1], a1 = operands[2];
-     unsigned HOST_WIDE_INT
-       q = gf2n_poly_long_div_quotient (UINTVAL (operands[3]));
-     rtx t0 = gen_rtx_CONST (SImode, GEN_INT (q));
-     rtx t1 = gen_rtx_CONST (SImode, operands[3]);
-     a0 = force_reg (SImode, gen_rtx_XOR (SImode, a0, a1));
-     a0 = force_reg (SImode, gen_rtx_CLMUL (SImode, a0, t0));
-     a0= force_reg (SImode, gen_rtx_ASHIFT (SImode, a0, GEN_INT (16)));
-     a0 = force_reg (SImode, gen_rtx_CLMUL (SImode, a0, t1));
-     a0 = force_reg (SImode, gen_rtx_LSHIFTRT (SImode, a0, GEN_INT (24)));
-     a0= force_reg (SImode, gen_rtx_ASHIFT (SImode, a0, GEN_INT (24)));
-     rtx tgt = simplify_gen_subreg (SImode, operands[0], HImode, 0);
-     emit_move_insn (tgt, a0);
-  }
-else
-  {
-    expand_crc_table_based (operands, QImode);
-  }
-DONE;
-})
\ No newline at end of file
+  if (TARGET_ZBC)
+    {
+      // Instruction sequence from slides.  Sizes need to be fixed.
+      rtx a0 = operands[1];
+      rtx a1 = operands[2];
+      unsigned HOST_WIDE_INT q
+        = gf2n_poly_long_div_quotient (UINTVAL (operands[3]));
+      rtx t0 = gen_rtx_CONST (SImode, GEN_INT (q));
+      rtx t1 = gen_rtx_CONST (SImode, operands[3]);
+      a0 = force_reg (SImode, gen_rtx_XOR (SImode, a0, a1));
+      a0 = force_reg (SImode, gen_rtx_CLMUL (SImode, a0, t0));
+      a0 = force_reg (SImode, gen_rtx_ASHIFT (SImode, a0, GEN_INT (16)));
+      a0 = force_reg (SImode, gen_rtx_CLMUL (SImode, a0, t1));
+      a0 = force_reg (SImode, gen_rtx_LSHIFTRT (SImode, a0, GEN_INT (24)));
+      a0 = force_reg (SImode, gen_rtx_ASHIFT (SImode, a0, GEN_INT (24)));
+      rtx tgt = simplify_gen_subreg (SImode, operands[0], HImode, 0);
+      emit_move_insn (tgt, a0);
+    }
+  else
+    {
+      /* If we do not have the ZBC extension (ie, no clmul), then
+         use a table based algorithm to implement the CRC.  */
+      expand_crc_table_based (operands, QImode);
+    }
+
+  DONE;
+})