[gcc(refs/vendors/riscv/heads/gcc-13-with-riscv-opts)] RISC-V: Split arguments of expand_vec_perm

[Jeff Law]

https://gcc.gnu.org/g:717961cb7bdabed041061f9aa2e3409a367a4382

commit 717961cb7bdabed041061f9aa2e3409a367a4382
Author: Juzhe-Zhong <juzhe.zhong@rivai.ai>
Date:   Sun Jun 4 17:25:03 2023 +0800

    RISC-V: Split arguments of expand_vec_perm
    
    Since the following patch will calls expand_vec_perm with
    splitted arguments, change the expand_vec_perm interface in
    this patch.
    
    gcc/ChangeLog:
    
            * config/riscv/autovec.md: Split arguments.
            * config/riscv/riscv-protos.h (expand_vec_perm): Ditto.
            * config/riscv/riscv-v.cc (expand_vec_perm): Ditto.

Diff:
---
 gcc/config/riscv/autovec.md     | 3 ++-
 gcc/config/riscv/riscv-protos.h | 2 +-
 gcc/config/riscv/riscv-v.cc     | 6 +-----
 3 files changed, 4 insertions(+), 7 deletions(-)

diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md
index 4fe0e3253dc..9f4492db23c 100644
--- a/gcc/config/riscv/autovec.md
+++ b/gcc/config/riscv/autovec.md
@@ -96,7 +96,8 @@
    (match_operand:<VINDEX> 3 "vector_perm_operand")]
   "TARGET_VECTOR && GET_MODE_NUNITS (<MODE>mode).is_constant ()"
   {
-    riscv_vector::expand_vec_perm (operands);
+    riscv_vector::expand_vec_perm (operands[0], operands[1],
+				   operands[2], operands[3]);
     DONE;
   }
 )
diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h
index d032f569a36..00e1b20c6c6 100644
--- a/gcc/config/riscv/riscv-protos.h
+++ b/gcc/config/riscv/riscv-protos.h
@@ -241,7 +241,7 @@ opt_machine_mode get_mask_mode (machine_mode);
 void expand_vec_series (rtx, rtx, rtx);
 void expand_vec_init (rtx, rtx);
 void expand_vcond (rtx *);
-void expand_vec_perm (rtx *);
+void expand_vec_perm (rtx, rtx, rtx, rtx);
 /* Rounding mode bitfield for fixed point VXRM.  */
 enum vxrm_field_enum
 {
diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
index 75cf00b7eba..382f95cdfce 100644
--- a/gcc/config/riscv/riscv-v.cc
+++ b/gcc/config/riscv/riscv-v.cc
@@ -2024,12 +2024,8 @@ emit_vlmax_masked_gather_mu_insn (rtx target, rtx op, rtx sel, rtx mask)
 /* Implement vec_perm<mode>.  */
 
 void
-expand_vec_perm (rtx *operands)
+expand_vec_perm (rtx target, rtx op0, rtx op1, rtx sel)
 {
-  rtx target = operands[0];
-  rtx op0 = operands[1];
-  rtx op1 = operands[2];
-  rtx sel = operands[3];
   machine_mode data_mode = GET_MODE (target);
   machine_mode sel_mode = GET_MODE (sel);